From 4470492ca3bf1fcb9015f0524a09d789407e5128 Mon Sep 17 00:00:00 2001 From: Samuel Sadok Date: Mon, 26 Feb 2018 13:37:44 -0800 Subject: [PATCH] update CubeMX files --- .gitattributes | 3 +- .../Device/ST/STM32F4xx/Include/stm32f405xx.h | 136 +- .../Device/ST/STM32F4xx/Include/stm32f4xx.h | 6 +- .../ST/STM32F4xx/Include/system_stm32f4xx.h | 2 - .../Inc/Legacy/stm32_hal_legacy.h | 622 ++-- .../STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h | 41 +- .../Inc/stm32f4xx_hal_adc.h | 72 +- .../Inc/stm32f4xx_hal_adc_ex.h | 18 +- .../Inc/stm32f4xx_hal_can.h | 765 ++--- .../Inc/stm32f4xx_hal_cortex.h | 2 - .../Inc/stm32f4xx_hal_def.h | 8 +- .../Inc/stm32f4xx_hal_dma.h | 50 +- .../Inc/stm32f4xx_hal_dma_ex.h | 2 - .../Inc/stm32f4xx_hal_flash.h | 12 +- .../Inc/stm32f4xx_hal_flash_ex.h | 2 - .../Inc/stm32f4xx_hal_flash_ramfunc.h | 2 - .../Inc/stm32f4xx_hal_gpio.h | 12 +- .../Inc/stm32f4xx_hal_gpio_ex.h | 2 - .../Inc/stm32f4xx_hal_pcd.h | 2 - .../Inc/stm32f4xx_hal_pcd_ex.h | 2 - .../Inc/stm32f4xx_hal_pwr.h | 18 +- .../Inc/stm32f4xx_hal_pwr_ex.h | 22 +- .../Inc/stm32f4xx_hal_rcc.h | 251 +- .../Inc/stm32f4xx_hal_rcc_ex.h | 220 +- .../Inc/stm32f4xx_hal_spi.h | 34 +- .../Inc/stm32f4xx_hal_tim.h | 100 +- .../Inc/stm32f4xx_hal_tim_ex.h | 2 - .../Inc/stm32f4xx_hal_uart.h | 52 +- .../Inc/stm32f4xx_ll_usb.h | 2 - .../STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c | 122 +- .../Src/stm32f4xx_hal_adc.c | 68 +- .../Src/stm32f4xx_hal_adc_ex.c | 44 +- .../Src/stm32f4xx_hal_can.c | 3054 +++++++++-------- .../Src/stm32f4xx_hal_cortex.c | 26 +- .../Src/stm32f4xx_hal_dma.c | 64 +- .../Src/stm32f4xx_hal_dma_ex.c | 36 +- .../Src/stm32f4xx_hal_flash.c | 58 +- .../Src/stm32f4xx_hal_flash_ex.c | 62 +- .../Src/stm32f4xx_hal_flash_ramfunc.c | 2 - .../Src/stm32f4xx_hal_gpio.c | 32 +- .../Src/stm32f4xx_hal_pcd.c | 108 +- .../Src/stm32f4xx_hal_pcd_ex.c | 30 +- .../Src/stm32f4xx_hal_pwr.c | 26 +- .../Src/stm32f4xx_hal_pwr_ex.c | 10 +- .../Src/stm32f4xx_hal_rcc.c | 557 +-- .../Src/stm32f4xx_hal_rcc_ex.c | 1600 +++++---- .../Src/stm32f4xx_hal_spi.c | 166 +- .../Src/stm32f4xx_hal_tim.c | 380 +- .../Src/stm32f4xx_hal_tim_ex.c | 154 +- .../Src/stm32f4xx_hal_uart.c | 124 +- .../Src/stm32f4xx_ll_usb.c | 174 +- Firmware/Board/v3.3/Inc/adc.h | 2 +- Firmware/Board/v3.3/Inc/can.h | 2 +- Firmware/Board/v3.3/Inc/dma.h | 2 +- Firmware/Board/v3.3/Inc/gpio.h | 2 +- Firmware/Board/v3.3/Inc/main.h | 39 +- Firmware/Board/v3.3/Inc/spi.h | 2 +- Firmware/Board/v3.3/Inc/stm32f4xx_hal_conf.h | 2 +- Firmware/Board/v3.3/Inc/stm32f4xx_it.h | 2 +- Firmware/Board/v3.3/Inc/tim.h | 2 +- Firmware/Board/v3.3/Inc/usart.h | 2 +- Firmware/Board/v3.3/Inc/usb_device.h | 65 +- Firmware/Board/v3.3/Inc/usbd_cdc_if.h | 75 +- Firmware/Board/v3.3/Inc/usbd_conf.h | 163 +- Firmware/Board/v3.3/Inc/usbd_desc.h | 109 +- Firmware/Board/v3.3/Makefile | 209 +- .../Class/CDC/Src/usbd_cdc.c | 4 +- .../FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c | 9 +- .../FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h | 8 +- .../FreeRTOS/Source/event_groups.c | 2 +- .../FreeRTOS/Source/include/event_groups.h | 26 +- .../FreeRTOS/Source/include/list.h | 10 +- .../FreeRTOS/Source/include/mpu_wrappers.h | 16 +- .../FreeRTOS/Source/include/portable.h | 22 +- .../FreeRTOS/Source/include/queue.h | 68 +- .../FreeRTOS/Source/include/task.h | 124 +- .../FreeRTOS/Source/include/timers.h | 30 +- .../Third_Party/FreeRTOS/Source/queue.c | 16 +- .../Third_Party/FreeRTOS/Source/tasks.c | 56 +- .../Third_Party/FreeRTOS/Source/timers.c | 28 +- Firmware/Board/v3.3/Odrive.ioc | 2 +- Firmware/Board/v3.3/Src/adc.c | 2 +- Firmware/Board/v3.3/Src/can.c | 20 +- Firmware/Board/v3.3/Src/dma.c | 2 +- Firmware/Board/v3.3/Src/freertos.c | 2 +- Firmware/Board/v3.3/Src/gpio.c | 20 +- Firmware/Board/v3.3/Src/main.c | 59 +- Firmware/Board/v3.3/Src/spi.c | 2 +- Firmware/Board/v3.3/Src/stm32f4xx_hal_msp.c | 2 +- .../v3.3/Src/stm32f4xx_hal_timebase_TIM.c | 2 +- Firmware/Board/v3.3/Src/stm32f4xx_it.c | 10 +- Firmware/Board/v3.3/Src/tim.c | 2 +- Firmware/Board/v3.3/Src/usart.c | 2 +- Firmware/Board/v3.3/Src/usb_device.c | 46 +- Firmware/Board/v3.3/Src/usbd_cdc_if.c | 170 +- Firmware/Board/v3.3/Src/usbd_conf.c | 211 +- Firmware/Board/v3.3/Src/usbd_desc.c | 418 ++- .../v3.3/{startup => }/startup_stm32f405xx.s | 2 - 98 files changed, 6222 insertions(+), 5208 deletions(-) rename Firmware/Board/v3.3/{startup => }/startup_stm32f405xx.s (99%) diff --git a/.gitattributes b/.gitattributes index ce4ac660..7010ebec 100644 --- a/.gitattributes +++ b/.gitattributes @@ -1,3 +1,4 @@ # CubeMX generates CRLF line endings -Firmware/Board/v3.3/** text eol=crlf +Firmware/Board/v3.3/**.c text eol=crlf +Firmware/Board/v3.3/**.h text eol=crlf diff --git a/Firmware/Board/v3.3/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h b/Firmware/Board/v3.3/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h index 1aa12c58..8f5c2c6f 100644 --- a/Firmware/Board/v3.3/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h +++ b/Firmware/Board/v3.3/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f405xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS STM32F405xx Device Peripheral Access Layer Header File. * * This file contains: @@ -169,9 +167,11 @@ typedef enum OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ + RNG_IRQn = 80, /*!< RNG global Interrupt */ FPU_IRQn = 81 /*!< FPU global interrupt */ } IRQn_Type; +/* Legacy define */ +#define HASH_RNG_IRQn RNG_IRQn /** * @} @@ -12205,7 +12205,7 @@ typedef struct #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!State = HAL_ADC_STATE_RESET) /** * @brief Enable the ADC peripheral. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON) /** * @brief Disable the ADC peripheral. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON) /** * @brief Enable the ADC end of conversion interrupt. - * @param __HANDLE__: specifies the ADC Handle. - * @param __INTERRUPT__: ADC Interrupt. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ ADC Interrupt. * @retval None */ #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__)) /** * @brief Disable the ADC end of conversion interrupt. - * @param __HANDLE__: specifies the ADC Handle. - * @param __INTERRUPT__: ADC interrupt. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ ADC interrupt. * @retval None */ #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__)) /** @brief Check if the specified ADC interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the ADC Handle. - * @param __INTERRUPT__: specifies the ADC interrupt source to check. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ specifies the ADC interrupt source to check. * @retval The new state of __IT__ (TRUE or FALSE). */ #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) /** * @brief Clear the ADC's pending flags. - * @param __HANDLE__: specifies the ADC Handle. - * @param __FLAG__: ADC flag. + * @param __HANDLE__ specifies the ADC Handle. + * @param __FLAG__ ADC flag. * @retval None */ #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) /** * @brief Get the selected ADC's flag status. - * @param __HANDLE__: specifies the ADC Handle. - * @param __FLAG__: ADC flag. + * @param __HANDLE__ specifies the ADC Handle. + * @param __FLAG__ ADC flag. * @retval None */ #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) @@ -616,7 +614,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @brief Verification of ADC state: enabled or disabled - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (ADC enabled) or RESET (ADC disabled) */ #define ADC_IS_ENABLE(__HANDLE__) \ @@ -626,7 +624,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @brief Test if conversion trigger of regular group is software start * or external trigger. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (software start) or RESET (external trigger) */ #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ @@ -635,7 +633,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @brief Test if conversion trigger of injected group is software start * or external trigger. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (software start) or RESET (external trigger) */ #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ @@ -652,7 +650,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @brief Clear ADC error code (set it to error code: "no error") - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ @@ -742,89 +740,89 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @brief Set ADC Regular channel sequence length. - * @param _NbrOfConversion_: Regular channel sequence length. + * @param _NbrOfConversion_ Regular channel sequence length. * @retval None */ #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U) /** * @brief Set the ADC's sample time for channel numbers between 10 and 18. - * @param _SAMPLETIME_: Sample time parameter. - * @param _CHANNELNB_: Channel number. + * @param _SAMPLETIME_ Sample time parameter. + * @param _CHANNELNB_ Channel number. * @retval None */ #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U))) /** * @brief Set the ADC's sample time for channel numbers between 0 and 9. - * @param _SAMPLETIME_: Sample time parameter. - * @param _CHANNELNB_: Channel number. + * @param _SAMPLETIME_ Sample time parameter. + * @param _CHANNELNB_ Channel number. * @retval None */ #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_))))) /** * @brief Set the selected regular channel rank for rank between 1 and 6. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U))) /** * @brief Set the selected regular channel rank for rank between 7 and 12. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U))) /** * @brief Set the selected regular channel rank for rank between 13 and 16. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U))) /** * @brief Enable ADC continuous conversion mode. - * @param _CONTINUOUS_MODE_: Continuous mode. + * @param _CONTINUOUS_MODE_ Continuous mode. * @retval None */ #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U) /** * @brief Configures the number of discontinuous conversions for the regular group channels. - * @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions. + * @param _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions. * @retval None */ -#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << POSITION_VAL(ADC_CR1_DISCNUM)) +#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << ADC_CR1_DISCNUM_Pos) /** * @brief Enable ADC scan mode. - * @param _SCANCONV_MODE_: Scan conversion mode. + * @param _SCANCONV_MODE_ Scan conversion mode. * @retval None */ #define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U) /** * @brief Enable the ADC end of conversion selection. - * @param _EOCSelection_MODE_: End of conversion selection mode. + * @param _EOCSelection_MODE_ End of conversion selection mode. * @retval None */ #define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U) /** * @brief Enable the ADC DMA continuous request. - * @param _DMAContReq_MODE_: DMA continuous request mode. + * @param _DMAContReq_MODE_ DMA continuous request mode. * @retval None */ #define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U) /** * @brief Return resolution bits in CR1 register. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES) diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h index 77173646..523eaae0 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_adc_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of ADC HAL module. ****************************************************************************** * @attention @@ -232,10 +230,14 @@ typedef struct #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \ defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \ - defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + defined(STM32F412Cx) #define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16) #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F412Zx || - STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ + STM32F412Vx || STM32F412Rx || STM32F412Cx */ + +#if defined(STM32F413xx) || defined(STM32F423xx) +#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18) +#endif /* STM32F413xx || STM32F423xx */ #if defined(STM32F411xE) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) @@ -377,9 +379,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /** * @brief Set the selected injected Channel rank. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. - * @param _JSQR_JL_: Sequence length. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. + * @param _JSQR_JL_ Sequence length. * @retval None */ #define ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * (uint8_t)(((_RANKNB_) + 3U) - (_JSQR_JL_)))) @@ -387,7 +389,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /** * @brief Defines if the selected ADC is within ADC common register ADC123 or ADC1 * if available (ADC2, ADC3 availability depends on STM32 product) - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval Common control register ADC123 or ADC1 */ #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h index c540ce6d..379090a3 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h @@ -2,13 +2,11 @@ ****************************************************************************** * @file stm32f4xx_hal_can.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of CAN HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -36,18 +34,13 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_CAN_H -#define __STM32F4xx_HAL_CAN_H +#ifndef STM32F4xx_HAL_CAN_H +#define STM32F4xx_HAL_CAN_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ - defined(STM32F423xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -55,6 +48,7 @@ * @{ */ +#if defined (CAN1) /** @addtogroup CAN * @{ */ @@ -63,7 +57,6 @@ /** @defgroup CAN_Exported_Types CAN Exported Types * @{ */ - /** * @brief HAL State structures definition */ @@ -71,59 +64,53 @@ typedef enum { HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ - HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */ - HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */ - HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ + HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */ + HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */ + HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */ + HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */ -}HAL_CAN_StateTypeDef; +} HAL_CAN_StateTypeDef; /** * @brief CAN init structure definition */ typedef struct { - uint32_t Prescaler; /*!< Specifies the length of a time quantum. - This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ + uint32_t Prescaler; /*!< Specifies the length of a time quantum. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ - uint32_t Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of @ref CAN_operating_mode */ + uint32_t Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ - uint32_t SJW; /*!< Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or - shorten a bit to perform resynchronization. - This parameter can be a value of @ref CAN_synchronisation_jump_width */ + uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware + is allowed to lengthen or shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ - uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ - uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ - uint32_t TTCM; /*!< Enable or disable the time triggered communication mode. - This parameter can be set to ENABLE or DISABLE. */ + FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t ABOM; /*!< Enable or disable the automatic bus-off management. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set to ENABLE or DISABLE. */ - uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority. - This parameter can be set to ENABLE or DISABLE */ -}CAN_InitTypeDef; + FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority. + This parameter can be set to ENABLE or DISABLE. */ + +} CAN_InitTypeDef; /** * @brief CAN filter configuration structure definition @@ -132,27 +119,30 @@ typedef struct { uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. This parameter can be a value of @ref CAN_filter_FIFO */ - uint32_t FilterNumber; /*!< Specifies the filter which will be initialized. - This parameter must be a number between Min_Data = 0 and Max_Data = 27 */ + uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized. + For single CAN instance(14 dedicated filter banks), + this parameter must be a number between Min_Data = 0 and Max_Data = 13. + For dual CAN instances(28 filter banks shared), + this parameter must be a number between Min_Data = 0 and Max_Data = 27. */ uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. This parameter can be a value of @ref CAN_filter_mode */ @@ -163,95 +153,94 @@ typedef struct uint32_t FilterActivation; /*!< Enable or disable the filter. This parameter can be set to ENABLE or DISABLE. */ - uint32_t BankNumber; /*!< Select the start slave bank filter. - This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ + uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance. + For single CAN instances, this parameter is meaningless. + For dual CAN instances, all filter banks with lower index are assigned to master + CAN instance, whereas all filter banks with greater index are assigned to slave + CAN instance. + This parameter must be a number between Min_Data = 0 and Max_Data = 27. */ -}CAN_FilterConfTypeDef; +} CAN_FilterTypeDef; /** - * @brief CAN Tx message structure definition + * @brief CAN Tx message header structure definition */ typedef struct { uint32_t StdId; /*!< Specifies the standard identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. - This parameter can be a value of @ref CAN_Identifier_Type */ + This parameter can be a value of @ref CAN_identifier_type */ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. This parameter can be a value of @ref CAN_remote_transmission_request */ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. - This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - uint8_t Data[8]; /*!< Contains the data to be transmitted. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start + of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7]. + @note: Time Triggered Communication Mode must be enabled. + @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent. + This parameter can be set to ENABLE or DISABLE. */ -}CanTxMsgTypeDef; +} CAN_TxHeaderTypeDef; /** - * @brief CAN Rx message structure definition + * @brief CAN Rx message header structure definition */ typedef struct { - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ - uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received. - This parameter can be a value of @ref CAN_Identifier_Type */ + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ - uint32_t RTR; /*!< Specifies the type of frame for the received message. - This parameter can be a value of @ref CAN_remote_transmission_request */ + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ - uint32_t DLC; /*!< Specifies the length of the frame that will be received. - This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - uint8_t Data[8]; /*!< Contains the data to be received. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception. + @note: Time Triggered Communication Mode must be enabled. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */ - uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ - uint32_t FIFONumber; /*!< Specifies the receive FIFO number. - This parameter can be CAN_FIFO0 or CAN_FIFO1 */ - -}CanRxMsgTypeDef; +} CAN_RxHeaderTypeDef; /** * @brief CAN handle Structure definition */ -typedef struct +typedef struct __CAN_HandleTypeDef { - CAN_TypeDef *Instance; /*!< Register base address */ + CAN_TypeDef *Instance; /*!< Register base address */ - CAN_InitTypeDef Init; /*!< CAN required parameters */ + CAN_InitTypeDef Init; /*!< CAN required parameters */ - CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ + __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ - CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */ + __IO uint32_t ErrorCode; /*!< CAN Error code. + This parameter can be a value of @ref CAN_Error_Code */ - CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */ - - __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ - - HAL_LockTypeDef Lock; /*!< CAN locking object */ - - __IO uint32_t ErrorCode; /*!< CAN Error code */ - -}CAN_HandleTypeDef; +} CAN_HandleTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ + /** @defgroup CAN_Exported_Constants CAN Exported Constants * @{ */ @@ -259,19 +248,30 @@ typedef struct /** @defgroup CAN_Error_Code CAN Error Code * @{ */ -#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */ -#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */ -#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */ -#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */ -#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */ -#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */ -#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */ -#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */ -#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */ -#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */ -#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */ -#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */ -#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */ +#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */ +#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */ +#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */ +#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ +#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */ +#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */ +#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */ +#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */ +#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */ +#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ +#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */ +#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */ +#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */ +#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */ + /** * @} */ @@ -279,8 +279,8 @@ typedef struct /** @defgroup CAN_InitStatus CAN InitStatus * @{ */ -#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */ -#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */ +#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */ /** * @} */ @@ -288,7 +288,7 @@ typedef struct /** @defgroup CAN_operating_mode CAN Operating Mode * @{ */ -#define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */ +#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ @@ -296,10 +296,11 @@ typedef struct * @} */ -/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width + +/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width * @{ */ -#define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */ +#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ @@ -307,10 +308,10 @@ typedef struct * @} */ -/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1 +/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 * @{ */ -#define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */ +#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ @@ -330,10 +331,10 @@ typedef struct * @} */ -/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2 +/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 * @{ */ -#define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */ +#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ @@ -345,11 +346,11 @@ typedef struct * @} */ -/** @defgroup CAN_filter_mode CAN Filter Mode +/** @defgroup CAN_filter_mode CAN Filter Mode * @{ */ -#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */ -#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */ +#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */ /** * @} */ @@ -357,8 +358,8 @@ typedef struct /** @defgroup CAN_filter_scale CAN Filter Scale * @{ */ -#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ -#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ +#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */ /** * @} */ @@ -366,17 +367,17 @@ typedef struct /** @defgroup CAN_filter_FIFO CAN Filter FIFO * @{ */ -#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */ /** * @} */ -/** @defgroup CAN_Identifier_Type CAN Identifier Type +/** @defgroup CAN_identifier_type CAN Identifier Type * @{ */ -#define CAN_ID_STD 0x00000000U /*!< Standard Id */ -#define CAN_ID_EXT 0x00000004U /*!< Extended Id */ +#define CAN_ID_STD (0x00000000U) /*!< Standard Id */ +#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ /** * @} */ @@ -384,17 +385,27 @@ typedef struct /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request * @{ */ -#define CAN_RTR_DATA 0x00000000U /*!< Data frame */ -#define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */ +#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ +#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ /** * @} */ -/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants +/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number * @{ */ -#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ +#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */ +#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */ +/** + * @} + */ + +/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes + * @{ + */ +#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */ +#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */ +#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */ /** * @} */ @@ -402,80 +413,72 @@ typedef struct /** @defgroup CAN_flags CAN Flags * @{ */ -/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() - and CAN_ClearFlag() functions. */ -/* If the flag is 0x1XXXXXXX, it means that it can only be used with - CAN_GetFlagStatus() function. */ - /* Transmit Flags */ -#define CAN_FLAG_RQCP0 0x00000500U /*!< Request MailBox0 flag */ -#define CAN_FLAG_RQCP1 0x00000508U /*!< Request MailBox1 flag */ -#define CAN_FLAG_RQCP2 0x00000510U /*!< Request MailBox2 flag */ -#define CAN_FLAG_TXOK0 0x00000501U /*!< Transmission OK MailBox0 flag */ -#define CAN_FLAG_TXOK1 0x00000509U /*!< Transmission OK MailBox1 flag */ -#define CAN_FLAG_TXOK2 0x00000511U /*!< Transmission OK MailBox2 flag */ -#define CAN_FLAG_TME0 0x0000051AU /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME1 0x0000051BU /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME2 0x0000051CU /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */ +#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */ +#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */ +#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */ +#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */ +#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */ +#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */ +#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */ +#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */ +#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */ +#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */ +#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */ +#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */ +#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */ +#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */ +#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */ +#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */ /* Receive Flags */ -#define CAN_FLAG_FF0 0x00000203U /*!< FIFO 0 Full flag */ -#define CAN_FLAG_FOV0 0x00000204U /*!< FIFO 0 Overrun flag */ - -#define CAN_FLAG_FF1 0x00000403U /*!< FIFO 1 Full flag */ -#define CAN_FLAG_FOV1 0x00000404U /*!< FIFO 1 Overrun flag */ +#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */ +#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */ /* Operating Mode Flags */ -#define CAN_FLAG_INAK 0x00000100U /*!< Initialization acknowledge flag */ -#define CAN_FLAG_SLAK 0x00000101U /*!< Sleep acknowledge flag */ -#define CAN_FLAG_ERRI 0x00000102U /*!< Error flag */ -#define CAN_FLAG_WKU 0x00000103U /*!< Wake up flag */ -#define CAN_FLAG_SLAKI 0x00000104U /*!< Sleep acknowledge flag */ - -/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. - In this case the SLAK bit can be polled.*/ +#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ +#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ +#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */ +#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */ /* Error Flags */ -#define CAN_FLAG_EWG 0x00000300U /*!< Error warning flag */ -#define CAN_FLAG_EPV 0x00000301U /*!< Error passive flag */ -#define CAN_FLAG_BOF 0x00000302U /*!< Bus-Off flag */ +#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ +#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ +#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ /** * @} */ + /** @defgroup CAN_Interrupts CAN Interrupts * @{ */ -#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ +/* Transmit Interrupt */ +#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ /* Receive Interrupts */ -#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ -#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ -#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ -#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ -#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ -#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ +#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ +#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ +#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ +#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ +#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ +#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ /* Operating Mode Interrupts */ -#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ -#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ +#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ +#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ /* Error Interrupts */ -#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ -#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ -#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ -#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ -#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ -/** - * @} - */ - -/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition - * @{ - */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) +#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ +#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ +#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ +#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ +#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ /** * @} */ @@ -484,213 +487,198 @@ typedef struct * @} */ -/* Exported macro ------------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ /** @defgroup CAN_Exported_Macros CAN Exported Macros * @{ */ -/** @brief Reset CAN handle state - * @param __HANDLE__: specifies the CAN Handle. +/** @brief Reset CAN handle state + * @param __HANDLE__ CAN handle. * @retval None */ #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) /** * @brief Enable the specified CAN interrupts. - * @param __HANDLE__: CAN handle - * @param __INTERRUPT__: CAN Interrupt + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to enable. + * This parameter can be any combination of @arg CAN_Interrupts * @retval None */ #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) /** * @brief Disable the specified CAN interrupts. - * @param __HANDLE__: CAN handle - * @param __INTERRUPT__: CAN Interrupt + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to disable. + * This parameter can be any combination of @arg CAN_Interrupts * @retval None */ #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) -/** - * @brief Return the number of pending received messages. - * @param __HANDLE__: CAN handle - * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval The number of pending message. +/** @brief Check if the specified CAN interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the CAN Handle. + * @param __INTERRUPT__ specifies the CAN interrupt source to check. + * This parameter can be a value of @arg CAN_Interrupts + * @retval The state of __IT__ (TRUE or FALSE). */ -#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U))) +#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__)) /** @brief Check whether the specified CAN flag is set or not. - * @param __HANDLE__: CAN Handle - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg CAN_TSR_RQCP0: Request MailBox0 Flag - * @arg CAN_TSR_RQCP1: Request MailBox1 Flag - * @arg CAN_TSR_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag - * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag - * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag - * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag - * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag - * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag - * @arg CAN_FLAG_EWG: Error Warning Flag - * @arg CAN_FLAG_EPV: Error Passive Flag - * @arg CAN_FLAG_BOF: Bus-Off Flag - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of @arg CAN_flags + * @retval The state of __FLAG__ (TRUE or FALSE). */ #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) + ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) /** @brief Clear the specified CAN pending flag. - * @param __HANDLE__: CAN Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - * @arg CAN_TSR_RQCP0: Request MailBox0 Flag - * @arg CAN_TSR_RQCP1: Request MailBox1 Flag - * @arg CAN_TSR_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag - * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag - * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag - * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag - * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag - * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag + * @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag + * @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag + * @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag + * @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag + * @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag + * @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag + * @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag + * @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag + * @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag + * @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKUI: Wake up Interrupt Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag + * @retval None */ #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__HANDLE__)->Instance->MSR) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK)))) - -/** @brief Check if the specified CAN interrupt source is enabled or disabled. - * @param __HANDLE__: CAN Handle - * @param __INTERRUPT__: specifies the CAN interrupt source to check. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable - * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable - * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) /** - * @brief Check the transmission status of a CAN Frame. - * @param __HANDLE__: CAN Handle - * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. - * @retval The new status of transmission (TRUE or FALSE). - */ -#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\ - ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2))) - -/** - * @brief Release the specified receive FIFO. - * @param __HANDLE__: CAN handle - * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval None - */ -#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1)) - -/** - * @brief Cancel a transmit request. - * @param __HANDLE__: CAN Handle - * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. - * @retval None - */ -#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\ - ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2)) - -/** - * @brief Enable or disable the DBG Freeze for CAN. - * @param __HANDLE__: CAN Handle - * @param __NEWSTATE__: new state of the CAN peripheral. - * This parameter can be: ENABLE (CAN reception/transmission is frozen - * during debug. Reception FIFOs can still be accessed/controlled normally) - * or DISABLE (CAN is working during debug). - * @retval None - */ -#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ -((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) - -/** - * @} - */ + * @} + */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup CAN_Exported_Functions +/** @addtogroup CAN_Exported_Functions CAN Exported Functions * @{ */ -/** @addtogroup CAN_Exported_Functions_Group1 - * @{ - */ -/* Initialization/de-initialization functions ***********************************/ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); -void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); -void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); +/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); + /** - * @} - */ + * @} + */ -/** @addtogroup CAN_Exported_Functions_Group2 - * @{ - */ -/* I/O operation functions ******************************************************/ -HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); -HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); -HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); -HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); +/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions + * @{ + */ + +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * @{ + */ + +/* Control functions **********************************************************/ +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); -void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); -void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); -void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); +uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox); +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox); +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); +uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * @{ + */ +/* Interrupts management ******************************************************/ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs); +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs); +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group5 Callback functions + * @brief Callback functions + * @{ + */ +/* Callbacks functions ********************************************************/ + +void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan); void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); -/** - * @} - */ -/** @addtogroup CAN_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State functions ***************************************************/ +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan); uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); -/** - * @} - */ +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); /** - * @} - */ + * @} + */ + +/** + * @} + */ /* Private types -------------------------------------------------------------*/ /** @defgroup CAN_Private_Types CAN Private Types @@ -708,71 +696,80 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); /** * @} - */ + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup CAN_Private_Constants CAN Private Constants * @{ */ -#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ -#define CAN_FLAG_MASK 0x000000FFU +#define CAN_FLAG_MASK (0x000000FFU) /** * @} */ -/* Private macros ------------------------------------------------------------*/ +/* Private Macros -----------------------------------------------------------*/ /** @defgroup CAN_Private_Macros CAN Private Macros * @{ */ + #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ ((MODE) == CAN_MODE_LOOPBACK)|| \ ((MODE) == CAN_MODE_SILENT) || \ ((MODE) == CAN_MODE_SILENT_LOOPBACK)) -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) +#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \ + ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \ + ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \ + ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \ + ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \ + ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \ + ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \ + ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ)) +#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \ + ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \ + ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \ + ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ)) #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) -#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U) +#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU) +#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U) +#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U) #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ ((MODE) == CAN_FILTERMODE_IDLIST)) #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ ((SCALE) == CAN_FILTERSCALE_32BIT)) #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ ((FIFO) == CAN_FILTER_FIFO1)) -#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U) - -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) -#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FFU)) +#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 )) +#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2)) +#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) #define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) - +#define IS_CAN_DLC(DLC) ((DLC) <= 8U) #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ ((IDTYPE) == CAN_ID_EXT)) #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) +#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1)) +#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \ + CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \ + CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \ + CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \ + CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \ + CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \ + CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR)) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ /** * @} */ -/* Private functions ---------------------------------------------------------*/ -/** @defgroup CAN_Private_Functions CAN Private Functions - * @{ - */ - -/** - * @} - */ - -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ - STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ - STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ - -/** - * @} - */ +#endif /* CAN1 */ /** * @} */ @@ -781,7 +778,7 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); } #endif -#endif /* __STM32F4xx_CAN_H */ +#endif /* STM32F4xx_HAL_CAN_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h index 53134d31..da3454b7 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_cortex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h index b9fd4170..06414648 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_def.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** @@ -86,7 +84,7 @@ typedef enum #define UNUSED(x) ((void)(x)) /** @brief Reset the Handle's State field. - * @param __HANDLE__: specifies the Peripheral Handle. + * @param __HANDLE__ specifies the Peripheral Handle. * @note This macro can be used for the following purpose: * - When the Handle is declared as local variable; before passing it as parameter * to HAL_PPP_Init() for the first time, it is mandatory to use this macro @@ -124,7 +122,7 @@ typedef enum }while (0U) #endif /* USE_RTOS */ -#if defined ( __GNUC__ ) +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ @@ -135,7 +133,7 @@ typedef enum /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined (__GNUC__) /* GNU Compiler */ +#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4))) #endif /* __ALIGN_END */ diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h index 18cc962d..75a8cc7f 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dma.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention @@ -378,8 +376,8 @@ typedef struct __DMA_HandleTypeDef * @brief DMA flag definitions * @{ */ -#define DMA_FLAG_FEIF0_4 0x00800001U -#define DMA_FLAG_DMEIF0_4 0x00800004U +#define DMA_FLAG_FEIF0_4 0x00000001U +#define DMA_FLAG_DMEIF0_4 0x00000004U #define DMA_FLAG_TEIF0_4 0x00000008U #define DMA_FLAG_HTIF0_4 0x00000010U #define DMA_FLAG_TCIF0_4 0x00000020U @@ -409,14 +407,14 @@ typedef struct __DMA_HandleTypeDef /* Exported macro ------------------------------------------------------------*/ /** @brief Reset DMA handle state - * @param __HANDLE__: specifies the DMA handle. + * @param __HANDLE__ specifies the DMA handle. * @retval None */ #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) /** * @brief Return the current DMA Stream FIFO filled level. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The FIFO filling state. * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full * and not empty. @@ -430,14 +428,14 @@ typedef struct __DMA_HandleTypeDef /** * @brief Enable the specified DMA Stream. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) /** * @brief Disable the specified DMA Stream. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval None */ #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) @@ -446,7 +444,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Return the current DMA Stream transfer complete flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer complete flag index. */ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ @@ -466,7 +464,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Return the current DMA Stream half transfer complete flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified half transfer complete flag index. */ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ @@ -486,7 +484,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Return the current DMA Stream transfer error flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified transfer error flag index. */ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ @@ -506,7 +504,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Return the current DMA Stream FIFO error flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified FIFO error flag index. */ #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ @@ -526,7 +524,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Return the current DMA Stream direct mode error flag. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * @retval The specified direct mode error flag index. */ #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ @@ -546,8 +544,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Get the DMA Stream pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: Get the specified flag. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCIFx: Transfer complete flag. * @arg DMA_FLAG_HTIFx: Half transfer complete flag. @@ -564,8 +562,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Clear the DMA Stream pending flags. - * @param __HANDLE__: DMA handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCIFx: Transfer complete flag. * @arg DMA_FLAG_HTIFx: Half transfer complete flag. @@ -582,8 +580,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Enable the specified DMA Stream interrupts. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask. * @arg DMA_IT_HT: Half transfer complete interrupt mask. @@ -597,8 +595,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Disable the specified DMA Stream interrupts. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask. * @arg DMA_IT_HT: Half transfer complete interrupt mask. @@ -612,8 +610,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Check whether the specified DMA Stream interrupt is enabled or disabled. - * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt source to check. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt source to check. * This parameter can be one of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask. * @arg DMA_IT_HT: Half transfer complete interrupt mask. @@ -628,8 +626,8 @@ typedef struct __DMA_HandleTypeDef /** * @brief Writes the number of data units to be transferred on the DMA Stream. - * @param __HANDLE__: DMA handle - * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535) + * @param __HANDLE__ DMA handle + * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535) * Number of data items depends only on the Peripheral data format. * * @note If Peripheral data format is Bytes: number of data units is equal @@ -647,7 +645,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. - * @param __HANDLE__: DMA handle + * @param __HANDLE__ DMA handle * * @retval The number of remaining data units in the current DMA Stream transfer. */ diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h index 501968a3..b32e8377 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dma_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h index 38f2db87..ed8538d9 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_flash.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of FLASH HAL module. ****************************************************************************** * @attention @@ -189,7 +187,7 @@ typedef struct */ /** * @brief Set the FLASH Latency. - * @param __LATENCY__: FLASH Latency + * @param __LATENCY__ FLASH Latency * The value of this parameter depend on device used within the same series * @retval none */ @@ -257,7 +255,7 @@ typedef struct }while(0U) /** * @brief Enable the specified FLASH interrupt. - * @param __INTERRUPT__ : FLASH interrupt + * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt * @arg FLASH_IT_ERR: Error Interrupt @@ -267,7 +265,7 @@ typedef struct /** * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__ : FLASH interrupt + * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt * @arg FLASH_IT_ERR: Error Interrupt @@ -277,7 +275,7 @@ typedef struct /** * @brief Get the specified FLASH flag status. - * @param __FLAG__: specifies the FLASH flags to check. + * @param __FLAG__ specifies the FLASH flags to check. * This parameter can be any combination of the following values: * @arg FLASH_FLAG_EOP : FLASH End of Operation flag * @arg FLASH_FLAG_OPERR : FLASH operation Error flag @@ -294,7 +292,7 @@ typedef struct /** * @brief Clear the specified FLASH flags. - * @param __FLAG__: specifies the FLASH flags to clear. + * @param __FLAG__ specifies the FLASH flags to clear. * This parameter can be any combination of the following values: * @arg FLASH_FLAG_EOP : FLASH End of Operation flag * @arg FLASH_FLAG_OPERR : FLASH operation Error flag diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h index 27df2c7e..d498b90c 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_flash_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of FLASH HAL Extension module. ****************************************************************************** * @attention diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h index 529a6d63..500d33ad 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_flash_ramfunc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of FLASH RAMFUNC driver. ****************************************************************************** * @attention diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h index b1f3269e..6a850df9 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_gpio.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention @@ -187,7 +185,7 @@ typedef enum /** * @brief Checks whether the specified EXTI line flag is set or not. - * @param __EXTI_LINE__: specifies the EXTI line flag to check. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ @@ -195,7 +193,7 @@ typedef enum /** * @brief Clears the EXTI's line pending flags. - * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ @@ -203,7 +201,7 @@ typedef enum /** * @brief Checks whether the specified EXTI line is asserted or not. - * @param __EXTI_LINE__: specifies the EXTI line to check. + * @param __EXTI_LINE__ specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ @@ -211,7 +209,7 @@ typedef enum /** * @brief Clears the EXTI's line pending bits. - * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ @@ -219,7 +217,7 @@ typedef enum /** * @brief Generates a Software interrupt on selected EXTI line. - * @param __EXTI_LINE__: specifies the EXTI line to check. + * @param __EXTI_LINE__ specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval None */ diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h index 620fa583..b958e4b9 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of GPIO HAL Extension module. ****************************************************************************** * @attention diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h index b4a825f3..1b96b739 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_pcd.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h index a41478be..f0973c67 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_pcd_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h index 24c5034e..c6e33f6a 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_pwr.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention @@ -169,7 +167,7 @@ typedef struct */ /** @brief Check PWR flag is set or not. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event * was received from the WKUP pin or from the RTC alarm (Alarm A @@ -192,7 +190,7 @@ typedef struct #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) /** @brief Clear the PWR's pending flags. - * @param __FLAG__: specifies the flag to clear. + * @param __FLAG__ specifies the flag to clear. * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag * @arg PWR_FLAG_SB: StandBy flag @@ -375,16 +373,16 @@ void HAL_PWR_DisableSEVOnPend(void); */ /* --- CR Register ---*/ /* Alias word address of DBP bit */ -#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP) +#define DBP_BIT_NUMBER PWR_CR_DBP_Pos #define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)) /* Alias word address of PVDE bit */ -#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE) +#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos #define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)) -/* Alias word address of PMODE bit */ -#define PMODE_BIT_NUMBER POSITION_VAL(PWR_CR_PMODE) -#define CR_PMODE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PMODE_BIT_NUMBER * 4U)) +/* Alias word address of VOS bit */ +#define VOS_BIT_NUMBER PWR_CR_VOS_Pos +#define CR_VOS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (VOS_BIT_NUMBER * 4U)) /** * @} */ @@ -394,7 +392,7 @@ void HAL_PWR_DisableSEVOnPend(void); */ /* --- CSR Register ---*/ /* Alias word address of EWUP bit */ -#define EWUP_BIT_NUMBER POSITION_VAL(PWR_CSR_EWUP) +#define EWUP_BIT_NUMBER PWR_CSR_EWUP_Pos #define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U)) /** * @} diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h index 7abc2412..16186195 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of PWR HAL Extension module. ****************************************************************************** * @attention @@ -126,7 +124,7 @@ #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) /** @brief macros configure the main internal regulator output voltage. - * @param __REGULATOR__: specifies the regulator output voltage to achieve + * @param __REGULATOR__ specifies the regulator output voltage to achieve * a tradeoff between performance and power consumption when the device does * not operate at the maximum frequency (refer to the datasheets for more details). * This parameter can be one of the following values: @@ -143,7 +141,7 @@ } while(0U) #else /** @brief macros configure the main internal regulator output voltage. - * @param __REGULATOR__: specifies the regulator output voltage to achieve + * @param __REGULATOR__ specifies the regulator output voltage to achieve * a tradeoff between performance and power consumption when the device does * not operate at the maximum frequency (refer to the datasheets for more details). * This parameter can be one of the following values: @@ -190,7 +188,7 @@ /** @brief Check PWR flag is set or not. * @note These macros can be used only for STM32F42xx/STM3243xx devices. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode * is ready @@ -269,23 +267,23 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t /* ------------- PWR registers bit address in the alias region ---------------*/ /* --- CR Register ---*/ /* Alias word address of FPDS bit */ -#define FPDS_BIT_NUMBER POSITION_VAL(PWR_CR_FPDS) +#define FPDS_BIT_NUMBER PWR_CR_FPDS_Pos #define CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U)) /* Alias word address of ODEN bit */ -#define ODEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODEN) +#define ODEN_BIT_NUMBER PWR_CR_ODEN_Pos #define CR_ODEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U)) /* Alias word address of ODSWEN bit */ -#define ODSWEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODSWEN) +#define ODSWEN_BIT_NUMBER PWR_CR_ODSWEN_Pos #define CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U)) /* Alias word address of MRLVDS bit */ -#define MRLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_MRLVDS) +#define MRLVDS_BIT_NUMBER PWR_CR_MRLVDS_Pos #define CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U)) /* Alias word address of LPLVDS bit */ -#define LPLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_LPLVDS) +#define LPLVDS_BIT_NUMBER PWR_CR_LPLVDS_Pos #define CR_LPLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U)) /** @@ -297,12 +295,12 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t */ /* --- CSR Register ---*/ /* Alias word address of BRE bit */ -#define BRE_BIT_NUMBER POSITION_VAL(PWR_CSR_BRE) +#define BRE_BIT_NUMBER PWR_CSR_BRE_Pos #define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U)) #if defined(STM32F469xx) || defined(STM32F479xx) /* Alias word address of WUPP bit */ -#define WUPP_BIT_NUMBER POSITION_VAL(PWR_CSR_WUPP) +#define WUPP_BIT_NUMBER PWR_CSR_WUPP_Pos #define CSR_WUPP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (WUPP_BIT_NUMBER * 4U)) #endif /* STM32F469xx || STM32F479xx */ /** diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h index 8d389856..fc89426f 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_rcc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention @@ -54,7 +52,7 @@ * @{ */ -/** @addtogroup RCC +/** @addtogroup RCC * @{ */ @@ -62,9 +60,9 @@ /** @defgroup RCC_Exported_Types RCC Exported Types * @{ */ - + /** - * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition */ typedef struct { @@ -90,7 +88,7 @@ typedef struct }RCC_OscInitTypeDef; /** - * @brief RCC System, AHB and APB busses clock configuration structure definition + * @brief RCC System, AHB and APB busses clock configuration structure definition */ typedef struct { @@ -212,8 +210,8 @@ typedef struct /** * @} */ - -/** @defgroup RCC_System_Clock_Source System Clock Source + +/** @defgroup RCC_System_Clock_Source System Clock Source * @note The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for * STM32F446xx devices. * @{ @@ -253,8 +251,8 @@ typedef struct #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /** * @} - */ - + */ + /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source * @{ */ @@ -265,13 +263,15 @@ typedef struct #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /** * @} - */ + */ /** @defgroup RCC_RTC_Clock_Source RTC Clock Source * @{ */ +#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U #define RCC_RTCCLKSOURCE_LSE 0x00000100U #define RCC_RTCCLKSOURCE_LSI 0x00000200U +#define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U #define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U #define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U #define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U @@ -351,7 +351,7 @@ typedef struct /** * @} */ - + /** @defgroup RCC_Flag Flags * Elements values convention: 0XXYYYYYb * - YYYYY : Flag position in the register @@ -381,7 +381,7 @@ typedef struct #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) /** * @} - */ + */ /** * @} @@ -395,8 +395,8 @@ typedef struct /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable * @brief Enable or disable the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. + * is disabled and the application software has to enable this clock before + * using it. * @{ */ #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ @@ -459,23 +459,23 @@ typedef struct * using it. * @{ */ -#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET) -#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET) -#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET) -#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET) -#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET) -#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET) +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET) +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET) -#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET) -#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET) +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET) #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET) -#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET) +#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET) #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET) -#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET) /** * @} - */ - + */ + /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -539,7 +539,7 @@ typedef struct #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) -#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) +#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) /** * @} */ @@ -565,15 +565,15 @@ typedef struct #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) -#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) /** * @} - */ - + */ + /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable * @brief Enable or disable the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before + * is disabled and the application software has to enable this clock before * using it. * @{ */ @@ -660,7 +660,7 @@ typedef struct #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) -#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) +#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) @@ -669,15 +669,15 @@ typedef struct #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) -#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) +#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) /** * @} - */ - -/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset + */ + +/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset * @brief Force or release AHB1 peripheral reset. * @{ - */ + */ #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) @@ -697,11 +697,11 @@ typedef struct * @} */ -/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset +/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset * @brief Force or release APB1 peripheral reset. * @{ */ -#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) @@ -710,7 +710,7 @@ typedef struct #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) -#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) @@ -722,11 +722,11 @@ typedef struct * @} */ -/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset +/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset * @brief Force or release APB2 peripheral reset. * @{ */ -#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) @@ -749,7 +749,7 @@ typedef struct * @} */ -/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable +/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. @@ -831,23 +831,23 @@ typedef struct */ /** @defgroup RCC_HSI_Configuration HSI Configuration - * @{ - */ - + * @{ + */ + /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. * It is used (enabled by hardware) as system clock source after startup * from Reset, wake-up from STOP and STANDBY mode, or in case of failure * of the HSE used directly or indirectly as system clock (if the Clock - * Security System CSS is enabled). + * Security System CSS is enabled). * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. + * you have to select another source of the system clock then stop the HSI. * @note After enabling the HSI, the application software should wait on HSIRDY * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. + * system clock source. * This parameter can be: ENABLE or DISABLE. * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. + * clock cycles. */ #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) @@ -855,27 +855,27 @@ typedef struct /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. * @note The calibration is used to compensate for the variations in voltage * and temperature that influence the frequency of the internal HSI RC. - * @param __HSICalibrationValue__: specifies the calibration trimming value. + * @param __HSICalibrationValue__ specifies the calibration trimming value. * (default is RCC_HSICALIBRATION_DEFAULT). * This parameter must be a number between 0 and 0x1F. */ #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\ - RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM))) + RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos)) /** * @} */ /** @defgroup RCC_LSI_Configuration LSI Configuration - * @{ - */ + * @{ + */ /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on + * @note After enabling the LSI, the application software should wait on * LSIRDY flag to be set indicating that LSI clock is stable and can * be used to clock the IWDG and/or the RTC. * @note LSI can not be disabled if the IWDG is running. * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. + * clock cycles. */ #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) @@ -884,12 +884,12 @@ typedef struct */ /** @defgroup RCC_HSE_Configuration HSE Configuration - * @{ - */ + * @{ + */ /** * @brief Macro to configure the External High Speed oscillator (HSE). - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. * User should request a transition to HSE Off first and then HSE On or HSE Bypass. * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application * software should wait on HSERDY flag to be set indicating that HSE clock @@ -897,11 +897,11 @@ typedef struct * @note HSE state can not be changed if it is used directly or through the * PLL as system clock. In this case, you have to select another source * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. * @note This function reset the CSSON bit, so if the clock security system(CSS) * was previously enabled you have to enable it again after calling this - * function. - * @param __STATE__: specifies the new state of the HSE. + * function. + * @param __STATE__ specifies the new state of the HSE. * This parameter can be one of the following values: * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after * 6 HSE oscillator clock cycles. @@ -930,21 +930,21 @@ typedef struct */ /** @defgroup RCC_LSE_Configuration LSE Configuration - * @{ + * @{ */ /** * @brief Macro to configure the External Low Speed oscillator (LSE). - * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. * User should request a transition to LSE Off first and then LSE On or LSE Bypass. * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using + * this domain after reset, you have to enable write access using * HAL_PWR_EnableBkUpAccess() function before to configure the LSE - * (to be done once after reset). + * (to be done once after reset). * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application * software should wait on LSERDY flag to be set indicating that LSE clock * is stable and can be used to clock the RTC. - * @param __STATE__: specifies the new state of the LSE. + * @param __STATE__ specifies the new state of the LSE. * This parameter can be one of the following values: * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after * 6 LSE oscillator clock cycles. @@ -973,7 +973,7 @@ typedef struct */ /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration - * @{ + * @{ */ /** @brief Macros to enable or disable the RTC clock. @@ -986,34 +986,52 @@ typedef struct * @note As the RTC clock configuration bits are in the Backup domain and write * access is denied to this domain after reset, you have to enable write * access using the Power Backup Access macro before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by * a Power On Reset (POR). - * @param __RTCCLKSource__: specifies the RTC clock source. + * @param __RTCCLKSource__ specifies the RTC clock source. * This parameter can be one of the following values: - * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. - * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. - * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected - * as RTC clock, where x:[2,31] + @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected + * as RTC clock, where x:[2,31] * @note If the LSE or LSI is used as RTC clock source, the RTC continues to * work in STOP and STANDBY modes, and can be used as wake-up source. * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. + * cannot be used in STOP and STANDBY modes. * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as * RTC clock source). */ #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) - + #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \ } while(0U) +/** @brief Macro to get the RTC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() + */ +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) + +/** + * @brief Get the RTC and HSE clock divider (RTCPRE). + * @retval Returned value can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected + * as RTC clock, where x:[2,31] + */ +#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL) + /** @brief Macros to force or release the Backup domain reset. * @note This function resets the RTC peripheral (including the backup registers) * and the RTC clock source selection in RCC_CSR register. - * @note The BKPSRAM is not affected by this reset. + * @note The BKPSRAM is not affected by this reset. */ #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) @@ -1022,11 +1040,11 @@ typedef struct */ /** @defgroup RCC_PLL_Configuration PLL Configuration - * @{ + * @{ */ /** @brief Macros to enable or disable the main PLL. - * @note After enabling the main PLL, the application software should wait on + * @note After enabling the main PLL, the application software should wait on * PLLRDY flag to be set indicating that PLL clock is stable and can * be used as system clock source. * @note The main PLL can not be disabled if it is used as system clock source @@ -1037,22 +1055,22 @@ typedef struct /** @brief Macro to configure the PLL clock source. * @note This function must be used only when the main PLL is disabled. - * @param __PLLSOURCE__: specifies the PLL entry clock source. + * @param __PLLSOURCE__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry - * + * */ #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) /** @brief Macro to configure the PLL multiplication factor. * @note This function must be used only when the main PLL is disabled. - * @param __PLLM__: specifies the division factor for PLL VCO input clock + * @param __PLLM__ specifies the division factor for PLL VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 2 MHz to limit PLL jitter. - * + * */ #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) /** @@ -1060,16 +1078,16 @@ typedef struct */ /** @defgroup RCC_Get_Clock_source Get Clock source - * @{ + * @{ */ /** * @brief Macro to configure the system clock source. - * @param __RCC_SYSCLKSOURCE__: specifies the system clock source. + * @param __RCC_SYSCLKSOURCE__ specifies the system clock source. * This parameter can be one of the following values: * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. - * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This + * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This * parameter is available only for STM32F446xx devices. */ #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) @@ -1082,8 +1100,8 @@ typedef struct * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter * is available only for STM32F446xx devices. - */ -#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS) /** @brief Macro to get the oscillator used as PLL clock source. * @retval The oscillator used as PLL clock source. The returned value can be one @@ -1097,9 +1115,9 @@ typedef struct */ /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config - * @{ - */ - + * @{ + */ + /** @brief Macro to configure the MCO1 clock. * @param __MCOCLKSOURCE__ specifies the MCO clock source. * This parameter can be one of the following values: @@ -1122,8 +1140,8 @@ typedef struct * @param __MCOCLKSOURCE__ specifies the MCO clock source. * This parameter can be one of the following values: * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source - * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx - * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices + * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx + * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source * @param __MCODIV__ specifies the MCO clock prescaler. @@ -1141,7 +1159,7 @@ typedef struct /** * @} */ - + /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management * @brief macros to manage the specified RCC Flags and interrupts. * @{ @@ -1149,7 +1167,7 @@ typedef struct /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable * the selected interrupts). - * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg RCC_IT_LSIRDY: LSI ready interrupt. * @arg RCC_IT_LSERDY: LSE ready interrupt. @@ -1160,9 +1178,9 @@ typedef struct */ #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) -/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable +/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable * the selected interrupts). - * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg RCC_IT_LSIRDY: LSI ready interrupt. * @arg RCC_IT_LSERDY: LSE ready interrupt. @@ -1175,20 +1193,20 @@ typedef struct /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] * bits to clear the selected interrupt pending bits. - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg RCC_IT_LSIRDY: LSI ready interrupt. * @arg RCC_IT_LSERDY: LSE ready interrupt. * @arg RCC_IT_HSIRDY: HSI ready interrupt. * @arg RCC_IT_HSERDY: HSE ready interrupt. * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. * @arg RCC_IT_CSS: Clock Security System interrupt */ #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) /** @brief Check the RCC's interrupt has occurred or not. - * @param __INTERRUPT__: specifies the RCC interrupt source to check. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. * This parameter can be one of the following values: * @arg RCC_IT_LSIRDY: LSI ready interrupt. * @arg RCC_IT_LSERDY: LSE ready interrupt. @@ -1201,13 +1219,13 @@ typedef struct */ #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) -/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, +/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. */ #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) /** @brief Check RCC flag is set or not. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. @@ -1230,7 +1248,7 @@ typedef struct /** * @} */ - + /** * @} */ @@ -1242,9 +1260,9 @@ typedef struct /** @addtogroup RCC_Exported_Functions_Group1 * @{ - */ + */ /* Initialization and de-initialization functions ******************************/ -void HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_DeInit(void); HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); /** @@ -1268,7 +1286,7 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t /* CSS NMI IRQ handler */ void HAL_RCC_NMI_IRQHandler(void); -/* User Callbacks in non blocking mode (IT mode) */ +/* User Callbacks in non blocking mode (IT mode) */ void HAL_RCC_CSSCallback(void); /** @@ -1291,7 +1309,7 @@ void HAL_RCC_CSSCallback(void); * @{ */ #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) -/* --- CR Register ---*/ +/* --- CR Register --- */ /* Alias word address of HSION bit */ #define RCC_CR_OFFSET (RCC_OFFSET + 0x00U) #define RCC_HSION_BIT_NUMBER 0x00U @@ -1303,7 +1321,7 @@ void HAL_RCC_CSSCallback(void); #define RCC_PLLON_BIT_NUMBER 0x18U #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)) -/* --- BDCR Register ---*/ +/* --- BDCR Register --- */ /* Alias word address of RTCEN bit */ #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U) #define RCC_RTCEN_BIT_NUMBER 0x0FU @@ -1312,7 +1330,7 @@ void HAL_RCC_CSSCallback(void); #define RCC_BDRST_BIT_NUMBER 0x10U #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)) -/* --- CSR Register ---*/ +/* --- CSR Register --- */ /* Alias word address of LSION bit */ #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U) #define RCC_LSION_BIT_NUMBER 0x00U @@ -1336,6 +1354,7 @@ void HAL_RCC_CSSCallback(void); #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT #define HSI_TIMEOUT_VALUE 2U /* 2 ms */ #define LSI_TIMEOUT_VALUE 2U /* 2 ms */ +#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ /** * @} @@ -1349,10 +1368,10 @@ void HAL_RCC_CSSCallback(void); /** @defgroup RCC_Private_Macros RCC Private Macros * @{ */ - + /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters * @{ - */ + */ #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U) #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ @@ -1407,7 +1426,7 @@ void HAL_RCC_CSSCallback(void); ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31)) - + #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U) #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U)) @@ -1433,7 +1452,7 @@ void HAL_RCC_CSSCallback(void); #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ - ((DIV) == RCC_MCODIV_5)) + ((DIV) == RCC_MCODIV_5)) #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU) /** @@ -1446,7 +1465,7 @@ void HAL_RCC_CSSCallback(void); /** * @} - */ + */ /** * @} diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h index 238994fa..613dfb2d 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention @@ -5723,32 +5721,32 @@ typedef struct defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /** @brief Macro to configure the main PLL clock source, multiplication and division factors. * @note This function must be used only when the main PLL is disabled. - * @param __RCC_PLLSource__: specifies the PLL entry clock source. + * @param __RCC_PLLSource__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * @param __PLLM__: specifies the division factor for PLL VCO input clock + * @param __PLLM__ specifies the division factor for PLL VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 2 MHz to limit PLL jitter. - * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLN parameter correctly to ensure that the VCO * output frequency is between 100 and 432 MHz. * - * @param __PLLP__: specifies the division factor for main system clock (SYSCLK) + * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) * This parameter must be a number in the range {2, 4, 6, or 8}. * - * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks + * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * @note If the USB OTG FS is used in your application, you have to set the * PLLQ parameter correctly to have 48 MHz clock for the USB. However, * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work * correctly. * - * @param __PLLR__: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. + * @param __PLLR__ PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks. * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/ STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. @@ -5756,33 +5754,33 @@ typedef struct */ #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ - ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ - ((((__PLLP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \ - ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) | \ - ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR)))) + ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ + ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \ + ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos))) #else /** @brief Macro to configure the main PLL clock source, multiplication and division factors. * @note This function must be used only when the main PLL is disabled. - * @param __RCC_PLLSource__: specifies the PLL entry clock source. + * @param __RCC_PLLSource__ specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * @param __PLLM__: specifies the division factor for PLL VCO input clock + * @param __PLLM__ specifies the division factor for PLL VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 2 MHz to limit PLL jitter. - * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock * This parameter must be a number between Min_Data = 50 and Max_Data = 432 * Except for STM32F411xE devices where Min_Data = 192. * @note You have to set the PLLN parameter correctly to ensure that the VCO * output frequency is between 100 and 432 MHz, Except for STM32F411xE devices * where frequency is between 192 and 432 MHz. - * @param __PLLP__: specifies the division factor for main system clock (SYSCLK) + * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) * This parameter must be a number in the range {2, 4, 6, or 8}. * - * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks + * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * @note If the USB OTG FS is used in your application, you have to set the * PLLQ parameter correctly to have 48 MHz clock for the USB. However, @@ -5792,9 +5790,9 @@ typedef struct */ #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \ - ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ - ((((__PLLP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \ - ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)))) + ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \ + ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos))) #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ /*----------------------------------------------------------------------------*/ @@ -5819,84 +5817,84 @@ typedef struct * @note This macro must be used only when the PLLI2S is disabled. * @note PLLI2S clock source is common with the main PLL (configured in * HAL_RCC_ClockConfig() API). - * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock + * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 1 MHz to limit PLLI2S jitter. * - * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. * - * @param __PLLI2SP__: specifies division factor for SPDIFRX Clock. + * @param __PLLI2SP__ specifies division factor for SPDIFRX Clock. * This parameter must be a number in the range {2, 4, 6, or 8}. * @note the PLLI2SP parameter is only available with STM32F446xx Devices * - * @param __PLLI2SR__: specifies the division factor for I2S clock + * @param __PLLI2SR__ specifies the division factor for I2S clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. * - * @param __PLLI2SQ__: specifies the division factor for SAI clock + * @param __PLLI2SQ__ specifies the division factor for SAI clock * This parameter must be a number between Min_Data = 2 and Max_Data = 15. */ #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ - ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\ - ((((__PLLI2SP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\ - ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\ - ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))) + ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\ + ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) #elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ defined(STM32F413xx) || defined(STM32F423xx) /** @brief Macro to configure the PLLI2S clock multiplication and division factors . * @note This macro must be used only when the PLLI2S is disabled. * @note PLLI2S clock source is common with the main PLL (configured in * HAL_RCC_ClockConfig() API). - * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock + * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 1 MHz to limit PLLI2S jitter. * - * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. * - * @param __PLLI2SR__: specifies the division factor for I2S clock + * @param __PLLI2SR__ specifies the division factor for I2S clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. * - * @param __PLLI2SQ__: specifies the division factor for SAI clock + * @param __PLLI2SQ__ specifies the division factor for SAI clock * This parameter must be a number between Min_Data = 2 and Max_Data = 15. */ #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \ (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ - ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\ - ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\ - ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))) + ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) #else /** @brief Macro to configure the PLLI2S clock multiplication and division factors . * @note This macro must be used only when the PLLI2S is disabled. * @note PLLI2S clock source is common with the main PLL (configured in * HAL_RCC_ClockConfig() API). - * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. * - * @param __PLLI2SR__: specifies the division factor for I2S clock + * @param __PLLI2SR__ specifies the division factor for I2S clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. * */ #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \ - (RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\ - ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))) + (RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) #endif /* STM32F446xx */ #if defined(STM32F411xE) @@ -5905,24 +5903,24 @@ typedef struct * @note This macro must be used only when the PLLI2S is disabled. * @note PLLI2S clock source is common with the main PLL (configured in * HAL_RCC_ClockConfig() API). - * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock + * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 2 MHz to limit PLLI2S jitter. - * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock * This parameter must be a number between Min_Data = 192 and Max_Data = 432. * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 192 and Max_Data = 432 MHz. - * @param __PLLI2SR__: specifies the division factor for I2S clock + * @param __PLLI2SR__ specifies the division factor for I2S clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. */ #define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\ - ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\ - ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))) + ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))) #endif /* STM32F411xE */ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) @@ -5930,15 +5928,15 @@ typedef struct * @note This macro must be used only when the PLLI2S is disabled. * @note PLLI2S clock source is common with the main PLL (configured in * HAL_RCC_ClockConfig() API) - * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock. + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. - * @param __PLLI2SQ__: specifies the division factor for SAI1 clock. + * @param __PLLI2SQ__ specifies the division factor for SAI1 clock. * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx * Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro - * @param __PLLI2SR__: specifies the division factor for I2S clock + * @param __PLLI2SR__ specifies the division factor for I2S clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. @@ -5961,79 +5959,79 @@ typedef struct #if defined(STM32F446xx) /** @brief Macro to configure the PLLSAI clock multiplication and division factors. * - * @param __PLLSAIM__: specifies the division factor for PLLSAI VCO input clock + * @param __PLLSAIM__ specifies the division factor for PLLSAI VCO input clock * This parameter must be a number between Min_Data = 2 and Max_Data = 63. * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 1 MHz to limit PLLI2S jitter. * @note The PLLSAIM parameter is only used with STM32F446xx Devices * - * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock. + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. * - * @param __PLLSAIP__: specifies division factor for OTG FS, SDIO and RNG clocks. + * @param __PLLSAIP__ specifies division factor for OTG FS, SDIO and RNG clocks. * This parameter must be a number in the range {2, 4, 6, or 8}. * @note the PLLSAIP parameter is only available with STM32F446xx Devices * - * @param __PLLSAIQ__: specifies the division factor for SAI clock + * @param __PLLSAIQ__ specifies the division factor for SAI clock * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * - * @param __PLLSAIR__: specifies the division factor for LTDC clock + * @param __PLLSAIR__ specifies the division factor for LTDC clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices */ #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ (RCC->PLLSAICFGR = ((__PLLSAIM__) | \ - ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) | \ - ((((__PLLSAIP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) | \ - ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)))) + ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ + ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) | \ + ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos))) #endif /* STM32F446xx */ #if defined(STM32F469xx) || defined(STM32F479xx) /** @brief Macro to configure the PLLSAI clock multiplication and division factors. * - * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock. + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. * - * @param __PLLSAIP__: specifies division factor for SDIO and CLK48 clocks. + * @param __PLLSAIP__ specifies division factor for SDIO and CLK48 clocks. * This parameter must be a number in the range {2, 4, 6, or 8}. * - * @param __PLLSAIQ__: specifies the division factor for SAI clock + * @param __PLLSAIQ__ specifies the division factor for SAI clock * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * - * @param __PLLSAIR__: specifies the division factor for LTDC clock + * @param __PLLSAIR__ specifies the division factor for LTDC clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. */ #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ - (RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\ - ((((__PLLSAIP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\ - ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) |\ - ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))) + (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ + ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ + ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\ + ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))) #endif /* STM32F469xx || STM32F479xx */ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) /** @brief Macro to configure the PLLSAI clock multiplication and division factors. * - * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock. + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. * This parameter must be a number between Min_Data = 50 and Max_Data = 432. * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. * - * @param __PLLSAIQ__: specifies the division factor for SAI clock + * @param __PLLSAIQ__ specifies the division factor for SAI clock * This parameter must be a number between Min_Data = 2 and Max_Data = 15. * - * @param __PLLSAIR__: specifies the division factor for LTDC clock + * @param __PLLSAIR__ specifies the division factor for LTDC clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices */ #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \ - (RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) | \ - ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) | \ - ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))) + (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \ + ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) | \ + ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))) #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ @@ -6043,14 +6041,14 @@ typedef struct #if defined(STM32F413xx) || defined(STM32F423xx) /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. * @note This function must be called before enabling the PLLI2S. - * @param __PLLI2SDivR__: specifies the PLLI2S division factor for SAI1 clock. + * @param __PLLI2SDivR__ specifies the PLLI2S division factor for SAI1 clock. * This parameter must be a number between 1 and 32. * SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__ */ #define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U)) /** @brief Macro to configure the SAI clock Divider coming from PLL. - * @param __PLLDivR__: specifies the PLL division factor for SAI1 clock. + * @param __PLLDivR__ specifies the PLL division factor for SAI1 clock. * This parameter must be a number between 1 and 32. * SAI1 clock frequency = f(PLLR) / __PLLDivR__ */ @@ -6061,7 +6059,7 @@ typedef struct defined(STM32F469xx) || defined(STM32F479xx) /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. * @note This function must be called before enabling the PLLI2S. - * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock. + * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock. * This parameter must be a number between 1 and 32. * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ */ @@ -6069,7 +6067,7 @@ typedef struct /** @brief Macro to configure the SAI clock Divider coming from PLLSAI. * @note This function must be called before enabling the PLLSAI. - * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock . + * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock . * This parameter must be a number between Min_Data = 1 and Max_Data = 32. * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ */ @@ -6081,7 +6079,7 @@ typedef struct * * @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices. * @note This function must be called before enabling the PLLSAI. - * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock . + * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . * This parameter must be a number between Min_Data = 2 and Max_Data = 16. * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ */ @@ -6096,7 +6094,7 @@ typedef struct defined(STM32F479xx) /** @brief Macro to configure the I2S clock source (I2SCLK). * @note This function must be called before enabling the I2S APB clock. - * @param __SOURCE__: specifies the I2S clock source. + * @param __SOURCE__ specifies the I2S clock source. * This parameter can be one of the following values: * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin @@ -6120,7 +6118,7 @@ typedef struct * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. * @note This function must be called before enabling PLLSAI, PLLI2S and * the SAI clock. - * @param __SOURCE__: specifies the SAI Block A clock source. + * @param __SOURCE__ specifies the SAI Block A clock source. * This parameter can be one of the following values: * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used * as SAI1 Block A clock. @@ -6135,7 +6133,7 @@ typedef struct * @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices. * @note This function must be called before enabling PLLSAI, PLLI2S and * the SAI clock. - * @param __SOURCE__: specifies the SAI Block B clock source. + * @param __SOURCE__ specifies the SAI Block B clock source. * This parameter can be one of the following values: * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used * as SAI1 Block B clock. @@ -6152,7 +6150,7 @@ typedef struct * @note This configuration is only available with STM32F446xx Devices. * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and * the SAI clock. - * @param __SOURCE__: specifies the SAI1 clock source. + * @param __SOURCE__ specifies the SAI1 clock source. * This parameter can be one of the following values: * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock. @@ -6175,7 +6173,7 @@ typedef struct * @note This configuration is only available with STM32F446xx Devices. * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and * the SAI clock. - * @param __SOURCE__: specifies the SAI2 clock source. + * @param __SOURCE__ specifies the SAI2 clock source. * This parameter can be one of the following values: * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock. @@ -6196,7 +6194,7 @@ typedef struct /** @brief Macro to configure I2S APB1 clock source selection. * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. - * @param __SOURCE__: specifies the I2S APB1 clock source. + * @param __SOURCE__ specifies the I2S APB1 clock source. * This parameter can be one of the following values: * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock. @@ -6216,7 +6214,7 @@ typedef struct /** @brief Macro to configure I2S APB2 clock source selection. * @note This function must be called before enabling PLL, PLLI2S and the I2S clock. - * @param __SOURCE__: specifies the SAI Block A clock source. + * @param __SOURCE__ specifies the SAI Block A clock source. * This parameter can be one of the following values: * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock. @@ -6235,7 +6233,7 @@ typedef struct #define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC)) /** @brief Macro to configure the CEC clock. - * @param __SOURCE__: specifies the CEC clock source. + * @param __SOURCE__ specifies the CEC clock source. * This parameter can be one of the following values: * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock @@ -6250,7 +6248,7 @@ typedef struct #define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)) /** @brief Macro to configure the FMPI2C1 clock. - * @param __SOURCE__: specifies the FMPI2C1 clock source. + * @param __SOURCE__ specifies the FMPI2C1 clock source. * This parameter can be one of the following values: * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock @@ -6267,7 +6265,7 @@ typedef struct #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) /** @brief Macro to configure the CLK48 clock. - * @param __SOURCE__: specifies the CLK48 clock source. + * @param __SOURCE__ specifies the CLK48 clock source. * This parameter can be one of the following values: * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. @@ -6282,7 +6280,7 @@ typedef struct #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)) /** @brief Macro to configure the SDIO clock. - * @param __SOURCE__: specifies the SDIO clock source. + * @param __SOURCE__ specifies the SDIO clock source. * This parameter can be one of the following values: * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. @@ -6297,7 +6295,7 @@ typedef struct #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL)) /** @brief Macro to configure the SPDIFRX clock. - * @param __SOURCE__: specifies the SPDIFRX clock source. + * @param __SOURCE__ specifies the SPDIFRX clock source. * This parameter can be one of the following values: * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock. * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. @@ -6315,7 +6313,7 @@ typedef struct #if defined(STM32F469xx) || defined(STM32F479xx) /** @brief Macro to configure the CLK48 clock. - * @param __SOURCE__: specifies the CLK48 clock source. + * @param __SOURCE__ specifies the CLK48 clock source. * This parameter can be one of the following values: * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. * @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. @@ -6330,7 +6328,7 @@ typedef struct #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL)) /** @brief Macro to configure the SDIO clock. - * @param __SOURCE__: specifies the SDIO clock source. + * @param __SOURCE__ specifies the SDIO clock source. * This parameter can be one of the following values: * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. @@ -6345,7 +6343,7 @@ typedef struct #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL)) /** @brief Macro to configure the DSI clock. - * @param __SOURCE__: specifies the DSI clock source. + * @param __SOURCE__ specifies the DSI clock source. * This parameter can be one of the following values: * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. @@ -6364,7 +6362,7 @@ typedef struct #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ defined(STM32F413xx) || defined(STM32F423xx) /** @brief Macro to configure the DFSDM1 clock. - * @param __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source. + * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. * This parameter can be one of the following values: * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock. @@ -6382,7 +6380,7 @@ typedef struct /** @brief Macro to configure DFSDM1 Audio clock source selection. * @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/ STM32F413xx/STM32F423xx Devices. - * @param __SOURCE__: specifies the DFSDM1 Audio clock source. + * @param __SOURCE__ specifies the DFSDM1 Audio clock source. * This parameter can be one of the following values: * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock @@ -6400,7 +6398,7 @@ typedef struct #if defined(STM32F413xx) || defined(STM32F423xx) /** @brief Macro to configure the DFSDM2 clock. - * @param __DFSDM2_CLKSOURCE__: specifies the DFSDM1 clock source. + * @param __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source. * This parameter can be one of the following values: * @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. * @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock. @@ -6417,7 +6415,7 @@ typedef struct /** @brief Macro to configure DFSDM1 Audio clock source selection. * @note This configuration is only available with STM32F413xx/STM32F423xx Devices. - * @param __SOURCE__: specifies the DFSDM2 Audio clock source. + * @param __SOURCE__ specifies the DFSDM2 Audio clock source. * This parameter can be one of the following values: * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock @@ -6436,7 +6434,7 @@ typedef struct * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices. * @note This function must be called before enabling PLLSAI, PLLI2S and * the SAI clock. - * @param __SOURCE__: specifies the SAI Block A clock source. + * @param __SOURCE__ specifies the SAI Block A clock source. * This parameter can be one of the following values: * @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. * @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock. @@ -6459,7 +6457,7 @@ typedef struct * @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices. * @note This function must be called before enabling PLLSAI, PLLI2S and * the SAI clock. - * @param __SOURCE__: specifies the SAI Block B clock source. + * @param __SOURCE__ specifies the SAI Block B clock source. * This parameter can be one of the following values: * @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock. * @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock. @@ -6479,7 +6477,7 @@ typedef struct #define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC)) /** @brief Macro to configure the LPTIM1 clock. - * @param __SOURCE__: specifies the LPTIM1 clock source. + * @param __SOURCE__ specifies the LPTIM1 clock source. * This parameter can be one of the following values: * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock @@ -6499,7 +6497,7 @@ typedef struct #endif /* STM32F413xx || STM32F423xx */ /** @brief Macro to configure I2S APB1 clock source selection. - * @param __SOURCE__: specifies the I2S APB1 clock source. + * @param __SOURCE__ specifies the I2S APB1 clock source. * This parameter can be one of the following values: * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. @@ -6518,7 +6516,7 @@ typedef struct #define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC)) /** @brief Macro to configure I2S APB2 clock source selection. - * @param __SOURCE__: specifies the I2S APB2 clock source. + * @param __SOURCE__ specifies the I2S APB2 clock source. * This parameter can be one of the following values: * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR. * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. @@ -6538,7 +6536,7 @@ typedef struct /** @brief Macro to configure the PLL I2S clock source (PLLI2SCLK). * @note This macro must be called before enabling the I2S APB clock. - * @param __SOURCE__: specifies the I2S clock source. + * @param __SOURCE__ specifies the I2S clock source. * This parameter can be one of the following values: * @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock. * @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin @@ -6547,7 +6545,7 @@ typedef struct #define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__)) /** @brief Macro to configure the FMPI2C1 clock. - * @param __SOURCE__: specifies the FMPI2C1 clock source. + * @param __SOURCE__ specifies the FMPI2C1 clock source. * This parameter can be one of the following values: * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock @@ -6564,7 +6562,7 @@ typedef struct #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) /** @brief Macro to configure the CLK48 clock. - * @param __SOURCE__: specifies the CLK48 clock source. + * @param __SOURCE__ specifies the CLK48 clock source. * This parameter can be one of the following values: * @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. * @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock. @@ -6579,7 +6577,7 @@ typedef struct #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)) /** @brief Macro to configure the SDIO clock. - * @param __SOURCE__: specifies the SDIO clock source. + * @param __SOURCE__ specifies the SDIO clock source. * This parameter can be one of the following values: * @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. @@ -6597,7 +6595,7 @@ typedef struct #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) /** @brief Macro to configure I2S clock source selection. - * @param __SOURCE__: specifies the I2S clock source. + * @param __SOURCE__ specifies the I2S clock source. * This parameter can be one of the following values: * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. @@ -6614,7 +6612,7 @@ typedef struct #define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC)) /** @brief Macro to configure the FMPI2C1 clock. - * @param __SOURCE__: specifies the FMPI2C1 clock source. + * @param __SOURCE__ specifies the FMPI2C1 clock source. * This parameter can be one of the following values: * @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock @@ -6631,7 +6629,7 @@ typedef struct #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL)) /** @brief Macro to configure the LPTIM1 clock. - * @param __SOURCE__: specifies the LPTIM1 clock source. + * @param __SOURCE__ specifies the LPTIM1 clock source. * This parameter can be one of the following values: * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock @@ -6657,7 +6655,7 @@ typedef struct defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /** @brief Macro to configure the Timers clocks prescalers * @note This feature is only available with STM32F429x/439x Devices. - * @param __PRESC__ : specifies the Timers clocks prescalers selection + * @param __PRESC__ specifies the Timers clocks prescalers selection * This parameter can be one of the following values: * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is * equal to HPRE if PPREx is corresponding to division by 1 or 2, @@ -6737,6 +6735,14 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); defined(STM32F423xx) void HAL_RCCEx_SelectLSEMode(uint8_t Mode); #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +#if defined(RCC_PLLI2S_SUPPORT) +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); +#endif /* RCC_PLLI2S_SUPPORT */ +#if defined(RCC_PLLSAI_SUPPORT) +HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); +#endif /* RCC_PLLSAI_SUPPORT */ /** * @} */ diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h index 9ba8dd35..933f4099 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_spi.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention @@ -308,16 +306,16 @@ typedef struct __SPI_HandleTypeDef */ /** @brief Reset SPI handle state. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) /** @brief Enable or disable the specified SPI interrupts. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -328,9 +326,9 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) /** @brief Check whether the specified SPI interrupt source is enabled or not. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the SPI interrupt source to check. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -340,9 +338,9 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SPI flag is set or not. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SPI_FLAG_RXNE: Receive buffer not empty flag * @arg SPI_FLAG_TXE: Transmit buffer empty flag @@ -356,14 +354,14 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the SPI CRCERR pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) /** @brief Clear the SPI MODF pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -376,7 +374,7 @@ typedef struct __SPI_HandleTypeDef } while(0U) /** @brief Clear the SPI OVR pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -389,7 +387,7 @@ typedef struct __SPI_HandleTypeDef } while(0U) /** @brief Clear the SPI FRE pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -401,14 +399,14 @@ typedef struct __SPI_HandleTypeDef }while(0U) /** @brief Enable the SPI peripheral. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE) /** @brief Disable the SPI peripheral. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -491,21 +489,21 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); */ /** @brief Set the SPI transmit-only mode. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE) /** @brief Set the SPI receive-only mode. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE)) /** @brief Reset the CRC calculation of the SPI. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h index 35172181..0600fb28 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_tim.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention @@ -853,21 +851,21 @@ typedef struct * @{ */ /** @brief Reset TIM handle state - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) /** * @brief Enable the TIM peripheral. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) /** * @brief Enable the TIM main Output. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) @@ -875,7 +873,7 @@ typedef struct /** * @brief Disable the TIM peripheral. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_DISABLE(__HANDLE__) \ @@ -893,7 +891,7 @@ typedef struct channels have been disabled */ /** * @brief Disable the TIM main Output. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None */ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ @@ -909,15 +907,15 @@ typedef struct /** * @brief Disable the TIM main Output. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ TIM handle * @retval None * @note The Main Output Enable of a timer instance is disabled unconditionally */ #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) /** @brief Enable the specified TIM interrupt. - * @param __HANDLE__: specifies the TIM Handle. - * @param __INTERRUPT__: specifies the TIM interrupt source to enable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -933,8 +931,8 @@ typedef struct /** @brief Disable the specified TIM interrupt. - * @param __HANDLE__: specifies the TIM Handle. - * @param __INTERRUPT__: specifies the TIM interrupt source to disable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -949,8 +947,8 @@ typedef struct #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) /** @brief Enable the specified DMA request. - * @param __HANDLE__: specifies the TIM Handle. - * @param __DMA__: specifies the TIM DMA request to enable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request @@ -964,8 +962,8 @@ typedef struct #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) /** @brief Disable the specified DMA request. - * @param __HANDLE__: specifies the TIM Handle. - * @param __DMA__: specifies the TIM DMA request to disable. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request @@ -979,8 +977,8 @@ typedef struct #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) /** @brief Check whether the specified TIM interrupt flag is set or not. - * @param __HANDLE__: specifies the TIM Handle. - * @param __FLAG__: specifies the TIM interrupt flag to check. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag @@ -1003,8 +1001,8 @@ typedef struct #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) /** @brief Clear the specified TIM interrupt flag. - * @param __HANDLE__: specifies the TIM Handle. - * @param __FLAG__: specifies the TIM interrupt flag to clear. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. * This parameter can be one of the following values: * @arg TIM_FLAG_UPDATE: Update interrupt flag * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag @@ -1028,8 +1026,8 @@ typedef struct /** * @brief Check whether the specified TIM interrupt source is enabled or not. - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the TIM interrupt source to check. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -1044,8 +1042,8 @@ typedef struct #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Clear the TIM interrupt pending bits. - * @param __HANDLE__: TIM handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt * @arg TIM_IT_CC1: Capture/Compare 1 interrupt @@ -1061,7 +1059,7 @@ typedef struct /** * @brief Indicates whether or not the TIM Counter is used as downcounter. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @retval False (Counter used as upcounter) or True (Counter used as downcounter) * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder mode. @@ -1070,8 +1068,8 @@ mode. /** * @brief Set the TIM Prescaler on runtime. - * @param __HANDLE__: TIM handle. - * @param __PRESC__: specifies the Prescaler new value. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. * @retval None */ #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) @@ -1103,14 +1101,14 @@ mode. /** * @brief Sets the TIM Capture Compare Register value on runtime without * calling another time ConfigChannel function. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__ : TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __COMPARE__: specifies the Capture Compare register new value. + * @param __COMPARE__ specifies the Capture Compare register new value. * @retval None */ #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ @@ -1118,8 +1116,8 @@ mode. /** * @brief Gets the TIM Capture Compare Register value on runtime. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channel associated with the capture compare register + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get capture/compare 1 register value * @arg TIM_CHANNEL_2: get capture/compare 2 register value @@ -1134,15 +1132,15 @@ mode. /** * @brief Sets the TIM Counter Register value on runtime. - * @param __HANDLE__: TIM handle. - * @param __COUNTER__: specifies the Counter register new value. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) /** * @brief Gets the TIM Counter Register value on runtime. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) */ #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) @@ -1150,8 +1148,8 @@ mode. /** * @brief Sets the TIM Autoreload Register value on runtime without calling * another time any Init function. - * @param __HANDLE__: TIM handle. - * @param __AUTORELOAD__: specifies the Counter register new value. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. * @retval None */ #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ @@ -1161,15 +1159,15 @@ mode. } while(0U) /** * @brief Gets the TIM Autoreload Register value on runtime. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) */ #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) /** * @brief Sets the TIM Clock Division value on runtime without calling another time any Init function. - * @param __HANDLE__: TIM handle. - * @param __CKD__: specifies the clock division value. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. * This parameter can be one of the following value: * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT @@ -1184,7 +1182,7 @@ mode. } while(0U) /** * @brief Gets the TIM Clock Division value on runtime. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @retval The clock division can be one of the following values: * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT @@ -1195,14 +1193,14 @@ mode. /** * @brief Sets the TIM Input Capture prescaler on runtime without calling * another time HAL_TIM_IC_ConfigChannel() function. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__ : TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __ICPSC__: specifies the Input Capture4 prescaler new value. + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. * This parameter can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events @@ -1218,8 +1216,8 @@ mode. /** * @brief Get the TIM Input Capture prescaler on runtime. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get input capture 1 prescaler value * @arg TIM_CHANNEL_2: get input capture 2 prescaler value @@ -1239,7 +1237,7 @@ mode. /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @note When the USR bit of the TIMx_CR1 register is set, only counter * overflow/underflow generates an update interrupt or DMA request (if * enabled) @@ -1250,7 +1248,7 @@ mode. /** * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ TIM handle. * @note When the USR bit of the TIMx_CR1 register is reset, any of the * following events generate an update interrupt or DMA request (if * enabled): @@ -1264,14 +1262,14 @@ mode. /** * @brief Sets the TIM Capture x input polarity on runtime. - * @param __HANDLE__: TIM handle. - * @param __CHANNEL__: TIM Channels to be configured. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __POLARITY__: Polarity for TIx source + * @param __POLARITY__ Polarity for TIx source * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h index 636e8918..3aa09d9e 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of TIM HAL Extension module. ****************************************************************************** * @attention diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h index ba2ed4f8..16f755bc 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_uart.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of UART HAL module. ****************************************************************************** * @attention @@ -353,7 +351,7 @@ typedef struct */ /** @brief Reset UART handle gstate & RxState - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval None @@ -364,15 +362,15 @@ typedef struct } while(0U) /** @brief Flushes the UART DR register - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. */ #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) /** @brief Checks whether the specified UART flag is set or not. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) * @arg UART_FLAG_LBD: LIN Break detection flag @@ -390,10 +388,10 @@ typedef struct #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) /** @brief Clears the specified UART pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). * @arg UART_FLAG_LBD: LIN Break detection flag. @@ -414,7 +412,7 @@ typedef struct #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) /** @brief Clear the UART PE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval None @@ -428,7 +426,7 @@ typedef struct } while(0U) /** @brief Clear the UART FE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval None @@ -436,7 +434,7 @@ typedef struct #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the UART NE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval None @@ -444,7 +442,7 @@ typedef struct #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the UART ORE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval None @@ -452,7 +450,7 @@ typedef struct #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the UART IDLE pending flag. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval None @@ -460,10 +458,10 @@ typedef struct #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) /** @brief Enable the specified UART interrupt. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. - * @param __INTERRUPT__: specifies the UART interrupt source to enable. + * @param __INTERRUPT__ specifies the UART interrupt source to enable. * This parameter can be one of the following values: * @arg UART_IT_CTS: CTS change interrupt * @arg UART_IT_LBD: LIN Break detection interrupt @@ -480,10 +478,10 @@ typedef struct (((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK))) /** @brief Disable the specified UART interrupt. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. - * @param __INTERRUPT__: specifies the UART interrupt source to disable. + * @param __INTERRUPT__ specifies the UART interrupt source to disable. * This parameter can be one of the following values: * @arg UART_IT_CTS: CTS change interrupt * @arg UART_IT_LBD: LIN Break detection interrupt @@ -500,10 +498,10 @@ typedef struct ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK))) /** @brief Checks whether the specified UART interrupt has occurred or not. - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. - * @param __IT__: specifies the UART interrupt source to check. + * @param __IT__ specifies the UART interrupt source to check. * This parameter can be one of the following values: * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) * @arg UART_IT_LBD: LIN Break detection interrupt @@ -526,7 +524,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * The Handle Instance can be USART1, USART2 or LPUART. * @retval None */ @@ -545,7 +543,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * The Handle Instance can be USART1, USART2 or LPUART. * @retval None */ @@ -564,7 +562,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * The Handle Instance can be USART1, USART2 or LPUART. * @retval None */ @@ -583,7 +581,7 @@ typedef struct * - UART instance should have already been initialised (through call of HAL_UART_Init() ) * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * The Handle Instance can be USART1, USART2 or LPUART. * @retval None */ @@ -594,25 +592,25 @@ typedef struct } while(0U) /** @brief macros to enables the UART's one bit sample method - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) /** @brief macros to disables the UART's one bit sample method - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) /** @brief Enable UART - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable UART - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__ specifies the UART Handle. * @retval None */ #define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h index 2eeb1117..1048bee5 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_usb.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of USB Core HAL module. ****************************************************************************** * @attention diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c index 8e741e4f..bf966f9a 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief HAL module driver. * This is the common part of the HAL initialization * @@ -68,11 +66,11 @@ * @{ */ /** - * @brief STM32F4xx HAL Driver version number V1.7.1 + * @brief STM32F4xx HAL Driver version number V1.7.3 */ #define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */ -#define __STM32F4xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ +#define __STM32F4xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ #define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\ |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\ @@ -86,19 +84,19 @@ /* --- MEMRMP Register ---*/ /* Alias word address of UFB_MODE bit */ #define MEMRMP_OFFSET SYSCFG_OFFSET -#define UFB_MODE_BIT_NUMBER POSITION_VAL(SYSCFG_MEMRMP_UFB_MODE) +#define UFB_MODE_BIT_NUMBER SYSCFG_MEMRMP_UFB_MODE_Pos #define UFB_MODE_BB (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U)) /* --- CMPCR Register ---*/ /* Alias word address of CMP_PD bit */ #define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20U) -#define CMP_PD_BIT_NUMBER POSITION_VAL(SYSCFG_CMPCR_CMP_PD) +#define CMP_PD_BIT_NUMBER SYSCFG_CMPCR_CMP_PD_Pos #define CMPCR_CMP_PD_BB (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U)) /* --- MCHDLYCR Register ---*/ /* Alias word address of BSCKSEL bit */ #define MCHDLYCR_OFFSET (SYSCFG_OFFSET + 0x30U) -#define BSCKSEL_BIT_NUMBER POSITION_VAL(SYSCFG_MCHDLYCR_BSCKSEL) +#define BSCKSEL_BIT_NUMBER SYSCFG_MCHDLYCR_BSCKSEL_Pos #define MCHDLYCR_BSCKSEL_BB (uint32_t)(PERIPH_BB_BASE + (MCHDLYCR_OFFSET * 32U) + (BSCKSEL_BIT_NUMBER * 4U)) /** * @} @@ -110,6 +108,8 @@ * @{ */ __IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ /** * @} */ @@ -125,16 +125,16 @@ __IO uint32_t uwTick; * @verbatim =============================================================================== - ##### Initialization and de-initialization functions ##### + ##### Initialization and Configuration functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initializes the Flash interface the NVIC allocation and initial clock configuration. It initializes the systick also when timeout is needed and the backup domain when enabled. - (+) de-Initializes common part of the HAL - (+) Configure The time base source to have 1ms time base with a dedicated + (+) De-Initializes common part of the HAL. + (+) Configure the time base source to have 1ms time base with a dedicated Tick interrupt priority. - (++) Systick timer is used by default as source of time base, but user + (++) SysTick timer is used by default as source of time base, but user can eventually implement his proper time base source (a general purpose timer for example or other time source), keeping in mind that Time base duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and @@ -174,11 +174,11 @@ HAL_StatusTypeDef HAL_Init(void) { /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) - __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE != 0U) - __HAL_FLASH_DATA_CACHE_ENABLE(); + __HAL_FLASH_DATA_CACHE_ENABLE(); #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) @@ -190,10 +190,10 @@ HAL_StatusTypeDef HAL_Init(void) /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); - + /* Init the low level hardware */ HAL_MspInit(); - + /* Return function status */ return HAL_OK; } @@ -229,12 +229,12 @@ HAL_StatusTypeDef HAL_DeInit(void) } /** - * @brief Initializes the MSP. + * @brief Initialize the MSP. * @retval None */ __weak void HAL_MspInit(void) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspInit could be implemented in the user file */ } @@ -245,7 +245,7 @@ __weak void HAL_MspInit(void) */ __weak void HAL_MspDeInit(void) { - /* NOTE : This function Should not be modified, when the callback is needed, + /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspDeInit could be implemented in the user file */ } @@ -259,20 +259,31 @@ __weak void HAL_MspDeInit(void) * @note In the default implementation, SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals. * Care must be taken if HAL_Delay() is called from a peripheral ISR process, - * The the SysTick interrupt must have higher priority (numerically lower) + * The SysTick interrupt must have higher priority (numerically lower) * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * The function is declared as __weak to be overwritten in case of other * implementation in user file. - * @param TickPriority: Tick interrupt priority. + * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - /*Configure the SysTick to have interrupt in 1ms time basis*/ - HAL_SYSTICK_Config(SystemCoreClock/1000U); + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + { + return HAL_ERROR; + } - /*Configure the SysTick IRQ priority */ - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + return HAL_ERROR; + } /* Return function status */ return HAL_OK; @@ -309,14 +320,14 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) * @brief This function is called to increment a global variable "uwTick" * used as application time base. * @note In the default implementation, this variable is incremented each 1ms - * in Systick ISR. + * in SysTick ISR. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { - uwTick++; + uwTick += uwTickFreq; } /** @@ -330,6 +341,44 @@ __weak uint32_t HAL_GetTick(void) return uwTick; } +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval Status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval tick period in Hz + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + /** * @brief This function provides minimum delay (in milliseconds) based * on variable incremented. @@ -338,20 +387,20 @@ __weak uint32_t HAL_GetTick(void) * is incremented. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. - * @param Delay: specifies the delay time length, in milliseconds. + * @param Delay specifies the delay time length, in milliseconds. * @retval None */ -__weak void HAL_Delay(__IO uint32_t Delay) +__weak void HAL_Delay(uint32_t Delay) { uint32_t tickstart = HAL_GetTick(); uint32_t wait = Delay; - - /* Add a period to guarantee minimum wait */ + + /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) { - wait++; + wait += (uint32_t)(uwTickFreq); } - + while((HAL_GetTick() - tickstart) < wait) { } @@ -395,7 +444,7 @@ __weak void HAL_ResumeTick(void) */ uint32_t HAL_GetHalVersion(void) { - return __STM32F4xx_HAL_VERSION; + return __STM32F4xx_HAL_VERSION; } /** @@ -404,7 +453,7 @@ uint32_t HAL_GetHalVersion(void) */ uint32_t HAL_GetREVID(void) { - return((DBGMCU->IDCODE) >> 16U); + return((DBGMCU->IDCODE) >> 16U); } /** @@ -413,7 +462,7 @@ uint32_t HAL_GetREVID(void) */ uint32_t HAL_GetDEVID(void) { - return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); + return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); } /** @@ -494,7 +543,7 @@ void HAL_DisableCompensationCell(void) /** * @brief Return the unique device identifier (UID based on 96 bits) - * @param UID: pointer to 3 words array. + * @param UID pointer to 3 words array. * @retval Device identifier */ void HAL_GetUID(uint32_t *UID) @@ -533,7 +582,6 @@ void HAL_EnableMemorySwappingBank(void) */ void HAL_DisableMemorySwappingBank(void) { - *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)DISABLE; } #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c index 3f04fc36..d67cff8e 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_adc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) peripheral: * + Initialization and de-initialization functions @@ -251,7 +249,7 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); * External trigger source and edge, DMA continuous request after the * last transfer and End of conversion selection). * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -329,7 +327,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /** * @brief Deinitializes the ADCx peripheral registers to their default reset values. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -376,7 +374,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) /** * @brief Initializes the ADC MSP. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -391,7 +389,7 @@ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) /** * @brief DeInitializes the ADC MSP. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -430,7 +428,7 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) /** * @brief Enables ADC and starts conversion of the regular channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -536,7 +534,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) * * @note Caution: This function will stop also injected channels. * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * * @retval HAL status. @@ -579,9 +577,9 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) * In this case, DMA resets the flag EOC and polling cannot be * performed on each conversion. Nevertheless, polling can still * be performed on the complete sequence. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param Timeout: Timeout value in millisecond. + * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) @@ -660,13 +658,13 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /** * @brief Poll for conversion event - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param EventType: the ADC event type. + * @param EventType the ADC event type. * This parameter can be one of the following values: * @arg ADC_AWD_EVENT: ADC Analog watch Dog event. * @arg ADC_OVR_EVENT: ADC Overrun event. - * @param Timeout: Timeout value in millisecond. + * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) @@ -727,7 +725,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy /** * @brief Enables the interrupt and starts ADC conversion of regular channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status. */ @@ -836,7 +834,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) * * @note Caution: This function will stop also injected channels. * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status. */ @@ -873,7 +871,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) /** * @brief Handles ADC interrupt request - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1016,10 +1014,10 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /** * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from ADC peripheral to memory. + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) @@ -1143,7 +1141,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /** * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -1189,7 +1187,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) /** * @brief Gets the converted value from data register of regular channel. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval Converted value */ @@ -1201,7 +1199,7 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) /** * @brief Regular conversion complete callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1216,7 +1214,7 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) /** * @brief Regular conversion half DMA transfer callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1231,7 +1229,7 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) /** * @brief Analog watchdog callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1252,7 +1250,7 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) * - If needed, restart a new ADC conversion using function * "HAL_ADC_Start_DMA()" * (this function is also clearing overrun flag) - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1289,9 +1287,9 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) /** * @brief Configures for the selected ADC regular channel its corresponding * rank in the sequencer and its sample time. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param sConfig: ADC configuration structure. + * @param sConfig ADC configuration structure. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) @@ -1400,9 +1398,9 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf * Considering that registers write delay may happen due to * bus activity, this might cause an uncertainty on the * effective timing of the new programmed threshold values. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure + * @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure * that contains the configuration information of ADC analog watchdog. * @retval HAL status */ @@ -1484,7 +1482,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG /** * @brief return the ADC state - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL state */ @@ -1496,7 +1494,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) /** * @brief Return the ADC error code - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval ADC Error Code */ @@ -1516,7 +1514,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) /** * @brief Initializes the ADCx peripheral according to the specified parameters * in the ADC_InitStruct without initializing the ADC MSP. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1604,7 +1602,7 @@ static void ADC_Init(ADC_HandleTypeDef* hadc) /** * @brief DMA transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1657,7 +1655,7 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1670,7 +1668,7 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c index 7f781735..5f3a039e 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the ADC extension peripheral: * + Extended features functions @@ -170,7 +168,7 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); /** * @brief Enables the selected ADC software start conversion of the injected channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -264,7 +262,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) /** * @brief Enables the interrupt and starts ADC conversion of injected channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * * @retval HAL status. @@ -369,7 +367,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. * @note In case of auto-injection mode, HAL_ADC_Stop must be used. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) @@ -421,9 +419,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) /** * @brief Poll for injected conversion complete - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param Timeout: Timeout value in millisecond. + * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) @@ -490,7 +488,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u * injected and regular groups, and disable the ADC. * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) @@ -545,9 +543,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) /** * @brief Gets the converted value from data register of injected channel. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param InjectedRank: the ADC injected rank. + * @param InjectedRank the ADC injected rank. * This parameter can be one of the following values: * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected @@ -600,10 +598,10 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa * * @note Caution: This function must be used only with the ADC master. * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param pData: Pointer to buffer in which transferred from ADC peripheral to memory will be stored. - * @param Length: The length of data to be transferred from ADC peripheral to memory. + * @param pData Pointer to buffer in which transferred from ADC peripheral to memory will be stored. + * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) @@ -721,7 +719,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t /** * @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -774,7 +772,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) /** * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results * data in the selected multi mode. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval The converted data value. */ @@ -793,7 +791,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) /** * @brief Injected conversion complete callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -809,9 +807,9 @@ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) /** * @brief Configures for the selected ADC injected channel its corresponding * rank in the sequencer and its sample time. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param sConfigInjected: ADC configuration structure for injected channel. + * @param sConfigInjected ADC configuration structure for injected channel. * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) @@ -972,9 +970,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /** * @brief Configures the ADC multi-mode - * @param hadc : pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param multimode : pointer to an ADC_MultiModeTypeDef structure that contains + * @param multimode pointer to an ADC_MultiModeTypeDef structure that contains * the configuration information for multimode. * @retval HAL status */ @@ -1021,7 +1019,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /** * @brief DMA transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1074,7 +1072,7 @@ static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1087,7 +1085,7 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c index d6aa756d..10dc178d 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c @@ -2,82 +2,135 @@ ****************************************************************************** * @file stm32f4xx_hal_can.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 - * @brief This file provides firmware functions to manage the following + * @brief CAN HAL module driver. + * This file provides firmware functions to manage the following * functionalities of the Controller Area Network (CAN) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions + * + Initialization and de-initialization functions + * + Configuration functions + * + Control functions + * + Interrupts management + * + Callbacks functions * + Peripheral State and Error functions * @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== - [..] - (#) Enable the CAN controller interface clock using - __HAL_RCC_CAN1_CLK_ENABLE() for CAN1, __HAL_RCC_CAN2_CLK_ENABLE() for CAN2 - and __HAL_RCC_CAN3_CLK_ENABLE() for CAN3 - -@- In case you are using CAN2 only, you have to enable the CAN1 clock. - - (#) CAN pins configuration - (++) Enable the clock for the CAN GPIOs using the following function: - __GPIOx_CLK_ENABLE() - (++) Connect and configure the involved CAN pins to AF9 using the - following function HAL_GPIO_Init() - - (#) Initialize and configure the CAN using CAN_Init() function. - - (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function. + [..] + (#) Initialize the CAN low level resources by implementing the + HAL_CAN_MspInit(): + (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE() + (++) Configure CAN pins + (+++) Enable the clock for the CAN GPIOs + (+++) Configure CAN pins as alternate function open-drain + (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification()) + (+++) Configure the CAN interrupt priority using + HAL_NVIC_SetPriority() + (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler() - (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function. - - (#) Receive a CAN frame using HAL_CAN_Receive() function. + (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This + function resorts to HAL_CAN_MspInit() for low-level initialization. - (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function. + (#) Configure the reception filters using the following configuration + functions: + (++) HAL_CAN_ConfigFilter() + + (#) Start the CAN module using HAL_CAN_Start() function. At this level + the node is active on the bus: it receive messages, and can send + messages. + + (#) To manage messages transmission, the following Tx control functions + can be used: + (++) HAL_CAN_AddTxMessage() to request transmission of a new + message. + (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending + message. + (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx + mailboxes. + (++) HAL_CAN_IsTxMessagePending() to check if a message is pending + in a Tx mailbox. + (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message + sent, if time triggered communication mode is enabled. + + (#) When a message is received into the CAN Rx FIFOs, it can be retrieved + using the HAL_CAN_GetRxMessage() function. The function + HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are + stored in the Rx Fifo. + + (#) Calling the HAL_CAN_Stop() function stops the CAN module. + + (#) The deinitialization is achieved with HAL_CAN_DeInit() function. + + + *** Polling mode operation *** + ============================== + [..] + (#) Reception: + (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel() + until at least one message is received. + (++) Then get the message using HAL_CAN_GetRxMessage(). + + (#) Transmission: + (++) Monitor the Tx mailboxes availability until at least one Tx + mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel(). + (++) Then request transmission of a message using + HAL_CAN_AddTxMessage(). + + + *** Interrupt mode operation *** + ================================ + [..] + (#) Notifications are activated using HAL_CAN_ActivateNotification() + function. Then, the process can be controlled through the + available user callbacks: HAL_CAN_xxxCallback(), using same APIs + HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage(). + + (#) Notifications can be deactivated using + HAL_CAN_DeactivateNotification() function. + + (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and + CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig + the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and + HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options + here. + (++) Directly get the Rx message in the callback, using + HAL_CAN_GetRxMessage(). + (++) Or deactivate the notification in the callback without + getting the Rx message. The Rx message can then be got later + using HAL_CAN_GetRxMessage(). Once the Rx message have been + read, the notification can be activated again. + + + *** Sleep mode *** + ================== + [..] + (#) The CAN peripheral can be put in sleep mode (low power), using + HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the + current CAN activity (transmission or reception of a CAN frame) will + be completed. + + (#) A notification can be activated to be informed when the sleep mode + will be entered. + + (#) It can be checked if the sleep mode is entered using + HAL_CAN_IsSleepActive(). + Note that the CAN state (accessible from the API HAL_CAN_GetState()) + is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is + submitted (the sleep mode is not yet entered), and become + HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective. + + (#) The wake-up from sleep mode can be trigged by two ways: + (++) Using HAL_CAN_WakeUp(). When returning from this function, + the sleep mode is exited (if return status is HAL_OK). + (++) When a start of Rx CAN frame is detected by the CAN peripheral, + if automatic wake up mode is enabled. - *** Polling mode IO operation *** - ================================= - [..] - (+) Start the CAN peripheral transmission and wait the end of this operation - using HAL_CAN_Transmit(), at this stage user can specify the value of timeout - according to his end application - (+) Start the CAN peripheral reception and wait the end of this operation - using HAL_CAN_Receive(), at this stage user can specify the value of timeout - according to his end application - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT() - (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT() - (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine - (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_CAN_TxCpltCallback - (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_CAN_ErrorCallback - - *** CAN HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in CAN HAL driver. - - (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts - (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts - (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled - (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags - (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status - - [..] - (@) You can refer to the CAN HAL driver header file for more useful macros - @endverbatim - ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -111,1331 +164,1707 @@ * @{ */ +#if defined(CAN1) + /** @defgroup CAN CAN * @brief CAN driver modules * @{ - */ - -#ifdef HAL_CAN_MODULE_ENABLED + */ + +#ifdef HAL_CAN_MODULE_ENABLED + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" +#endif -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ - defined(STM32F423xx) - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @addtogroup CAN_Private_Constants +/** @defgroup CAN_Private_Constants CAN Private Constants * @{ */ -#define CAN_TIMEOUT_VALUE 10U +#define CAN_TIMEOUT_VALUE 10U /** * @} */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @addtogroup CAN_Private_Functions - * @{ - */ -static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber); -static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); -/** - * @} - */ - /* Exported functions --------------------------------------------------------*/ + /** @defgroup CAN_Exported_Functions CAN Exported Functions * @{ */ -/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Initialize and configure the CAN. - (+) De-initialize the CAN. - + (+) HAL_CAN_Init : Initialize and configure the CAN. + (+) HAL_CAN_DeInit : De-initialize the CAN. + (+) HAL_CAN_MspInit : Initialize the CAN MSP. + (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP. + @endverbatim * @{ */ - + /** * @brief Initializes the CAN peripheral according to the specified * parameters in the CAN_InitStruct. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) { - uint32_t InitStatus = CAN_INITSTATUS_FAILED; uint32_t tickstart = 0U; - + /* Check CAN handle */ - if(hcan == NULL) + if (hcan == NULL) { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP)); - assert_param(IS_CAN_MODE(hcan->Init.Mode)); - assert_param(IS_CAN_SJW(hcan->Init.SJW)); - assert_param(IS_CAN_BS1(hcan->Init.BS1)); - assert_param(IS_CAN_BS2(hcan->Init.BS2)); - assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); - - - if(hcan->State == HAL_CAN_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hcan->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ - HAL_CAN_MspInit(hcan); - } - - /* Initialize the CAN state*/ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Exit from sleep mode */ - hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP); - - /* Request initialisation */ - hcan->Instance->MCR |= CAN_MCR_INRQ ; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - - /* Check acknowledge */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - /* Set the time triggered communication mode */ - if (hcan->Init.TTCM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_TTCM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM; - } - - /* Set the automatic bus-off management */ - if (hcan->Init.ABOM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_ABOM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM; - } - - /* Set the automatic wake-up mode */ - if (hcan->Init.AWUM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_AWUM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM; - } - - /* Set the no automatic retransmission */ - if (hcan->Init.NART == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_NART; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART; - } - - /* Set the receive FIFO locked mode */ - if (hcan->Init.RFLM == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_RFLM; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM; - } - - /* Set the transmit FIFO priority */ - if (hcan->Init.TXFP == ENABLE) - { - hcan->Instance->MCR |= CAN_MCR_TXFP; - } - else - { - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP; - } - - /* Set the bit timing register */ - hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \ - ((uint32_t)hcan->Init.SJW) | \ - ((uint32_t)hcan->Init.BS1) | \ - ((uint32_t)hcan->Init.BS2) | \ - ((uint32_t)hcan->Init.Prescaler - 1U); - - /* Request leave initialisation */ - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - - /* Check acknowledged */ - if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - InitStatus = CAN_INITSTATUS_SUCCESS; - } - } - - if(InitStatus == CAN_INITSTATUS_SUCCESS) - { - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Initialize the CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Initialize the CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - /* Return function status */ return HAL_ERROR; } -} - -/** - * @brief Configures the CAN reception filter according to the specified - * parameters in the CAN_FilterInitStruct. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that - * contains the filter configuration information. - * @retval None - */ -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) -{ - uint32_t filternbrbitpos = 0U; - CAN_TypeDef *can_ip; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); /* Check the parameters */ - assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); - assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); - assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber)); - - filternbrbitpos = 1U << sFilterConfig->FilterNumber; -#if defined (CAN3) - /* Check the CAN instance */ - if(hcan->Instance == CAN3) - { - can_ip = CAN3; + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority)); + assert_param(IS_CAN_MODE(hcan->Init.Mode)); + assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth)); + assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); + assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); + assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); + + if (hcan->State == HAL_CAN_STATE_RESET) + { + /* Init the low level hardware: CLOCK, NVIC */ + HAL_CAN_MspInit(hcan); + } + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check Sleep mode leave acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait initialisation acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET) + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Set the time triggered communication mode */ + if (hcan->Init.TimeTriggeredMode == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); } else { - can_ip = CAN1; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); } -#else - can_ip = CAN1; -#endif - - /* Initialisation mode for the filter */ - can_ip->FMR |= (uint32_t)CAN_FMR_FINIT; -#if defined (CAN2) - /* Select the start slave bank */ - can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB); - can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8U); -#endif - - /* Filter Deactivation */ - can_ip->FA1R &= ~(uint32_t)filternbrbitpos; - - /* Filter Scale */ - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + /* Set the automatic bus-off management */ + if (hcan->Init.AutoBusOff == ENABLE) { - /* 16-bit scale for the filter */ - can_ip->FS1R &= ~(uint32_t)filternbrbitpos; - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); } - - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + else { - /* 32-bit scale for the filter */ - can_ip->FS1R |= filternbrbitpos; - - /* 32-bit identifier or First 32-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); - /* 32-bit mask or Second 32-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); } - /* Filter Mode */ - if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + /* Set the automatic wake-up mode */ + if (hcan->Init.AutoWakeUp == ENABLE) { - /*Id/Mask mode for the filter*/ - can_ip->FM1R &= ~(uint32_t)filternbrbitpos; + SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + else { - /*Identifier list mode for the filter*/ - can_ip->FM1R |= (uint32_t)filternbrbitpos; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); } - /* Filter FIFO assignment */ - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + /* Set the automatic retransmission */ + if (hcan->Init.AutoRetransmission == ENABLE) { - /* FIFO 0 assignation for the filter */ - can_ip->FFA1R &= ~(uint32_t)filternbrbitpos; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); + } + else + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); } - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1) + /* Set the receive FIFO locked mode */ + if (hcan->Init.ReceiveFifoLocked == ENABLE) { - /* FIFO 1 assignation for the filter */ - can_ip->FFA1R |= (uint32_t)filternbrbitpos; + SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); } - - /* Filter activation */ - if (sFilterConfig->FilterActivation == ENABLE) + else { - can_ip->FA1R |= filternbrbitpos; + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); } - /* Leave the initialisation mode for the filter */ - can_ip->FMR &= ~((uint32_t)CAN_FMR_FINIT); - + /* Set the transmit FIFO priority */ + if (hcan->Init.TransmitFifoPriority == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + } + + /* Set the bit timing register */ + WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | + hcan->Init.SyncJumpWidth | + hcan->Init.TimeSeg1 | + hcan->Init.TimeSeg2 | + (hcan->Init.Prescaler - 1U))); + + /* Initialize the error code */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + /* Return function status */ return HAL_OK; } /** - * @brief Deinitializes the CANx peripheral registers to their default reset values. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @brief Deinitializes the CAN peripheral registers to their default + * reset values. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) { /* Check CAN handle */ - if(hcan == NULL) + if (hcan == NULL) { - return HAL_ERROR; + return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* DeInit the low level hardware */ + + /* Stop the CAN module */ + HAL_CAN_Stop(hcan); + + /* DeInit the low level hardware: CLOCK, NVIC */ HAL_CAN_MspDeInit(hcan); - + + /* Reset the CAN peripheral */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + /* Change CAN state */ hcan->State = HAL_CAN_STATE_RESET; - /* Release Lock */ - __HAL_UNLOCK(hcan); - /* Return function status */ return HAL_OK; } /** * @brief Initializes the CAN MSP. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_MspInit could be implemented in the user file - */ + */ } /** * @brief DeInitializes the CAN MSP. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_MspDeInit could be implemented in the user file - */ + */ +} + + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions. + * +@verbatim + ============================================================================== + ##### Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters + +@endverbatim + * @{ + */ + +/** + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that + * contains the filter configuration information. + * @retval None + */ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) +{ + uint32_t filternbrbitpos = 0U; + CAN_TypeDef *can_ip = hcan->Instance; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check the parameters */ + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow)); + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); + +#if defined(CAN3) + /* Check the CAN instance */ + if (hcan->Instance == CAN3) + { + /* CAN3 is single instance with 14 dedicated filters banks */ + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); + } + else + { + /* CAN1 and CAN2 are dual instances with 28 common filters banks */ + /* Select master instance to access the filter banks */ + can_ip = CAN1; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank)); + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); + } +#elif defined(CAN2) + /* CAN1 and CAN2 are dual instances with 28 common filters banks */ + /* Select master instance to access the filter banks */ + can_ip = CAN1; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank)); + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); +#else + /* CAN1 is single instance with 14 dedicated filters banks */ + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); +#endif + + /* Initialisation mode for the filter */ + SET_BIT(can_ip->FMR, CAN_FMR_FINIT); + +#if defined(CAN3) + /* Check the CAN instance */ + if (can_ip == CAN1) + { + /* Select the start filter number of CAN2 slave instance */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); + SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); + } + +#elif defined(CAN2) + /* Select the start filter number of CAN2 slave instance */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); + SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); + +#endif + /* Convert filter number into bit position */ + filternbrbitpos = (1U) << sFilterConfig->FilterBank; + + /* Filter Deactivation */ + CLEAR_BIT(can_ip->FA1R, filternbrbitpos); + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + { + /* 16-bit scale for the filter */ + CLEAR_BIT(can_ip->FS1R, filternbrbitpos); + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + } + + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + { + /* 32-bit scale for the filter */ + SET_BIT(can_ip->FS1R, filternbrbitpos); + + /* 32-bit identifier or First 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* 32-bit mask or Second 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + } + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + { + /* Id/Mask mode for the filter*/ + CLEAR_BIT(can_ip->FM1R, filternbrbitpos); + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /* Identifier list mode for the filter*/ + SET_BIT(can_ip->FM1R, filternbrbitpos); + } + + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); + } + else + { + /* FIFO 1 assignation for the filter */ + SET_BIT(can_ip->FFA1R, filternbrbitpos); + } + + /* Filter activation */ + if (sFilterConfig->FilterActivation == ENABLE) + { + SET_BIT(can_ip->FA1R, filternbrbitpos); + } + + /* Leave the initialisation mode for the filter */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } } /** * @} */ -/** @defgroup CAN_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions +/** @defgroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions * -@verbatim +@verbatim ============================================================================== - ##### IO operation functions ##### + ##### Control functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Transmit a CAN frame message. - (+) Receive a CAN frame message. - (+) Enter CAN peripheral in sleep mode. - (+) Wake up the CAN peripheral from sleep mode. - + (+) HAL_CAN_Start : Start the CAN module + (+) HAL_CAN_Stop : Stop the CAN module + (+) HAL_CAN_RequestSleep : Request sleep mode entry. + (+) HAL_CAN_WakeUp : Wake up from sleep mode. + (+) HAL_CAN_IsSleepActive : Check is sleep mode is active. + (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes + and activate the corresponding + transmission request + (+) HAL_CAN_AbortTxRequest : Abort transmission request + (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level + (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is + pending on the selected Tx mailbox + (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO + (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level + @endverbatim * @{ */ /** - * @brief Initiates and transmits a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param Timeout: Specify Timeout value + * @brief Start the CAN module. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) { - uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; uint32_t tickstart = 0U; - /* Check the parameters */ - assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); - assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); - assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); + if (hcan->State == HAL_CAN_STATE_READY) + { + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_LISTENING; - if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ - ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ - ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) - { - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - case(HAL_CAN_STATE_BUSY_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - } - - /* Select one empty transmit mailbox */ - if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmitmailbox = CAN_TXMAILBOX_0; - } - else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmitmailbox = CAN_TXMAILBOX_1; - } - else - { - transmitmailbox = CAN_TXMAILBOX_2; - } + /* Request leave initialisation */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - /* Set up the Id */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if (hcan->pTxMsg->IDE == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \ - hcan->pTxMsg->RTR); - } - else - { - assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); - } - - /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; - - /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[0U])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[4U])); - /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; - /* Get tick */ tickstart = HAL_GetTick(); - - /* Check End of transmission flag */ - while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) != RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hcan->State = HAL_CAN_STATE_TIMEOUT; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox); + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } + return HAL_ERROR; } } - /* Change CAN state */ - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - default: /* HAL_CAN_STATE_BUSY_TX */ - hcan->State = HAL_CAN_STATE_READY; - break; - } + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - /* Return function status */ return HAL_OK; } else { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; - /* Return function status */ return HAL_ERROR; } } /** - * @brief Initiates and transmits a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @brief Stop the CAN module and enable access to configuration registers. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) -{ - uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; - - /* Check the parameters */ - assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); - assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); - assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - - if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ - ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ - ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) - { - /* Process Locked */ - __HAL_LOCK(hcan); - - /* Select one empty transmit mailbox */ - if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmitmailbox = CAN_TXMAILBOX_0; - } - else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmitmailbox = CAN_TXMAILBOX_1; - } - else - { - transmitmailbox = CAN_TXMAILBOX_2; - } - - /* Set up the Id */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if(hcan->pTxMsg->IDE == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \ - hcan->pTxMsg->RTR); - } - else - { - assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \ - hcan->pTxMsg->IDE | \ - hcan->pTxMsg->RTR); - } - - /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; - - /* Set up the data field */ - hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[0U])); - hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) | - ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) | - ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) | - ((uint32_t)hcan->pTxMsg->Data[4U])); - - /* Change CAN state */ - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - case(HAL_CAN_STATE_BUSY_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - } - - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hcan); - - /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; - - /* Enable Error warning, Error passive, Bus-off, - Last error and Error Interrupts */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR | - CAN_IT_TME); - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - /* Return function status */ - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Receives a correct CAN frame. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber: FIFO Number value - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) { uint32_t tickstart = 0U; - CanRxMsgTypeDef* pRxMsg = NULL; - - /* Check the parameters */ - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Check if CAN state is not busy for RX FIFO0 */ - if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ - (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + if (hcan->State == HAL_CAN_STATE_LISTENING) { - return HAL_BUSY; - } + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - /* Check if CAN state is not busy for RX FIFO1 */ - if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) - { - return HAL_BUSY; - } + /* Get tick */ + tickstart = HAL_GetTick(); - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - if (FIFONumber == CAN_FIFO0) - { - switch(hcan->State) + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET) { - case(HAL_CAN_STATE_BUSY_TX): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - case(HAL_CAN_STATE_BUSY_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - } - } - else /* FIFONumber == CAN_FIFO1 */ - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - case(HAL_CAN_STATE_BUSY_RX0): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - } - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check pending message */ - while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { - hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; } } - } - /* Set RxMsg pointer */ - if(FIFONumber == CAN_FIFO0) - { - pRxMsg = hcan->pRxMsg; - } - else /* FIFONumber == CAN_FIFO1 */ - { - pRxMsg = hcan->pRx1Msg; - } + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - /* Get the Id */ - pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (pRxMsg->IDE == CAN_ID_STD) - { - pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); - } - else - { - pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); - } - - pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); - /* Get the FIFONumber */ - pRxMsg->FIFONumber = FIFONumber; - /* Get the data field */ - pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); - pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); - pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); - pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); - pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); - pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); - - /* Release the FIFO */ - if(FIFONumber == CAN_FIFO0) - { - /* Release FIFO0 */ - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); - } - else /* FIFONumber == CAN_FIFO1 */ - { - /* Release FIFO1 */ - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); - } - - /* Change CAN state */ - if (FIFONumber == CAN_FIFO0) - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - default: /* HAL_CAN_STATE_BUSY_RX0 */ - hcan->State = HAL_CAN_STATE_READY; - break; - } - } - else /* FIFONumber == CAN_FIFO1 */ - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - default: /* HAL_CAN_STATE_BUSY_RX1 */ - hcan->State = HAL_CAN_STATE_READY; - break; - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Receives a correct CAN frame. - * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber: Specify the FIFO number - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_FIFO(FIFONumber)); - - /* Check if CAN state is not busy for RX FIFO0 */ - if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ - (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) - { - return HAL_BUSY; - } - - /* Check if CAN state is not busy for RX FIFO1 */ - if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ - (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) - { - return HAL_BUSY; - } - - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - if(FIFONumber == CAN_FIFO0) - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - case(HAL_CAN_STATE_BUSY_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - } - } - else /* FIFONumber == CAN_FIFO1 */ - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - case(HAL_CAN_STATE_BUSY_RX0): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; - break; - default: /* HAL_CAN_STATE_READY */ - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - } - } - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Enable interrupts: */ - /* - Enable Error warning Interrupt */ - /* - Enable Error passive Interrupt */ - /* - Enable Bus-off Interrupt */ - /* - Enable Last error code Interrupt */ - /* - Enable Error Interrupt */ - /* - Enable Transmit mailbox empty Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR | - CAN_IT_TME); - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - if(FIFONumber == CAN_FIFO0) - { - /* Enable FIFO 0 overrun and message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); - } - else - { - /* Enable FIFO 1 overrun and message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Enters the Sleep (low power) mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) -{ - uint32_t tickstart = 0U; - - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Request Sleep mode */ - hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Sleep mode status */ - if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) - { - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_ERROR; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK) - { - if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - { - hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral - * is in the normal mode. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) -{ - uint32_t tickstart = 0U; - - /* Process locked */ - __HAL_LOCK(hcan); - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY; - - /* Wake up request */ - hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Sleep mode status */ - while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) - { - if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - { - hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; - } - } - if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK) - { - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_ERROR; - } - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Handles CAN interrupt request - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) -{ - uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U; - uint32_t errorcode = HAL_CAN_ERROR_NONE; - - /* Check Overrun flag for FIFO0 */ - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0); - if(tmp1 && tmp2) - { - /* Set CAN error code to FOV0 error */ - errorcode |= HAL_CAN_ERROR_FOV0; - - /* Clear FIFO0 Overrun Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); - } - /* Check Overrun flag for FIFO1 */ - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1); - - if(tmp1 && tmp2) - { - /* Set CAN error code to FOV1 error */ - errorcode |= HAL_CAN_ERROR_FOV1; - - /* Clear FIFO1 Overrun Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); - } - - /* Check End of transmission flag */ - if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME)) - { - tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0); - tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1); - tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2); - if(tmp1 || tmp2 || tmp3) - { - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0); - tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1); - tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2); - /* Check Transmit success */ - if(tmp1 || tmp2 || tmp3) - { - /* Call transmit function */ - CAN_Transmit_IT(hcan); - } - else /* Transmit failure */ - { - /* Set CAN error code to TXFAIL error */ - errorcode |= HAL_CAN_ERROR_TXFAIL; - } - - /* Clear transmission status flags (RQCPx and TXOKx) */ - SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \ - CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2); - } - } - - tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0); - /* Check End of reception flag for FIFO0 */ - if((tmp1 != 0U) && tmp2) - { - /* Call receive function */ - CAN_Receive_IT(hcan, CAN_FIFO0); - } - - tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1); - /* Check End of reception flag for FIFO1 */ - if((tmp1 != 0U) && tmp2) - { - /* Call receive function */ - CAN_Receive_IT(hcan, CAN_FIFO1); - } - - /* Set error code in handle */ - hcan->ErrorCode |= errorcode; - - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG); - tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); - /* Check Error Warning Flag */ - if(tmp1 && tmp2 && tmp3) - { - /* Set CAN error code to EWG error */ - hcan->ErrorCode |= HAL_CAN_ERROR_EWG; - } - - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV); - tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); - /* Check Error Passive Flag */ - if(tmp1 && tmp2 && tmp3) - { - /* Set CAN error code to EPV error */ - hcan->ErrorCode |= HAL_CAN_ERROR_EPV; - } - - tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF); - tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); - /* Check Bus-Off Flag */ - if(tmp1 && tmp2 && tmp3) - { - /* Set CAN error code to BOF error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BOF; - } - - tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC); - tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC); - tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); - /* Check Last error code Flag */ - if((!tmp1) && tmp2 && tmp3) - { - tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC; - switch(tmp1) - { - case(CAN_ESR_LEC_0): - /* Set CAN error code to STF error */ - hcan->ErrorCode |= HAL_CAN_ERROR_STF; - break; - case(CAN_ESR_LEC_1): - /* Set CAN error code to FOR error */ - hcan->ErrorCode |= HAL_CAN_ERROR_FOR; - break; - case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0): - /* Set CAN error code to ACK error */ - hcan->ErrorCode |= HAL_CAN_ERROR_ACK; - break; - case(CAN_ESR_LEC_2): - /* Set CAN error code to BR error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BR; - break; - case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0): - /* Set CAN error code to BD error */ - hcan->ErrorCode |= HAL_CAN_ERROR_BD; - break; - case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1): - /* Set CAN error code to CRC error */ - hcan->ErrorCode |= HAL_CAN_ERROR_CRC; - break; - default: - break; - } - - /* Clear Last error code Flag */ - hcan->Instance->ESR &= ~(CAN_ESR_LEC); - } - - /* Call the Error call Back in case of Errors */ - if(hcan->ErrorCode != HAL_CAN_ERROR_NONE) - { - /* Clear ERRI Flag */ - hcan->Instance->MSR = CAN_MSR_ERRI; - /* Set the CAN state ready to be able to start again the process */ + /* Change CAN peripheral state */ hcan->State = HAL_CAN_STATE_READY; - /* Disable interrupts: */ - /* - Disable Error warning Interrupt */ - /* - Disable Error passive Interrupt */ - /* - Disable Bus-off Interrupt */ - /* - Disable Last error code Interrupt */ - /* - Disable Error Interrupt */ - /* - Disable FIFO 0 message pending Interrupt */ - /* - Disable FIFO 0 Overrun Interrupt */ - /* - Disable FIFO 1 message pending Interrupt */ - /* - Disable FIFO 1 Overrun Interrupt */ - /* - Disable Transmit mailbox empty Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR | - CAN_IT_FMP0| - CAN_IT_FOV0| - CAN_IT_FMP1| - CAN_IT_FOV1| - CAN_IT_TME); + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; - /* Call Error callback function */ - HAL_CAN_ErrorCallback(hcan); - } + return HAL_ERROR; + } } /** - * @brief Transmission complete callback in non blocking mode - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Request the sleep mode (low power) entry. + * When returning from this function, Sleep mode will be entered + * as soon as the current CAN activity (transmission or reception + * of a CAN frame) has been completed. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) +{ + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Request Sleep mode */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Wake up from sleep mode. + * When returning with HAL_OK status from this function, Sleep mode + * is exited. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) +{ + __IO uint32_t count = 0; + uint32_t timeout = 1000000U; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Wake up request */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Wait sleep mode is exited */ + do + { + /* Check if timeout is reached */ + if (++count > timeout) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + return HAL_ERROR; + } + } + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Check is sleep mode is active. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Status + * - 0 : Sleep mode is not active. + * - 1 : Sleep mode is active. + */ +uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) +{ + uint32_t status = 0U; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check Sleep mode */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) + { + status = 1U; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Add a message to the first free Tx mailbox and activate the + * corresponding transmission request. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param pHeader pointer to a CAN_TxHeaderTypeDef structure. + * @param aData array containing the payload of the Tx frame. + * @param pTxMailbox pointer to a variable where the function will return + * the TxMailbox used to store the Tx message. + * This parameter can be a value of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) +{ + uint32_t transmitmailbox; + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(pHeader->IDE)); + assert_param(IS_CAN_RTR(pHeader->RTR)); + assert_param(IS_CAN_DLC(pHeader->DLC)); + if (pHeader->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(pHeader->StdId)); + } + else + { + assert_param(IS_CAN_EXTID(pHeader->ExtId)); + } + assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check that all the Tx mailboxes are not full */ + if (((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) || + ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) || + ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET)) + { + /* Select an empty transmit mailbox */ + transmitmailbox = (hcan->Instance->TSR & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; + + /* Store the Tx mailbox */ + *pTxMailbox = 1U << transmitmailbox; + + /* Set up the Id */ + if (pHeader->IDE == CAN_ID_STD) + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | + pHeader->RTR); + } + else + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + pHeader->IDE | + pHeader->RTR); + } + + /* Set up the DLC */ + hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); + + /* Set up the Transmit Global Time mode */ + if (pHeader->TransmitGlobalTime == ENABLE) + { + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); + } + + /* Set up the data field */ + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, + ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | + ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | + ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | + ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, + ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); + + /* Request transmission */ + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Abort transmission requests + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of the Tx Mailboxes to abort. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check Tx Mailbox 0 */ + if ((TxMailboxes & CAN_TX_MAILBOX0) != RESET) + { + /* Add cancellation request for Tx Mailbox 0 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); + } + + /* Check Tx Mailbox 1 */ + if ((TxMailboxes & CAN_TX_MAILBOX1) != RESET) + { + /* Add cancellation request for Tx Mailbox 1 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); + } + + /* Check Tx Mailbox 2 */ + if ((TxMailboxes & CAN_TX_MAILBOX2) != RESET) + { + /* Add cancellation request for Tx Mailbox 2 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Number of free Tx Mailboxes. + */ +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) +{ + uint32_t freelevel = 0U; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check Tx Mailbox 0 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) + { + freelevel++; + } + + /* Check Tx Mailbox 1 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) + { + freelevel++; + } + + /* Check Tx Mailbox 2 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET) + { + freelevel++; + } + } + + /* Return Tx Mailboxes free level */ + return freelevel; +} + +/** + * @brief Check if a transmission request is pending on the selected Tx + * Mailboxes. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of Tx Mailboxes to check. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval Status + * - 0 : No pending transmission request on any selected Tx Mailboxes. + * - 1 : Pending transmission request on at least one of the selected + * Tx Mailbox. + */ +uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + uint32_t status = 0U; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check pending transmission request on the selected Tx Mailboxes */ + if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos)) + { + status = 1U; + } + } + + /* Return status */ + return status; +} + +/** + * @brief Return timestamp of Tx message sent, if time triggered communication + mode is enabled. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailbox Tx Mailbox where the timestamp of message sent will be + * read. + * This parameter can be one value of @arg CAN_Tx_Mailboxes. + * @retval Timestamp of message sent from Tx Mailbox. + */ +uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) +{ + uint32_t timestamp = 0U; + uint32_t transmitmailbox; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX(TxMailbox)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Select the Tx mailbox */ + transmitmailbox = POSITION_VAL(TxMailbox); + + /* Get timestamp */ + timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos; + } + + /* Return the timestamp */ + return timestamp; +} + +/** + * @brief Get an CAN frame from the Rx FIFO zone into the message RAM. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Fifo number of the received message to be read. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header + * of the Rx frame will be stored. + * @param aData array where the payload of the Rx frame will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) +{ + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check the Rx FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Check that the Rx FIFO 0 is not empty */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == RESET) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */ + { + /* Check that the Rx FIFO 1 is not empty */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == RESET) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + + /* Get the header */ + pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; + if (pHeader->IDE == CAN_ID_STD) + { + pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; + } + else + { + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + } + pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_RTR_Pos; + pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; + pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; + pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; + + /* Get the data */ + aData[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos; + aData[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos; + aData[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos; + aData[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos; + aData[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos; + aData[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos; + aData[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos; + aData[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos; + + /* Release the FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Release RX FIFO 0 */ + SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); + } + else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */ + { + /* Release RX FIFO 1 */ + SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Return Rx FIFO fill level. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Rx FIFO. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @retval Number of messages available in Rx FIFO. + */ +uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo) +{ + uint32_t filllevel = 0U; + + /* Check function parameters */ + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + if (RxFifo == CAN_RX_FIFO0) + { + filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0; + } + else /* RxFifo == CAN_RX_FIFO1 */ + { + filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1; + } + } + + /* Return Rx FIFO fill level */ + return filllevel; +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * +@verbatim + ============================================================================== + ##### Interrupts management ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ActivateNotification : Enable interrupts + (+) HAL_CAN_DeactivateNotification : Disable interrupts + (+) HAL_CAN_IRQHandler : Handles CAN interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Enable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param ActiveITs indicates which interrupts will be enabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) +{ + /* Check function parameters */ + assert_param(IS_CAN_IT(ActiveITs)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Enable the selected interrupts */ + __HAL_CAN_ENABLE_IT(hcan, ActiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param InactiveITs indicates which interrupts will be disabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs) +{ + /* Check function parameters */ + assert_param(IS_CAN_IT(InactiveITs)); + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Disable the selected interrupts */ + __HAL_CAN_DISABLE_IT(hcan, InactiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Handles CAN interrupt request + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan) +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) +{ + uint32_t errorcode = HAL_CAN_ERROR_NONE; + uint32_t interrupts = READ_REG(hcan->Instance->IER); + uint32_t msrflags = READ_REG(hcan->Instance->MSR); + uint32_t tsrflags = READ_REG(hcan->Instance->TSR); + uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); + uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); + uint32_t esrflags = READ_REG(hcan->Instance->ESR); + + /* Transmit Mailbox empty interrupt management *****************************/ + if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != RESET) + { + /* Transmit Mailbox 0 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP0) != RESET) + { + /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); + + if ((tsrflags & CAN_TSR_TXOK0) != RESET) + { + /* Transmission Mailbox 0 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0CompleteCallback(hcan); + } + else + { + if ((tsrflags & CAN_TSR_ALST0) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST0; + } + else if ((tsrflags & CAN_TSR_TERR0) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR0; + } + else + { + /* Transmission Mailbox 0 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0AbortCallback(hcan); + } + } + } + + /* Transmit Mailbox 1 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP1) != RESET) + { + /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); + + if ((tsrflags & CAN_TSR_TXOK1) != RESET) + { + /* Transmission Mailbox 1 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1CompleteCallback(hcan); + } + else + { + if ((tsrflags & CAN_TSR_ALST1) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST1; + } + else if ((tsrflags & CAN_TSR_TERR1) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR1; + } + else + { + /* Transmission Mailbox 1 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1AbortCallback(hcan); + } + } + } + + /* Transmit Mailbox 2 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP2) != RESET) + { + /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); + + if ((tsrflags & CAN_TSR_TXOK2) != RESET) + { + /* Transmission Mailbox 2 complete callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2CompleteCallback(hcan); + } + else + { + if ((tsrflags & CAN_TSR_ALST2) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST2; + } + else if ((tsrflags & CAN_TSR_TERR2) != RESET) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR2; + } + else + { + /* Transmission Mailbox 2 abort callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2AbortCallback(hcan); + } + } + } + } + + /* Receive FIFO 0 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != RESET) + { + if ((rf0rflags & CAN_RF0R_FOVR0) != RESET) + { + /* Set CAN error code to Rx Fifo 0 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } + } + + /* Receive FIFO 0 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO0_FULL) != RESET) + { + if ((rf0rflags & CAN_RF0R_FULL0) != RESET) + { + /* Clear FIFO 0 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); + + /* Receive FIFO 0 full Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0FullCallback(hcan); + } + } + + /* Receive FIFO 0 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != RESET) + { + /* Check if message is still pending */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != RESET) + { + /* Receive FIFO 0 mesage pending Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0MsgPendingCallback(hcan); + } + } + + /* Receive FIFO 1 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != RESET) + { + if ((rf1rflags & CAN_RF1R_FOVR1) != RESET) + { + /* Set CAN error code to Rx Fifo 1 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } + } + + /* Receive FIFO 1 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO1_FULL) != RESET) + { + if ((rf1rflags & CAN_RF1R_FULL1) != RESET) + { + /* Clear FIFO 1 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); + + /* Receive FIFO 1 full Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1FullCallback(hcan); + } + } + + /* Receive FIFO 1 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != RESET) + { + /* Check if message is still pending */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != RESET) + { + /* Receive FIFO 1 mesage pending Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1MsgPendingCallback(hcan); + } + } + + /* Sleep interrupt management *********************************************/ + if ((interrupts & CAN_IT_SLEEP_ACK) != RESET) + { + if ((msrflags & CAN_MSR_SLAKI) != RESET) + { + /* Clear Sleep interrupt Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); + + /* Sleep Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_SleepCallback(hcan); + } + } + + /* WakeUp interrupt management *********************************************/ + if ((interrupts & CAN_IT_WAKEUP) != RESET) + { + if ((msrflags & CAN_MSR_WKUI) != RESET) + { + /* Clear WakeUp Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); + + /* WakeUp Callback */ + /* Call weak (surcharged) callback */ + HAL_CAN_WakeUpFromRxMsgCallback(hcan); + } + } + + /* Error interrupts management *********************************************/ + if ((interrupts & CAN_IT_ERROR) != RESET) + { + if ((msrflags & CAN_MSR_ERRI) != RESET) + { + /* Check Error Warning Flag */ + if (((interrupts & CAN_IT_ERROR_WARNING) != RESET) && + ((esrflags & CAN_ESR_EWGF) != RESET)) + { + /* Set CAN error code to Error Warning */ + errorcode |= HAL_CAN_ERROR_EWG; + + /* No need for clear of Error Warning Flag as read-only */ + } + + /* Check Error Passive Flag */ + if (((interrupts & CAN_IT_ERROR_PASSIVE) != RESET) && + ((esrflags & CAN_ESR_EPVF) != RESET)) + { + /* Set CAN error code to Error Passive */ + errorcode |= HAL_CAN_ERROR_EPV; + + /* No need for clear of Error Passive Flag as read-only */ + } + + /* Check Bus-off Flag */ + if (((interrupts & CAN_IT_BUSOFF) != RESET) && + ((esrflags & CAN_ESR_BOFF) != RESET)) + { + /* Set CAN error code to Bus-Off */ + errorcode |= HAL_CAN_ERROR_BOF; + + /* No need for clear of Error Bus-Off as read-only */ + } + + /* Check Last Error Code Flag */ + if (((interrupts & CAN_IT_LAST_ERROR_CODE) != RESET) && + ((esrflags & CAN_ESR_LEC) != RESET)) + { + switch (esrflags & CAN_ESR_LEC) + { + case (CAN_ESR_LEC_0): + /* Set CAN error code to Stuff error */ + errorcode |= HAL_CAN_ERROR_STF; + break; + case (CAN_ESR_LEC_1): + /* Set CAN error code to Form error */ + errorcode |= HAL_CAN_ERROR_FOR; + break; + case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + /* Set CAN error code to Acknowledgement error */ + errorcode |= HAL_CAN_ERROR_ACK; + break; + case (CAN_ESR_LEC_2): + /* Set CAN error code to Bit recessive error */ + errorcode |= HAL_CAN_ERROR_BR; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + /* Set CAN error code to Bit Dominant error */ + errorcode |= HAL_CAN_ERROR_BD; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + errorcode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + } + + /* Clear Last error code Flag */ + CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); + } + } + + /* Clear ERRI Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); + } + + /* Call the Error call Back in case of Errors */ + if (errorcode != HAL_CAN_ERROR_NONE) + { + /* Update error code in handle */ + hcan->ErrorCode |= errorcode; + + /* Call Error callback function */ + /* Call weak (surcharged) callback */ + HAL_CAN_ErrorCallback(hcan); + } +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group5 Callback functions + * @brief CAN Callback functions + * +@verbatim + ============================================================================== + ##### Callback functions ##### + ============================================================================== + [..] + This subsection provides the following callback functions: + (+) HAL_CAN_TxMailbox0CompleteCallback + (+) HAL_CAN_TxMailbox1CompleteCallback + (+) HAL_CAN_TxMailbox2CompleteCallback + (+) HAL_CAN_TxMailbox0AbortCallback + (+) HAL_CAN_TxMailbox1AbortCallback + (+) HAL_CAN_TxMailbox2AbortCallback + (+) HAL_CAN_RxFifo0MsgPendingCallback + (+) HAL_CAN_RxFifo0FullCallback + (+) HAL_CAN_RxFifo1MsgPendingCallback + (+) HAL_CAN_RxFifo1FullCallback + (+) HAL_CAN_SleepCallback + (+) HAL_CAN_WakeUpFromRxMsgCallback + (+) HAL_CAN_ErrorCallback + +@endverbatim + * @{ + */ + +/** + * @brief Transmission Mailbox 0 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxCpltCallback could be implemented in the user file + the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the + user file */ } /** - * @brief Transmission complete callback in non blocking mode - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Transmission Mailbox 1 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ -__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan) +__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_RxCpltCallback could be implemented in the user file + the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 0 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 1 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Rx FIFO 1 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 1 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Sleep callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_SleepCallback could be implemented in the user file + */ +} + +/** + * @brief WakeUp from Rx message callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the + user file */ } /** * @brief Error CAN callback. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval None */ @@ -1443,6 +1872,7 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcan); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_CAN_ErrorCallback could be implemented in the user file */ @@ -1452,230 +1882,110 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) * @} */ -/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions - * @brief CAN Peripheral State functions - * -@verbatim +/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * +@verbatim ============================================================================== ##### Peripheral State and Error functions ##### ============================================================================== [..] This subsection provides functions allowing to : - (+) Check the CAN state. - (+) Check CAN Errors detected during interrupt process - + (+) HAL_CAN_GetState() : Return the CAN state. + (+) HAL_CAN_GetError() : Return the CAN error codes if any. + (+) HAL_CAN_ResetError(): Reset the CAN error codes if any. + @endverbatim * @{ */ /** - * @brief return the CAN state - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Return the CAN state. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL state */ -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan) +HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan) { + HAL_CAN_StateTypeDef state = hcan->State; + + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) + { + /* Check sleep mode acknowledge flag */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET) + { + /* Sleep mode is active */ + state = HAL_CAN_STATE_SLEEP_ACTIVE; + } + /* Check sleep mode request flag */ + else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != RESET) + { + /* Sleep mode request is pending */ + state = HAL_CAN_STATE_SLEEP_PENDING; + } + } + /* Return CAN state */ - return hcan->State; + return state; } /** - * @brief Return the CAN error code - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains + * @brief Return the CAN error code. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval CAN Error Code */ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) { + /* Return CAN error code */ return hcan->ErrorCode; } /** - * @} - */ -/** - * @brief Initiates and transmits a CAN frame message. - * @param hcan: pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. + * @brief Reset the CAN error code. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. * @retval HAL status */ -static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) { - /* Disable Transmit mailbox empty Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) - { - /* Disable Error warning, Error passive, Bus-off, Last error code - and Error Interrupts */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR ); - } + HAL_StatusTypeDef status = HAL_OK; - /* Change CAN state */ - switch(hcan->State) + if ((hcan->State == HAL_CAN_STATE_READY) || + (hcan->State == HAL_CAN_STATE_LISTENING)) { - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; - break; - default: /* HAL_CAN_STATE_BUSY_TX */ - hcan->State = HAL_CAN_STATE_READY; - break; - } - - /* Transmission complete callback */ - HAL_CAN_TxCpltCallback(hcan); - - return HAL_OK; -} - -/** - * @brief Receives a correct CAN frame. - * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param FIFONumber: Specify the FIFO number - * @retval HAL status - * @retval None - */ -static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) -{ - uint32_t tmp1 = 0U; - CanRxMsgTypeDef* pRxMsg = NULL; - - /* Set RxMsg pointer */ - if(FIFONumber == CAN_FIFO0) - { - pRxMsg = hcan->pRxMsg; - } - else /* FIFONumber == CAN_FIFO1 */ - { - pRxMsg = hcan->pRx1Msg; - } - - /* Get the Id */ - pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (pRxMsg->IDE == CAN_ID_STD) - { - pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); + /* Reset CAN error code */ + hcan->ErrorCode = 0U; } else { - pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); - } - - pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FIFONumber */ - pRxMsg->FIFONumber = FIFONumber; - /* Get the FMI */ - pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); - /* Get the data field */ - pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); - pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); - pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); - pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); - pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); - pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); - /* Release the FIFO */ - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - /* Disable FIFO 0 overrun and message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); - - /* Disable FIFO 1 overrun and message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); + status = HAL_ERROR; } - tmp1 = hcan->State; - if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1)) - { - /* Disable Error warning, Error passive, Bus-off, Last error code - and Error Interrupts */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR); - } - - /* Change CAN state */ - if (FIFONumber == CAN_FIFO0) - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX_RX0): - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX1; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; - break; - default: /* HAL_CAN_STATE_BUSY_RX0 */ - hcan->State = HAL_CAN_STATE_READY; - break; - } - } - else /* FIFONumber == CAN_FIFO1 */ - { - switch(hcan->State) - { - case(HAL_CAN_STATE_BUSY_TX_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX; - break; - case(HAL_CAN_STATE_BUSY_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_RX0; - break; - case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): - hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; - break; - default: /* HAL_CAN_STATE_BUSY_RX1 */ - hcan->State = HAL_CAN_STATE_READY; - break; - } - } - - /* Receive complete callback */ - HAL_CAN_RxCpltCallback(hcan); - - /* Return function status */ - return HAL_OK; + /* Return the status */ + return status; } /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ - STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ - STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ -#endif /* HAL_CAN_MODULE_ENABLED */ /** * @} */ +#endif /* HAL_CAN_MODULE_ENABLED */ + +/** + * @} + */ + +#endif /* CAN1 */ + /** * @} */ diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c index c8e0c5fc..c277ebf6 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_cortex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: @@ -142,7 +140,7 @@ /** * @brief Sets the priority grouping field (preemption priority and subpriority) * using the required unlock sequence. - * @param PriorityGroup: The priority grouping bits length. + * @param PriorityGroup The priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority * 4 bits for subpriority @@ -169,13 +167,13 @@ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) /** * @brief Sets the priority of an interrupt. - * @param IRQn: External interrupt number. + * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) - * @param PreemptPriority: The preemption priority for the IRQn channel. + * @param PreemptPriority The preemption priority for the IRQn channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority - * @param SubPriority: the subpriority level for the IRQ channel. + * @param SubPriority the subpriority level for the IRQ channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None @@ -240,7 +238,7 @@ void HAL_NVIC_SystemReset(void) /** * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. * Counter is in free running mode to generate periodic interrupts. - * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ @@ -287,7 +285,7 @@ void HAL_MPU_Disable(void) /** * @brief Enable the MPU. - * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * @param MPU_Control Specifies the control mode of the MPU during hard fault, * NMI, FAULTMASK and privileged access to the default memory * This parameter can be one of the following values: * @arg MPU_HFNMI_PRIVDEF_NONE @@ -311,7 +309,7 @@ void HAL_MPU_Enable(uint32_t MPU_Control) /** * @brief Initializes and configures the Region and the memory to be protected. - * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains + * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ @@ -367,10 +365,10 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void) /** * @brief Gets the priority of an interrupt. - * @param IRQn: External interrupt number. + * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) - * @param PriorityGroup: the priority grouping bits length. + * @param PriorityGroup the priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority * 4 bits for subpriority @@ -382,8 +380,8 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void) * 1 bits for subpriority * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority * 0 bits for subpriority - * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). - * @param pSubPriority: Pointer on the Subpriority value (starting from 0). + * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority Pointer on the Subpriority value (starting from 0). * @retval None */ void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) @@ -463,7 +461,7 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) /** * @brief Configures the SysTick clock source. - * @param CLKSource: specifies the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. * This parameter can be one of the following values: * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c index f30c8aec..b7efc719 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dma.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief DMA HAL module driver. * * This file provides firmware functions to manage the following @@ -182,7 +180,7 @@ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); /** * @brief Initialize the DMA according to the specified * parameters in the DMA_InitTypeDef and create the associated handle. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ @@ -321,7 +319,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /** * @brief DeInitializes the DMA peripheral - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ @@ -408,11 +406,11 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) /** * @brief Starts the DMA Transfer. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) @@ -452,11 +450,11 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui /** * @brief Start the DMA Transfer with interrupt enabled. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) @@ -512,7 +510,7 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, /** * @brief Aborts the DMA Transfer. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * * @note After disabling a DMA Stream, a check for wait until the DMA Stream is @@ -585,7 +583,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) /** * @brief Aborts the DMA Transfer in Interrupt mode. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ @@ -610,13 +608,13 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) /** * @brief Polling for transfer complete. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param CompleteLevel: Specifies the DMA level complete. + * @param CompleteLevel Specifies the DMA level complete. * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead. * This model could be used for debug purpose. * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). - * @param Timeout: Timeout duration. + * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) @@ -751,7 +749,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level /** * @brief Handles DMA interrupt request. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ @@ -968,11 +966,11 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /** * @brief Register callbacks - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param CallbackID: User Callback identifer + * @param CallbackID User Callback identifer * a DMA_HandleTypeDef structure as parameter. - * @param pCallback: pointer to private callbacsk function which has pointer to + * @param pCallback pointer to private callbacsk function which has pointer to * a DMA_HandleTypeDef structure as parameter. * @retval HAL status */ @@ -1030,9 +1028,9 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call /** * @brief UnRegister callbacks - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param CallbackID: User Callback identifer + * @param CallbackID User Callback identifer * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @retval HAL status */ @@ -1117,7 +1115,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca /** * @brief Returns the DMA state. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL state */ @@ -1128,7 +1126,7 @@ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) /** * @brief Return the DMA error code - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval DMA Error Code */ @@ -1151,11 +1149,11 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) /** * @brief Sets the DMA Transfer parameter. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) @@ -1166,7 +1164,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t /* Configure DMA Stream data length */ hdma->Instance->NDTR = DataLength; - /* Peripheral to Memory */ + /* Memory to Peripheral */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) { /* Configure DMA Stream destination address */ @@ -1175,7 +1173,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t /* Configure DMA Stream source address */ hdma->Instance->M0AR = SrcAddress; } - /* Memory to Peripheral */ + /* Peripheral to Memory */ else { /* Configure DMA Stream source address */ @@ -1188,7 +1186,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t /** * @brief Returns the DMA Stream base address depending on stream number - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval Stream base address */ @@ -1216,7 +1214,7 @@ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) /** * @brief Check compatibility between FIFO threshold level and size of the memory burst - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c index 71e02019..48cfd776 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dma_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief DMA Extension HAL module driver * This file provides firmware functions to manage the following * functionalities of the DMA Extension peripheral: @@ -108,12 +106,12 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddres /** * @brief Starts the multi_buffer DMA Transfer. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) @@ -162,12 +160,12 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t S /** * @brief Starts the multi_buffer DMA Transfer with interrupt enabled. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) @@ -243,10 +241,10 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_ /** * @brief Change the memory0 or memory1 address on the fly. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param Address: The new address - * @param memory: the memory to be changed, This parameter can be one of + * @param Address The new address + * @param memory the memory to be changed, This parameter can be one of * the following values: * MEMORY0 / * MEMORY1 @@ -285,11 +283,11 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre /** * @brief Set the DMA Transfer parameter. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c index d8cda32c..a7525847 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_flash.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: @@ -164,10 +162,10 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); /** * @brief Program byte, halfword, word or double word at a specified address - * @param TypeProgram: Indicate the way to program at a specified address. + * @param TypeProgram Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed * * @retval HAL_StatusTypeDef HAL Status */ @@ -222,10 +220,10 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint /** * @brief Program byte, halfword, word or double word at a specified address with interrupt enabled. - * @param TypeProgram: Indicate the way to program at a specified address. + * @param TypeProgram Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed * * @retval HAL Status */ @@ -392,7 +390,7 @@ void HAL_FLASH_IRQHandler(void) /** * @brief FLASH end of operation interrupt callback - * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure * Mass Erase: Bank number which has been requested to erase * Sectors Erase: Sector which has been erased * (if 0xFFFFFFFFU, it means that all the selected sectors have been erased) @@ -410,7 +408,7 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) /** * @brief FLASH operation error interrupt callback - * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure * Mass Erase: Bank number which has been requested to erase * Sectors Erase: Sector number which returned an error * Program: Address which was selected for data program @@ -450,18 +448,22 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { - if((FLASH->CR & FLASH_CR_LOCK) != RESET) + HAL_StatusTypeDef status = HAL_OK; + + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) { /* Authorize the FLASH Registers access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + + /* Verify Flash is unlocked */ + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + status = HAL_ERROR; + } } - else - { - return HAL_ERROR; - } - - return HAL_OK; + + return status; } /** @@ -560,7 +562,7 @@ uint32_t HAL_FLASH_GetError(void) /** * @brief Wait for a FLASH operation to complete. - * @param Timeout: maximum flash operationtimeout + * @param Timeout maximum flash operationtimeout * @retval HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) @@ -619,8 +621,8 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. * @retval None */ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) @@ -647,8 +649,8 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. * @retval None */ static void FLASH_Program_Word(uint32_t Address, uint32_t Data) @@ -672,8 +674,8 @@ static void FLASH_Program_Word(uint32_t Address, uint32_t Data) * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. * @retval None */ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) @@ -697,8 +699,8 @@ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. * @retval None */ static void FLASH_Program_Byte(uint32_t Address, uint8_t Data) diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c index 0d4f0f83..7b5eff69 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_flash_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Extended FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the FLASH extension peripheral: @@ -168,10 +166,10 @@ extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); */ /** * @brief Perform a mass erase or erase the specified FLASH memory sectors - * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. * - * @param[out] SectorError: pointer to variable that + * @param[out] SectorError pointer to variable that * contains the configuration information on faulty sector in case of error * (0xFFFFFFFFU means that all the sectors have been correctly erased) * @@ -243,7 +241,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /** * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled - * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. * * @retval HAL Status @@ -296,7 +294,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) /** * @brief Program option bytes - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that + * @param pOBInit pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. * * @retval HAL Status @@ -355,7 +353,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) /** * @brief Get the Option byte configuration - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that + * @param pOBInit pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. * * @retval None @@ -384,7 +382,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /** * @brief Program option bytes - * @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that + * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that * contains the configuration information for the programming. * * @retval HAL Status @@ -440,7 +438,7 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO /** * @brief Get the OBEX byte configuration - * @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that + * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that * contains the configuration information for the programming. * * @retval None @@ -538,7 +536,7 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void) #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /** * @brief Full erase of FLASH memory sectors - * @param VoltageRange: The device voltage range which defines the erase parallelism. + * @param VoltageRange The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, * the operation will be done by byte (8-bit) @@ -549,7 +547,7 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void) * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, * the operation will be done by double word (64-bit) * - * @param Banks: Banks to be erased + * @param Banks Banks to be erased * This parameter can be one of the following values: * @arg FLASH_BANK_1: Bank1 to be erased * @arg FLASH_BANK_2: Bank2 to be erased @@ -586,9 +584,9 @@ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) /** * @brief Erase the specified FLASH memory sector - * @param Sector: FLASH sector to erase + * @param Sector FLASH sector to erase * The value of this parameter depend on device used within the same series - * @param VoltageRange: The device voltage range which defines the erase parallelism. + * @param VoltageRange The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, * the operation will be done by byte (8-bit) @@ -635,7 +633,7 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); FLASH->CR |= tmp_psize; CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); - FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB)); + FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); FLASH->CR |= FLASH_CR_STRT; } @@ -647,13 +645,13 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). * - * @param WRPSector: specifies the sector(s) to be write protected. + * @param WRPSector specifies the sector(s) to be write protected. * This parameter can be one of the following values: * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23 * @arg OB_WRP_SECTOR_All * @note BANK2 starts from OB_WRP_SECTOR_12 * - * @param Banks: Enable write protection on all the sectors for the specific bank + * @param Banks Enable write protection on all the sectors for the specific bank * This parameter can be one of the following values: * @arg FLASH_BANK_1: WRP on all sectors of bank1 * @arg FLASH_BANK_2: WRP on all sectors of bank2 @@ -718,13 +716,13 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). * - * @param WRPSector: specifies the sector(s) to be write protected. + * @param WRPSector specifies the sector(s) to be write protected. * This parameter can be one of the following values: * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23 * @arg OB_WRP_Sector_All * @note BANK2 starts from OB_WRP_SECTOR_12 * - * @param Banks: Disable write protection on all the sectors for the specific bank + * @param Banks Disable write protection on all the sectors for the specific bank * This parameter can be one of the following values: * @arg FLASH_BANK_1: Bank1 to be erased * @arg FLASH_BANK_2: Bank2 to be erased @@ -951,7 +949,7 @@ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t Se defined(STM32F423xx) /** * @brief Mass erase of FLASH memory - * @param VoltageRange: The device voltage range which defines the erase parallelism. + * @param VoltageRange The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, * the operation will be done by byte (8-bit) @@ -962,7 +960,7 @@ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t Se * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, * the operation will be done by double word (64-bit) * - * @param Banks: Banks to be erased + * @param Banks Banks to be erased * This parameter can be one of the following values: * @arg FLASH_BANK_1: Bank1 to be erased * @@ -982,9 +980,9 @@ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) /** * @brief Erase the specified FLASH memory sector - * @param Sector: FLASH sector to erase + * @param Sector FLASH sector to erase * The value of this parameter depend on device used within the same series - * @param VoltageRange: The device voltage range which defines the erase parallelism. + * @param VoltageRange The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, * the operation will be done by byte (8-bit) @@ -1026,7 +1024,7 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); FLASH->CR |= tmp_psize; CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); - FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB)); + FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); FLASH->CR |= FLASH_CR_STRT; } @@ -1038,10 +1036,10 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). * - * @param WRPSector: specifies the sector(s) to be write protected. + * @param WRPSector specifies the sector(s) to be write protected. * The value of this parameter depend on device used within the same series * - * @param Banks: Enable write protection on all the sectors for the specific bank + * @param Banks Enable write protection on all the sectors for the specific bank * This parameter can be one of the following values: * @arg FLASH_BANK_1: WRP on all sectors of bank1 * @@ -1074,10 +1072,10 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). * - * @param WRPSector: specifies the sector(s) to be write protected. + * @param WRPSector specifies the sector(s) to be write protected. * The value of this parameter depend on device used within the same series * - * @param Banks: Enable write protection on all the sectors for the specific bank + * @param Banks Enable write protection on all the sectors for the specific bank * This parameter can be one of the following values: * @arg FLASH_BANK_1: WRP on all sectors of bank1 * @@ -1167,7 +1165,7 @@ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector) /** * @brief Set the read protection level. - * @param Level: specifies the read protection level. + * @param Level specifies the read protection level. * This parameter can be one of the following values: * @arg OB_RDP_LEVEL_0: No protection * @arg OB_RDP_LEVEL_1: Read protection of the memory @@ -1197,15 +1195,15 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level) /** * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param Iwdg: Selects the IWDG mode + * @param Iwdg Selects the IWDG mode * This parameter can be one of the following values: * @arg OB_IWDG_SW: Software IWDG selected * @arg OB_IWDG_HW: Hardware IWDG selected - * @param Stop: Reset event when entering STOP mode. + * @param Stop Reset event when entering STOP mode. * This parameter can be one of the following values: * @arg OB_STOP_NO_RST: No reset generated when entering in STOP * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param Stdby: Reset event when entering Standby mode. + * @param Stdby Reset event when entering Standby mode. * This parameter can be one of the following values: * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY * @arg OB_STDBY_RST: Reset generated when entering in STANDBY @@ -1238,7 +1236,7 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t /** * @brief Set the BOR Level. - * @param Level: specifies the Option Bytes BOR Reset Level. + * @param Level specifies the Option Bytes BOR Reset Level. * This parameter can be one of the following values: * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c index 0955b800..fab41154 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_flash_ramfunc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief FLASH RAMFUNC module driver. * This file provides a FLASH firmware functions which should be * executed from internal SRAM diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c index 876b37bb..1430d188 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_gpio.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: @@ -180,9 +178,9 @@ /** * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. - * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ @@ -305,9 +303,9 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /** * @brief De-initializes the GPIOx peripheral registers to their default reset values. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. - * @param GPIO_Pin: specifies the port bit to be written. + * @param GPIO_Pin specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). * @retval None */ @@ -386,9 +384,9 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /** * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. - * @param GPIO_Pin: specifies the port bit to read. + * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ @@ -417,11 +415,11 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. * - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. - * @param GPIO_Pin: specifies the port bit to be written. + * @param GPIO_Pin specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @param PinState: specifies the value to be written to the selected bit. + * @param PinState specifies the value to be written to the selected bit. * This parameter can be one of the GPIO_PinState enum values: * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin @@ -445,9 +443,9 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin /** * @brief Toggles the specified GPIO pins. - * @param GPIOx: Where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * @param GPIOx Where x can be (A..K) to select the GPIO peripheral for STM32F429X device or * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. - * @param GPIO_Pin: Specifies the pins to be toggled. + * @param GPIO_Pin Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) @@ -464,8 +462,8 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. * @note The configuration of the locked GPIO pins can no longer be modified * until the next reset. - * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F4 family - * @param GPIO_Pin: specifies the port bit to be locked. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F4 family + * @param GPIO_Pin specifies the port bit to be locked. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @retval None */ @@ -499,7 +497,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /** * @brief This function handles EXTI interrupt request. - * @param GPIO_Pin: Specifies the pins connected EXTI line + * @param GPIO_Pin Specifies the pins connected EXTI line * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) @@ -514,7 +512,7 @@ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) /** * @brief EXTI line detection callbacks. - * @param GPIO_Pin: Specifies the pins connected EXTI line + * @param GPIO_Pin Specifies the pins connected EXTI line * @retval None */ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c index 446583af..a2300a3e 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_pcd.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -133,7 +131,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t /** * @brief Initializes the PCD according to the specified * parameters in the PCD_InitTypeDef and initialize the associated handle. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) @@ -218,7 +216,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /** * @brief DeInitializes the PCD peripheral. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) @@ -244,7 +242,7 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) /** * @brief Initializes the PCD MSP. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) @@ -258,7 +256,7 @@ __weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) /** * @brief DeInitializes PCD MSP. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) @@ -291,7 +289,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) /** * @brief Start The USB OTG Device. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) @@ -305,7 +303,7 @@ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) /** * @brief Stop The USB OTG Device. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) @@ -320,7 +318,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) /** * @brief Handles PCD interrupt request. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) @@ -717,8 +715,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Data OUT stage callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -733,8 +731,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Data IN stage callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -748,7 +746,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } /** * @brief Setup stage callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) @@ -762,7 +760,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief USB Start Of Frame callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) @@ -776,7 +774,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief USB Reset callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) @@ -790,7 +788,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Suspend event callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) @@ -804,7 +802,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Resume event callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) @@ -818,8 +816,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Incomplete ISO OUT callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -834,8 +832,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Incomplete ISO IN callback. - * @param hpcd: PCD handle - * @param epnum: endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval None */ __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -850,7 +848,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Connection event callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) @@ -864,7 +862,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Disconnection event callback. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval None */ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) @@ -897,7 +895,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /** * @brief Connect the USB device. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) @@ -910,7 +908,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) /** * @brief Disconnect the USB device. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) @@ -923,8 +921,8 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) /** * @brief Set the USB Device address. - * @param hpcd: PCD handle - * @param address: new device address + * @param hpcd PCD handle + * @param address new device address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) @@ -936,10 +934,10 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) } /** * @brief Open and configure an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param ep_mps: endpoint max packet size - * @param ep_type: endpoint type + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param ep_mps endpoint max packet size + * @param ep_type endpoint type * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) @@ -980,8 +978,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint /** * @brief Deactivate an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) @@ -1009,10 +1007,10 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) /** * @brief Receive an amount of data. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param pBuf: pointer to the reception buffer - * @param len: amount of data to be received + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the reception buffer + * @param len amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) @@ -1047,8 +1045,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u /** * @brief Get Received Data Size. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval Data Size */ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) @@ -1057,10 +1055,10 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) } /** * @brief Send an amount of data. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address - * @param pBuf: pointer to the transmission buffer - * @param len: amount of data to be sent + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the transmission buffer + * @param len amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) @@ -1095,8 +1093,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, /** * @brief Set a STALL condition over an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) @@ -1130,8 +1128,8 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) /** * @brief Clear a STALL condition over in an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) @@ -1160,8 +1158,8 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) /** * @brief Flush an endpoint. - * @param hpcd: PCD handle - * @param ep_addr: endpoint address + * @param hpcd PCD handle + * @param ep_addr endpoint address * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) @@ -1184,7 +1182,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) /** * @brief Activate remote wakeup signalling. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) @@ -1201,7 +1199,7 @@ HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) /** * @brief De-activate remote wakeup signalling. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) @@ -1233,7 +1231,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) /** * @brief Return the PCD handle state. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL state */ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) @@ -1255,8 +1253,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) /** * @brief Check FIFO for the next packet to be loaded. - * @param hpcd: PCD handle - * @param epnum : endpoint number + * @param hpcd PCD handle + * @param epnum endpoint number * @retval HAL status */ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c index 401fcfc2..f7d754db 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -83,9 +81,9 @@ /** * @brief Set Tx FIFO - * @param hpcd: PCD handle - * @param fifo: The number of Tx fifo - * @param size: Fifo size + * @param hpcd PCD handle + * @param fifo The number of Tx fifo + * @param size Fifo size * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) @@ -126,8 +124,8 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin /** * @brief Set Rx FIFO - * @param hpcd: PCD handle - * @param size: Size of Rx fifo + * @param hpcd PCD handle + * @param size Size of Rx fifo * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) @@ -141,7 +139,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /** * @brief Activate LPM feature - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) @@ -158,7 +156,7 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) /** * @brief Deactivate LPM feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) @@ -174,8 +172,8 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) /** * @brief Send LPM message to user layer callback. - * @param hpcd: PCD handle - * @param msg: LPM message + * @param hpcd PCD handle + * @param msg LPM message * @retval HAL status */ __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) @@ -189,7 +187,7 @@ __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef m #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /** * @brief HAL_PCDEx_BCD_VBUSDetect : handle BatteryCharging Process - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) @@ -260,7 +258,7 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) /** * @brief HAL_PCDEx_ActivateBCD : active BatteryCharging feature - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) @@ -275,7 +273,7 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) /** * @brief HAL_PCDEx_DeActivateBCD : de-active BatteryCharging feature - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) @@ -288,8 +286,8 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) /** * @brief HAL_PCDEx_BatteryCharging_Callback : Send BatteryCharging message to user layer - * @param hpcd: PCD handle - * @param msg: LPM message + * @param hpcd PCD handle + * @param msg LPM message * @retval HAL status */ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg) diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c index ec27001b..dffb78e2 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_pwr.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: @@ -168,7 +166,7 @@ void HAL_PWR_DisableBkUpAccess(void) forced in input pull-down configuration and is active on rising edges. (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00. (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13 - (++) For STM32F410xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01 + (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01 *** Low Power modes configuration *** ===================================== @@ -260,7 +258,7 @@ void HAL_PWR_DisableBkUpAccess(void) /** * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration + * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration * information for the PVD. * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage threshold corresponding to each @@ -326,11 +324,11 @@ void HAL_PWR_DisablePVD(void) /** * @brief Enables the Wake-up PINx functionality. - * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. + * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. * This parameter can be one of the following values: * @arg PWR_WAKEUP_PIN1 - * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices - * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx devices + * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices + * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices * @retval None */ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) @@ -344,11 +342,11 @@ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) /** * @brief Disables the Wake-up PINx functionality. - * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. + * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. * This parameter can be one of the following values: * @arg PWR_WAKEUP_PIN1 - * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices - * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices + * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices + * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices * @retval None */ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) @@ -368,13 +366,13 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) * @note In Sleep mode, the systick is stopped to avoid exit from this mode with * systick interrupt when used as time base for Timeout * - * @param Regulator: Specifies the regulator state in SLEEP mode. + * @param Regulator Specifies the regulator state in SLEEP mode. * This parameter can be one of the following values: * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON * @note This parameter is not used for the STM32F4 family and is kept as parameter * just to maintain compatibility with the lower power families. - * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction. + * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction @@ -413,11 +411,11 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) * startup delay is incurred when waking up from Stop mode. * By keeping the internal regulator ON during Stop mode, the consumption * is higher although the startup time is reduced. - * @param Regulator: Specifies the regulator state in Stop mode. + * @param Regulator Specifies the regulator state in Stop mode. * This parameter can be one of the following values: * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON - * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. + * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c index 113cea58..b6d48b9f 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_pwr_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of PWR extension peripheral: @@ -236,7 +234,7 @@ uint32_t HAL_PWREx_GetVoltageRange(void) #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) /** * @brief Configures the main internal regulator output voltage. - * @param VoltageScaling: specifies the regulator output voltage to achieve + * @param VoltageScaling specifies the regulator output voltage to achieve * a tradeoff between performance and power consumption. * This parameter can be one of the following values: * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, @@ -281,7 +279,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /** * @brief Configures the main internal regulator output voltage. - * @param VoltageScaling: specifies the regulator output voltage to achieve + * @param VoltageScaling specifies the regulator output voltage to achieve * a tradeoff between performance and power consumption. * This parameter can be one of the following values: * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, @@ -561,13 +559,13 @@ HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void) * By keeping the internal regulator ON during Stop mode, the consumption * is higher although the startup time is reduced. * - * @param Regulator: specifies the regulator state in STOP mode. + * @param Regulator specifies the regulator state in STOP mode. * This parameter can be one of the following values: * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode * and Flash memory in power-down when the device is in Stop under-drive mode * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode * and Flash memory in power-down when the device is in Stop under-drive mode - * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c index b34b9543..1f833074 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c @@ -2,21 +2,19 @@ ****************************************************************************** * @file stm32f4xx_hal_rcc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief RCC HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: * + Initialization and de-initialization functions * + Peripheral Control functions - * - @verbatim + * + @verbatim ============================================================================== ##### RCC specific features ##### ============================================================================== - [..] - After reset the device is running from Internal High Speed oscillator - (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache and I-Cache are disabled, and all peripherals are off except internal SRAM, Flash and JTAG. (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; @@ -24,12 +22,12 @@ (+) The clock for all peripherals is switched off, except the SRAM and FLASH. (+) All GPIOs are in input floating state, except the JTAG pins which are assigned to be used for debug purpose. - - [..] - Once the device started from reset, the user application has to: + + [..] + Once the device started from reset, the user application has to: (+) Configure the clock source to be used to drive the System clock (if the application needs higher frequency/performance) - (+) Configure the System clock frequency and Flash settings + (+) Configure the System clock frequency and Flash settings (+) Configure the AHB and APB busses prescalers (+) Enable the clock for the peripheral(s) to be used (+) Configure the clock source(s) for peripherals which clocks are not @@ -37,17 +35,17 @@ ##### RCC Limitations ##### ============================================================================== - [..] - A delay between an RCC peripheral clock enable and the effective peripheral - enabling should be taken into account in order to manage the peripheral read/write + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write from/to registers. (+) This delay depends on the peripheral mapping. - (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle + (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle after the clock enable bit is set on the hardware register - (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle + (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle after the clock enable bit is set on the hardware register - [..] + [..] Implemented Workaround: (+) For AHB & APB peripherals, a dummy read to the peripheral register has been inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. @@ -81,7 +79,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" @@ -102,12 +100,11 @@ /** @addtogroup RCC_Private_Constants * @{ */ -#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ /* Private macro -------------------------------------------------------------*/ #define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() #define MCO1_GPIO_PORT GPIOA -#define MCO1_PIN GPIO_PIN_8 +#define MCO1_PIN GPIO_PIN_8 #define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() #define MCO2_GPIO_PORT GPIOC @@ -119,7 +116,7 @@ /* Private variables ---------------------------------------------------------*/ /** @defgroup RCC_Private_Variables RCC Private Variables * @{ - */ + */ /** * @} */ @@ -130,16 +127,16 @@ * @{ */ -/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to configure the internal/external oscillators - (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 + (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 and APB2). [..] Internal/external clock and PLL configuration @@ -152,7 +149,7 @@ (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or through the PLL as System clock source. Can be used also as RTC clock source. - (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. (#) PLL (clocked by HSI or HSE), featuring two different output clocks: (++) The first output is used to generate the high speed system clock (up to 168 MHz) @@ -160,10 +157,10 @@ the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() - and if a HSE clock failure occurs(HSE used directly or through PLL as System + and if a HSE clock failure occurs(HSE used directly or through PLL as System clock source), the System clocks automatically switched to HSI and an interrupt - is generated if enabled. The interrupt is linked to the Cortex-M4 NMI - (Non-Maskable Interrupt) exception vector. + is generated if enabled. The interrupt is linked to the Cortex-M4 NMI + (Non-Maskable Interrupt) exception vector. (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL clock (through a configurable prescaler) on PA8 pin. @@ -171,36 +168,36 @@ (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S clock (through a configurable prescaler) on PC9 pin. - [..] System, AHB and APB busses clocks configuration + [..] System, AHB and APB busses clocks configuration (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable - prescaler and used to clock the CPU, memory and peripherals mapped - on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived - from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these busses. You can use - "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these busses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum - frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. + frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum frequency should be adapted accordingly (refer to the product datasheets for more details). (#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices, - the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz. + the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz. Depending on the device voltage range, the maximum frequency should be adapted accordingly (refer to the product datasheets for more details). - + (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz, - PCLK2 84 MHz and PCLK1 42 MHz. + PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum frequency should be adapted accordingly (refer to the product datasheets for more details). - + (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz, - PCLK2 100 MHz and PCLK1 50 MHz. + PCLK2 100 MHz and PCLK1 50 MHz. Depending on the device voltage range, the maximum frequency should be adapted accordingly (refer to the product datasheets for more details). - + @endverbatim * @{ */ @@ -214,17 +211,19 @@ * - CSS, MCO1 and MCO2 OFF * - All interrupts disabled * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @retval None + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL status */ -__weak void HAL_RCC_DeInit(void) -{} +__weak HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + return HAL_OK; +} /** * @brief Initializes the RCC Oscillators according to the specified parameters in the * RCC_OscInitTypeDef. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC Oscillators. * @note The PLL is not disabled when used as system clock. * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not @@ -237,11 +236,17 @@ __weak void HAL_RCC_DeInit(void) */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - uint32_t tickstart = 0U; - + uint32_t tickstart; + + /* Check Null pointer */ + if(RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - /*------------------------------- HSE Configuration ------------------------*/ + /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) { /* Check the parameters */ @@ -259,25 +264,25 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - + /* Check the HSE State */ if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) { - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till HSE is ready */ + + /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } else { - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till HSE is bypassed or disabled */ @@ -286,7 +291,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } } @@ -297,7 +302,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) @@ -325,16 +330,16 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Get Start Tick*/ tickstart = HAL_GetTick(); - /* Wait till HSI is ready */ + /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } - } - - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); } else @@ -344,15 +349,15 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ + + /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } - } + } + } } } } @@ -367,58 +372,68 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); - - /* Get Start Tick*/ + + /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ + + /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } - } + } + } } } - /*------------------------------ LSE Configuration -------------------------*/ + /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) { + FlagStatus pwrclkchanged = RESET; + /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - PWR->CR |= PWR_CR_DBP; - - /* Wait for Backup domain Write protection enable */ - tickstart = HAL_GetTick(); - - while((PWR->CR & PWR_CR_DBP) == RESET) + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) { - if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) { - return HAL_TIMEOUT; - } + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } } /* Set the new LSE configuration -----------------------------------------*/ @@ -428,30 +443,36 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc { /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } else { - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } + + /* Restore clock configuration if changed */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ @@ -460,7 +481,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) - { + { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) { /* Check the parameters */ @@ -469,52 +490,52 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); - + /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick*/ + + /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ + + /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } - } + } /* Configure the main PLL clock source, multiplication and division factors. */ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ RCC_OscInitStruct->PLL.PLLM | \ - (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ - (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \ - (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ)))); + (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ + (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ + (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); - /* Get Start Tick*/ + /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ + + /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick*/ + + /* Get Start Tick */ tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ + + /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) @@ -531,27 +552,27 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc } return HAL_OK; } - + /** - * @brief Initializes the CPU, AHB and APB busses clocks according to the specified + * @brief Initializes the CPU, AHB and APB busses clocks according to the specified * parameters in the RCC_ClkInitStruct. - * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that + * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC peripheral. - * @param FLatency: FLASH Latency, this parameter depend on device selected - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * @param FLatency FLASH Latency, this parameter depend on device selected + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated by HAL_RCC_GetHCLKFreq() function called within this function * * @note The HSI is used (enabled by hardware) as system clock source after * startup from Reset, wake-up from STOP and STANDBY mode, or in case * of failure of the HSE used directly or indirectly as system clock * (if the Clock Security System CSS is enabled). - * + * * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). + * clock source is ready (clock stable after startup delay or PLL locked). * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. - * + * occur when the clock source will be ready. + * * @note Depending on the device voltage range, the software has to set correctly * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") @@ -559,56 +580,74 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { - uint32_t tickstart = 0U; - + uint32_t tickstart; + + /* Check Null pointer */ + if(RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); assert_param(IS_FLASH_LATENCY(FLatency)); - - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ - + /* Increasing the number of wait states because of higher CPU frequency */ - if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) - { + if(FLatency > __HAL_FLASH_GET_LATENCY()) + { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - + /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + if(__HAL_FLASH_GET_LATENCY() != FLatency) { return HAL_ERROR; } } - + /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + } + + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + } + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); } - - /*------------------------- SYSCLK Configuration ---------------------------*/ + + /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { + { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - + /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { - /* Check the HSE ready flag */ + /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { return HAL_ERROR; } } /* PLL is selected as System Clock Source */ - else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || + else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) { - /* Check the PLL ready flag */ + /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { return HAL_ERROR; @@ -617,81 +656,49 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /* HSI is selected as System Clock Source */ else { - /* Check the HSI ready flag */ + /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { return HAL_ERROR; } } - + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - /* Get Start Tick*/ + + /* Get Start Tick */ tickstart = HAL_GetTick(); - - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLRCLK) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - + } + /* Decreasing the number of wait states because of lower CPU frequency */ - if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) - { + if(FLatency < __HAL_FLASH_GET_LATENCY()) + { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - + /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + if(__HAL_FLASH_GET_LATENCY() != FLatency) { return HAL_ERROR; } - } + } - /*-------------------------- PCLK1 Configuration ---------------------------*/ + /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); } - - /*-------------------------- PCLK2 Configuration ---------------------------*/ + + /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); @@ -699,11 +706,11 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)]; + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; - /* Configure the source of time base considering new system clocks settings*/ + /* Configure the source of time base considering new system clocks settings */ HAL_InitTick (TICK_INT_PRIORITY); - + return HAL_OK; } @@ -711,17 +718,17 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui * @} */ -/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions - * @brief RCC clocks control functions +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to control the RCC Clocks + This subsection provides a set of functions allowing to control the RCC Clocks frequencies. - + @endverbatim * @{ */ @@ -729,22 +736,22 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /** * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). * @note PA8/PC9 should be configured in alternate function mode. - * @param RCC_MCOx: specifies the output direction for the clock source. + * @param RCC_MCOx specifies the output direction for the clock source. * This parameter can be one of the following values: * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8). * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9). - * @param RCC_MCOSource: specifies the clock source to output. + * @param RCC_MCOSource specifies the clock source to output. * This parameter can be one of the following values: * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source - * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx - * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices + * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx + * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source - * @param RCC_MCODiv: specifies the MCOx prescaler. + * @param RCC_MCODiv specifies the MCOx prescaler. * This parameter can be one of the following values: * @arg RCC_MCODIV_1: no division applied to MCOx clock * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock @@ -765,34 +772,34 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M if(RCC_MCOx == RCC_MCO1) { assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); - + /* MCO1 Clock Enable */ __MCO1_CLK_ENABLE(); - - /* Configure the MCO1 pin in alternate function mode */ + + /* Configure the MCO1 pin in alternate function mode */ GPIO_InitStruct.Pin = MCO1_PIN; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Alternate = GPIO_AF0_MCO; HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); - + /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); - + /* This RCC MCO1 enable feature is available only on STM32F410xx devices */ #if defined(RCC_CFGR_MCO1EN) __HAL_RCC_MCO1_ENABLE(); -#endif /* RCC_CFGR_MCO1EN */ +#endif /* RCC_CFGR_MCO1EN */ } #if defined(RCC_CFGR_MCO2) else { assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); - + /* MCO2 Clock Enable */ __MCO2_CLK_ENABLE(); - + /* Configure the MCO2 pin in alternate function mode */ GPIO_InitStruct.Pin = MCO2_PIN; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -800,7 +807,7 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Alternate = GPIO_AF0_MCO; HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); - + /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */ MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U))); @@ -817,8 +824,8 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M * @note If a failure is detected on the HSE oscillator clock, this oscillator * is automatically disabled and an interrupt is generated to inform the * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. * @retval None */ void HAL_RCC_EnableCSS(void) @@ -837,14 +844,14 @@ void HAL_RCC_DisableCSS(void) /** * @brief Returns the SYSCLK frequency - * - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value * 16 MHz) but the real value may vary depending on the variations * in voltage and temperature. @@ -852,17 +859,17 @@ void HAL_RCC_DisableCSS(void) * 25 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. - * + * * @note The result of this function could be not correct when using fractional * value for HSE crystal. - * - * @note This function can be used by the user application to compute the + * + * @note This function can be used by the user application to compute the * baudrate for the communication peripherals or configure other parameters. - * + * * @note Each time SYSCLK changes, this function must be called to update the * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * + * + * * @retval SYSCLK frequency */ __weak uint32_t HAL_RCC_GetSysClockFreq(void) @@ -891,15 +898,15 @@ __weak uint32_t HAL_RCC_GetSysClockFreq(void) if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) { /* HSE used as PLL clock source */ - pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); + pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); } else { /* HSI used as PLL clock source */ - pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); + pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); } - pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1U) *2U); - + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U); + sysclockfreq = pllvco/pllp; break; } @@ -913,11 +920,11 @@ __weak uint32_t HAL_RCC_GetSysClockFreq(void) } /** - * @brief Returns the HCLK frequency + * @brief Returns the HCLK frequency * @note Each time HCLK changes, this function must be called to update the * right HCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ @@ -927,19 +934,19 @@ uint32_t HAL_RCC_GetHCLKFreq(void) } /** - * @brief Returns the PCLK1 frequency + * @brief Returns the PCLK1 frequency * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) -{ +{ /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]); + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]); } /** - * @brief Returns the PCLK2 frequency + * @brief Returns the PCLK2 frequency * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency @@ -947,13 +954,13 @@ uint32_t HAL_RCC_GetPCLK1Freq(void) uint32_t HAL_RCC_GetPCLK2Freq(void) { /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]); -} + return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]); +} /** - * @brief Configures the RCC_OscInitStruct according to the internal + * @brief Configures the RCC_OscInitStruct according to the internal * RCC configuration registers. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * will be configured. * @retval None */ @@ -961,7 +968,7 @@ __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Set all possible values for the Oscillator type parameter ---------------*/ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; - + /* Get the HSE configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) { @@ -975,7 +982,7 @@ __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->HSEState = RCC_HSE_OFF; } - + /* Get the HSI configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) { @@ -985,9 +992,9 @@ __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->HSIState = RCC_HSI_OFF; } - - RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM)); - + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); + /* Get the LSE configuration -----------------------------------------------*/ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) { @@ -1001,7 +1008,7 @@ __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->LSEState = RCC_LSE_OFF; } - + /* Get the LSI configuration -----------------------------------------------*/ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) { @@ -1011,7 +1018,7 @@ __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->LSIState = RCC_LSI_OFF; } - + /* Get the PLL configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) { @@ -1023,38 +1030,38 @@ __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); - RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)); - RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> POSITION_VAL(RCC_PLLCFGR_PLLP)); - RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)); + RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos); + RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos); } /** - * @brief Configures the RCC_ClkInitStruct according to the internal + * @brief Configures the RCC_ClkInitStruct according to the internal * RCC configuration registers. - * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that + * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that * will be configured. - * @param pFLatency: Pointer on the Flash Latency. + * @param pFLatency Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - - /* Get the SYSCLK configuration --------------------------------------------*/ + + /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); - - /* Get the HCLK configuration ----------------------------------------------*/ - RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); - - /* Get the APB1 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); - - /* Get the APB2 configuration ----------------------------------------------*/ + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); - - /* Get the Flash Wait State (Latency) configuration ------------------------*/ - *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); } /** @@ -1083,7 +1090,7 @@ __weak void HAL_RCC_CSSCallback(void) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_RCC_CSSCallback could be implemented in the user file - */ + */ } /** diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c index d347be95..ab11566b 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c @@ -2,13 +2,11 @@ ****************************************************************************** * @file stm32f4xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Extension RCC HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: * + Extended Peripheral Control functions - * + * ****************************************************************************** * @attention * @@ -37,7 +35,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" @@ -60,7 +58,7 @@ */ /** * @} - */ + */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -69,37 +67,37 @@ * @{ */ -/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Extended Peripheral Control functions ##### =============================================================================== [..] - This subsection provides a set of functions allowing to control the RCC Clocks + This subsection provides a set of functions allowing to control the RCC Clocks frequencies. - [..] + [..] (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to - select the RTC clock source; in this case the Backup domain will be reset in - order to modify the RTC Clock source, as consequence RTC registers (including + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including the backup registers) and RCC_BDCR register are set to their reset values. - + @endverbatim * @{ */ -#if defined(STM32F446xx) +#if defined(STM32F446xx) /** * @brief Initializes the RCC extended peripherals clocks according to the specified * parameters in the RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals * clocks(I2S, SAI, LTDC RTC and TIM). - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including * the backup registers) and RCC_BDCR register are set to their reset values. * * @retval HAL status @@ -115,100 +113,100 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk uint32_t pllsaiq = 0U; uint32_t plli2sused = 0U; uint32_t pllsaiused = 0U; - + /* Check the peripheral clock selection parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - + /*------------------------ I2S APB1 configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) { /* Check the parameters */ assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection)); - + /* Configure I2S Clock source */ __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection); /* Enable the PLLI2S when it's used as clock source for I2S */ if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S) { - plli2sused = 1U; + plli2sused = 1U; } } /*--------------------------------------------------------------------------*/ - + /*---------------------------- I2S APB2 configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) { /* Check the parameters */ assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection)); - + /* Configure I2S Clock source */ __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection); /* Enable the PLLI2S when it's used as clock source for I2S */ if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S) { - plli2sused = 1U; + plli2sused = 1U; } } /*--------------------------------------------------------------------------*/ - + /*--------------------------- SAI1 configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) { /* Check the parameters */ assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); - + /* Configure SAI1 Clock source */ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) { - plli2sused = 1U; + plli2sused = 1U; } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) { - pllsaiused = 1U; + pllsaiused = 1U; } } /*--------------------------------------------------------------------------*/ - + /*-------------------------- SAI2 configuration ----------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) { /* Check the parameters */ assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); - + /* Configure SAI2 Clock source */ __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); - + /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) { - plli2sused = 1U; + plli2sused = 1U; } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) { - pllsaiused = 1U; + pllsaiused = 1U; } } /*--------------------------------------------------------------------------*/ - + /*----------------------------- RTC configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - + /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; - + /* Get tick */ tickstart = HAL_GetTick(); - + while((PWR->CR & PWR_CR_DBP) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) @@ -216,7 +214,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk return HAL_TIMEOUT; } } - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) { @@ -233,8 +231,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Get tick */ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -247,7 +245,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); } /*--------------------------------------------------------------------------*/ - + /*---------------------------- TIM configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) { @@ -255,80 +253,80 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); } /*--------------------------------------------------------------------------*/ - + /*---------------------------- FMPI2C1 Configuration -----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) { /* Check the parameters */ assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); - + /* Configure the FMPI2C1 clock source */ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); } /*--------------------------------------------------------------------------*/ - + /*------------------------------ CEC Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); - + /* Configure the CEC clock source */ __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); } /*--------------------------------------------------------------------------*/ - + /*----------------------------- CLK48 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) { /* Check the parameters */ assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); - + /* Configure the CLK48 clock source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); /* Enable the PLLSAI when it's used as clock source for CLK48 */ if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP) { - pllsaiused = 1U; + pllsaiused = 1U; } } /*--------------------------------------------------------------------------*/ - + /*----------------------------- SDIO Configuration -------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) { /* Check the parameters */ assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); - + /* Configure the SDIO clock source */ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); } /*--------------------------------------------------------------------------*/ - + /*------------------------------ SPDIFRX Configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) { /* Check the parameters */ assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection)); - + /* Configure the SPDIFRX clock source */ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection); /* Enable the PLLI2S when it's used as clock source for SPDIFRX */ if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP) { - plli2sused = 1U; + plli2sused = 1U; } } /*--------------------------------------------------------------------------*/ - + /*---------------------------- PLLI2S Configuration ------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1, I2S on APB2 or SPDIFRX */ if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) { /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); + __HAL_RCC_PLLI2S_DISABLE(); /* Get tick */ tickstart = HAL_GetTick(); /* Wait till PLLI2S is disabled */ @@ -338,66 +336,66 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* return in case of Timeout detected */ return HAL_TIMEOUT; - } + } } - + /* check for common PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); - - /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/ + + /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S))) { /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - + /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ - plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U); - plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); + plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); + plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR); } - - /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ + + /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || - ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) { /* Check for PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); /* Check for PLLI2S/DIVQ parameters */ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); - + /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */ - plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U); - plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); - /* Configure the PLLI2S division factors */ + plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); + plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); - } - /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/ + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)) { /* check for Parameters */ assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ - plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U); - plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); + plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); + plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr); - } - - /*----------------- In Case of PLLI2S is just selected -----------------*/ + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) { /* Check for Parameters */ @@ -408,8 +406,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); - } - + } + /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); /* Get tick */ @@ -423,32 +421,32 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk return HAL_TIMEOUT; } } - } + } /*--------------------------------------------------------------------------*/ - + /*----------------------------- PLLSAI Configuration -----------------------*/ /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */ if(pllsaiused == 1U) { /* Disable PLLSAI Clock */ - __HAL_RCC_PLLSAI_DISABLE(); + __HAL_RCC_PLLSAI_DISABLE(); /* Get tick */ tickstart = HAL_GetTick(); /* Wait till PLLSAI is disabled */ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) { if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) - { + { /* return in case of Timeout detected */ return HAL_TIMEOUT; } } - + /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM)); assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); - - /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/ + + /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) || ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) { @@ -456,31 +454,31 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); /* check for PLLSAI/DIVQ Parameter */ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); - + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ - pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U); + pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0U); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ - __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); - } - /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/ - /* In Case of PLLI2S is selected as source clock for CLK48 */ + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + } + + /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/ + /* In Case of PLLI2S is selected as source clock for CLK48 */ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)) { /* check for Parameters */ assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */ - pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); + pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); /* Configure the PLLSAI division factors */ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */ /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0U); - } + } /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); @@ -490,11 +488,11 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) { if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) - { + { /* return in case of Timeout detected */ return HAL_TIMEOUT; } - } + } } return HAL_OK; } @@ -502,14 +500,14 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /** * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal * RCC configuration registers. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * will be configured. * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tempreg; - + /* Set all possible values for the extended clock type parameter------------*/ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\ RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ @@ -517,53 +515,53 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMPI2C1 |\ RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDIO |\ RCC_PERIPHCLK_SPDIFRX; - + /* Get the PLLI2S Clock configuration --------------------------------------*/ - PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SM)); - PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); - PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U); - PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); - PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); + PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos); + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); /* Get the PLLSAI Clock configuration --------------------------------------*/ - PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIM)); - PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)); - PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U); - PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); + PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> RCC_PLLSAICFGR_PLLSAIM_Pos); + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); + PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/ - PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ)); - PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ)); + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos); /* Get the SAI1 clock configuration ----------------------------------------*/ PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); - + /* Get the SAI2 clock configuration ----------------------------------------*/ PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); - + /* Get the I2S APB1 clock configuration ------------------------------------*/ PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE(); - + /* Get the I2S APB2 clock configuration ------------------------------------*/ PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE(); - + /* Get the RTC Clock configuration -----------------------------------------*/ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); - + /* Get the CEC clock configuration -----------------------------------------*/ PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); - + /* Get the FMPI2C1 clock configuration -------------------------------------*/ PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE(); - + /* Get the CLK48 clock configuration ----------------------------------------*/ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); - + /* Get the SDIO clock configuration ----------------------------------------*/ PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE(); - + /* Get the SPDIFRX clock configuration -------------------------------------*/ PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE(); - + /* Get the TIM Prescaler configuration -------------------------------------*/ if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) { @@ -576,9 +574,9 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) } /** - * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk: Peripheral clock identifier + * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock @@ -601,16 +599,16 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) switch (PeriphClk) { case RCC_PERIPHCLK_SAI1: - case RCC_PERIPHCLK_SAI2: + case RCC_PERIPHCLK_SAI2: { - saiclocksource = RCC->DCKCFGR; + saiclocksource = RCC->DCKCFGR; saiclocksource &= (RCC_DCKCFGR_SAI1SRC | RCC_DCKCFGR_SAI2SRC); switch (saiclocksource) { - case 0U: /* PLLSAI is the clock source for SAI*/ + case 0U: /* PLLSAI is the clock source for SAI*/ { /* Configure the PLLSAI division factor */ - /* PLLSAI_VCO Input = PLL_SOURCE/PLLSAIM */ + /* PLLSAI_VCO Input = PLL_SOURCE/PLLSAIM */ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) { /* In Case the PLL Source is HSI (Internal Clock) */ @@ -620,22 +618,22 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { /* In Case the PLL Source is HSE (External Clock) */ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM))); - } + } /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U; frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U))/(tmpreg1); - + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U); - frequency = frequency/(tmpreg1); - break; + frequency = frequency/(tmpreg1); + break; } case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/ case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/ - { + { /* Configure the PLLI2S division factor */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) { /* In Case the PLL Source is HSI (Internal Clock) */ @@ -646,22 +644,22 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* In Case the PLL Source is HSE (External Clock) */ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM))); } - + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U; frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U))/(tmpreg1); - + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U); + tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U); frequency = frequency/(tmpreg1); - break; + break; } case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/ case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/ { /* Configure the PLLI2S division factor */ - /* PLL_VCO Input = PLL_SOURCE/PLLM */ + /* PLL_VCO Input = PLL_SOURCE/PLLM */ if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) { /* In Case the PLL Source is HSI (Internal Clock) */ @@ -672,17 +670,17 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* In Case the PLL Source is HSE (External Clock) */ vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); } - + /* PLL_VCO Output = PLL_VCO Input * PLLN */ /* SAI_CLK_x = PLL_VCO Output/PLLR */ tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U; frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U))/(tmpreg1); - break; + break; } case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/ { frequency = EXTERNAL_CLOCK_VALUE; - break; + break; } case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/ { @@ -696,12 +694,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* In Case the PLL Source is HSE (External Clock) */ frequency = (uint32_t)(HSE_VALUE); } - break; - } + break; + } default : { break; - } + } } break; } @@ -711,8 +709,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE(); switch (srcclk) { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ - case RCC_I2SAPB1CLKSOURCE_EXT: + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPB1CLKSOURCE_EXT: { /* Set the I2S clock to the external clock value */ frequency = EXTERNAL_CLOCK_VALUE; @@ -733,7 +731,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); } - + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ @@ -755,7 +753,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); } - + /* PLL_VCO Output = PLL_VCO Input * PLLN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); /* I2S_CLK = PLL_VCO Output/PLLR */ @@ -782,15 +780,15 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) break; } } - break; - } + break; + } case RCC_PERIPHCLK_I2S_APB2: { /* Get the current I2S source */ srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE(); switch (srcclk) { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ case RCC_I2SAPB2CLKSOURCE_EXT: { /* Set the I2S clock to the external clock value */ @@ -812,7 +810,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); } - + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ @@ -834,7 +832,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); } - + /* PLL_VCO Output = PLL_VCO Input * PLLN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); /* I2S_CLK = PLL_VCO Output/PLLR */ @@ -859,12 +857,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = 0U; break; - } + } } break; } } - return frequency; + return frequency; } #endif /* STM32F446xx */ @@ -872,13 +870,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /** * @brief Initializes the RCC extended peripherals clocks according to the specified * parameters in the RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals * clocks(I2S, SAI, LTDC, RTC and TIM). - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including * the backup registers) and RCC_BDCR register are set to their reset values. * * @retval HAL status @@ -890,45 +888,45 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk uint32_t pllsaip = 0U; uint32_t pllsaiq = 0U; uint32_t pllsair = 0U; - + /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - + /*--------------------------- CLK48 Configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) { /* Check the parameters */ assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); - + /* Configure the CLK48 clock source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); - } + } /*--------------------------------------------------------------------------*/ - + /*------------------------------ SDIO Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) { /* Check the parameters */ assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); - + /* Configure the SDIO clock source */ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); } /*--------------------------------------------------------------------------*/ - + /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/ /*------------------- Common configuration SAI/I2S -------------------------*/ - /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division - factor is common parameters for both peripherals */ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || + /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division + factor is common parameters for both peripherals */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) { /* check for Parameters */ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); - + /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); + __HAL_RCC_PLLI2S_DISABLE(); /* Get tick */ tickstart = HAL_GetTick(); /* Wait till PLLI2S is disabled */ @@ -940,10 +938,10 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk return HAL_TIMEOUT; } } - + /*---------------------- I2S configuration -------------------------------*/ - /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added - only for I2S configuration */ + /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added + only for I2S configuration */ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) { /* check for Parameters */ @@ -953,38 +951,38 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); } - - /*---------------------------- SAI configuration -------------------------*/ - /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must - be added only for SAI configuration */ + + /*---------------------------- SAI configuration -------------------------*/ + /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must + be added only for SAI configuration */ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S)) { /* Check the PLLI2S division factors */ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); - + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ - tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); - /* Configure the PLLI2S division factors */ + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1); - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); } - - /*----------------- In Case of PLLI2S is just selected -----------------*/ + + /*----------------- In Case of PLLI2S is just selected -----------------*/ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) { /* Check for Parameters */ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - + /* Configure the PLLI2S multiplication and division factors */ __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); - } - + } + /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); /* Get tick */ @@ -1000,53 +998,53 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } /*--------------------------------------------------------------------------*/ - + /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/ /*----------------------- Common configuration SAI/LTDC --------------------*/ /* In Case of SAI, LTDC or CLK48 Clock Configuration through PLLSAI, PLLSAIN division - factor is common parameters for these peripherals */ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || - (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || + factor is common parameters for these peripherals */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))) { /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); - + /* Disable PLLSAI Clock */ - __HAL_RCC_PLLSAI_DISABLE(); + __HAL_RCC_PLLSAI_DISABLE(); /* Get tick */ tickstart = HAL_GetTick(); /* Wait till PLLSAI is disabled */ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) { if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) - { + { /* return in case of Timeout detected */ return HAL_TIMEOUT; } } - + /*---------------------------- SAI configuration -------------------------*/ - /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must - be added only for SAI configuration */ + /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must + be added only for SAI configuration */ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI)) { assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); - + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ - pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U); + pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ - pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); + pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ - __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair); - /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair); + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); } - + /*---------------------------- LTDC configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) { @@ -1054,34 +1052,34 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ - pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U); + pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U); /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */ - pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); + pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, pllsaiq, PeriphClkInit->PLLSAI.PLLSAIR); - /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ + /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); - } - + } + /*---------------------------- CLK48 configuration ------------------------*/ /* Configure the PLLSAI when it is used as clock source for CLK48 */ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == (RCC_PERIPHCLK_CLK48)) && + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == (RCC_PERIPHCLK_CLK48)) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)) { assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); - + /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */ - pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); + pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ - pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); + pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* CLK48_CLK(first level) = PLLSAI_VCO Output/PLLSAIP */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair); } - + /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); /* Get tick */ @@ -1090,30 +1088,30 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) { if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) - { + { /* return in case of Timeout detected */ return HAL_TIMEOUT; } - } + } } /*--------------------------------------------------------------------------*/ - + /*---------------------------- RTC configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - + /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; - + /* Get tick */ tickstart = HAL_GetTick(); - + while((PWR->CR & PWR_CR_DBP) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) @@ -1121,7 +1119,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk return HAL_TIMEOUT; } } - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) { @@ -1132,14 +1130,14 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_BACKUPRESET_RELEASE(); /* Restore the Content of BDCR register */ RCC->BDCR = tmpreg1; - + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) { /* Get tick */ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -1162,44 +1160,44 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /** - * @brief Configures the RCC_PeriphCLKInitTypeDef according to the internal + * @brief Configures the RCC_PeriphCLKInitTypeDef according to the internal * RCC configuration registers. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * will be configured. * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tempreg; - + /* Set all possible values for the extended clock type parameter------------*/ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI |\ RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC |\ RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDIO; - + /* Get the PLLI2S Clock configuration --------------------------------------*/ - PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); - PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); - PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); /* Get the PLLSAI Clock configuration --------------------------------------*/ - PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)); - PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); - PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); + PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/ - PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ)); - PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ)); + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos); PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR); /* Get the RTC Clock configuration -----------------------------------------*/ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); - + /* Get the CLK48 clock configuration -------------------------------------*/ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); - + /* Get the SDIO clock configuration ----------------------------------------*/ PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE(); - + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) { PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; @@ -1211,9 +1209,9 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) } /** - * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk: Peripheral clock identifier + * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock * @retval Frequency in KHz @@ -1235,8 +1233,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) srcclk = __HAL_RCC_GET_I2S_SOURCE(); switch (srcclk) { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ - case RCC_I2SCLKSOURCE_EXT: + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SCLKSOURCE_EXT: { /* Set the I2S clock to the external clock value */ frequency = EXTERNAL_CLOCK_VALUE; @@ -1257,7 +1255,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); } - + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ @@ -1269,7 +1267,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = 0U; break; - } + } } break; } @@ -1282,13 +1280,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /** * @brief Initializes the RCC extended peripherals clocks according to the specified * parameters in the RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals * clocks(I2S, LTDC RTC and TIM). - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including * the backup registers) and RCC_BDCR register are set to their reset values. * * @retval HAL status @@ -1304,106 +1302,106 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Check the peripheral clock selection parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - + /*----------------------------------- I2S APB1 configuration ---------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1)) { /* Check the parameters */ assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection)); - + /* Configure I2S Clock source */ __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection); /* Enable the PLLI2S when it's used as clock source for I2S */ if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S) { - plli2sused = 1U; + plli2sused = 1U; } } /*--------------------------------------------------------------------------*/ - + /*----------------------------------- I2S APB2 configuration ---------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2)) { /* Check the parameters */ assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection)); - + /* Configure I2S Clock source */ __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection); /* Enable the PLLI2S when it's used as clock source for I2S */ if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S) { - plli2sused = 1U; + plli2sused = 1U; } } /*--------------------------------------------------------------------------*/ - + #if defined(STM32F413xx) || defined(STM32F423xx) /*----------------------- SAI1 Block A configuration -----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == (RCC_PERIPHCLK_SAIA)) { /* Check the parameters */ assert_param(IS_RCC_SAIACLKSOURCE(PeriphClkInit->SaiAClockSelection)); - + /* Configure SAI1 Clock source */ __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(PeriphClkInit->SaiAClockSelection); /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR) { - plli2sused = 1U; + plli2sused = 1U; } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLR) { /* Check for PLL/DIVR parameters */ assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR)); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */ + + /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */ __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR); } } /*--------------------------------------------------------------------------*/ - + /*---------------------- SAI1 Block B configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == (RCC_PERIPHCLK_SAIB)) { /* Check the parameters */ assert_param(IS_RCC_SAIBCLKSOURCE(PeriphClkInit->SaiBClockSelection)); - + /* Configure SAI1 Clock source */ __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(PeriphClkInit->SaiBClockSelection); /* Enable the PLLI2S when it's used as clock source for SAI */ if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR) { - plli2sused = 1U; + plli2sused = 1U; } /* Enable the PLLSAI when it's used as clock source for SAI */ if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLR) { /* Check for PLL/DIVR parameters */ assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR)); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */ + + /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */ __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR); } } /*--------------------------------------------------------------------------*/ #endif /* STM32F413xx || STM32F423xx */ - + /*------------------------------------ RTC configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - + /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; - + /* Get tick */ tickstart = HAL_GetTick(); - + while((PWR->CR & PWR_CR_DBP) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) @@ -1411,7 +1409,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk return HAL_TIMEOUT; } } - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) { @@ -1428,8 +1426,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Get tick */ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -1442,7 +1440,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); } /*--------------------------------------------------------------------------*/ - + /*------------------------------------ TIM configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) { @@ -1450,46 +1448,46 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); } /*--------------------------------------------------------------------------*/ - + /*------------------------------------- FMPI2C1 Configuration --------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) { /* Check the parameters */ assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); - + /* Configure the FMPI2C1 clock source */ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); } /*--------------------------------------------------------------------------*/ - + /*------------------------------------- CLK48 Configuration ----------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) { /* Check the parameters */ assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection)); - + /* Configure the SDIO clock source */ __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); /* Enable the PLLI2S when it's used as clock source for CLK48 */ if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ) { - plli2sused = 1U; + plli2sused = 1U; } } /*--------------------------------------------------------------------------*/ - + /*------------------------------------- SDIO Configuration -----------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) { /* Check the parameters */ assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection)); - + /* Configure the SDIO clock source */ __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection); } /*--------------------------------------------------------------------------*/ - + /*-------------------------------------- PLLI2S Configuration --------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : I2S on APB1 or I2S on APB2*/ @@ -1515,8 +1513,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); /*-------------------- Set the PLL I2S clock -----------------------------*/ __HAL_RCC_PLL_I2S_CONFIG(PeriphClkInit->PLLI2SSelection); - - /*------- In Case of PLLI2S is selected as source clock for I2S ----------*/ + + /*------- In Case of PLLI2S is selected as source clock for I2S ----------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) || ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)) || ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)) || @@ -1531,28 +1529,28 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); } - + #if defined(STM32F413xx) || defined(STM32F423xx) - /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ + /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/ if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == RCC_PERIPHCLK_SAIA) && (PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)) || - ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == RCC_PERIPHCLK_SAIB) && (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR))) + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == RCC_PERIPHCLK_SAIB) && (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR))) { /* Check for PLLI2S Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); /* Check for PLLI2S/DIVR parameters */ assert_param(IS_RCC_PLLI2S_DIVR_VALUE(PeriphClkInit->PLLI2SDivR)); - + /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for SAI configuration) */ - plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); - /* Configure the PLLI2S division factors */ + plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVR */ - __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLI2SDivR); - } + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVR */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLI2SDivR); + } #endif /* STM32F413xx || STM32F423xx */ /*----------------- In Case of PLLI2S is just selected ------------------*/ @@ -1605,8 +1603,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); } /*--------------------------------------------------------------------------*/ - -#if defined(STM32F413xx) || defined(STM32F423xx) + +#if defined(STM32F413xx) || defined(STM32F423xx) /*-------------------- DFSDM2 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2) { @@ -1628,13 +1626,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_DFSDM2AUDIO_CONFIG(PeriphClkInit->Dfsdm2AudioClockSelection); } /*--------------------------------------------------------------------------*/ - + /*---------------------------- LPTIM1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) { /* Check the parameters */ assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); - + /* Configure the LPTIM1 clock source */ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); } @@ -1647,14 +1645,14 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /** * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal * RCC configuration registers. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * will be configured. * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tempreg; - + /* Set all possible values for the extended clock type parameter------------*/ #if defined(STM32F413xx) || defined(STM32F423xx) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\ @@ -1671,26 +1669,26 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_DFSDM1 |\ RCC_PERIPHCLK_DFSDM1_AUDIO; #endif /* STM32F413xx || STM32F423xx */ - - + + /* Get the PLLI2S Clock configuration --------------------------------------*/ - PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SM)); - PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); - PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); - PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); + PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos); + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); #if defined(STM32F413xx) || defined(STM32F423xx) /* Get the PLL/PLLI2S division factors -------------------------------------*/ - PeriphClkInit->PLLI2SDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVR) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVR)); - PeriphClkInit->PLLDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> POSITION_VAL(RCC_DCKCFGR_PLLDIVR)); + PeriphClkInit->PLLI2SDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVR) >> RCC_DCKCFGR_PLLI2SDIVR_Pos); + PeriphClkInit->PLLDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> RCC_DCKCFGR_PLLDIVR_Pos); #endif /* STM32F413xx || STM32F423xx */ - + /* Get the I2S APB1 clock configuration ------------------------------------*/ PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE(); - + /* Get the I2S APB2 clock configuration ------------------------------------*/ PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE(); - + /* Get the RTC Clock configuration -----------------------------------------*/ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); @@ -1700,29 +1698,29 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Get the CLK48 clock configuration ---------------------------------------*/ PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); - + /* Get the SDIO clock configuration ----------------------------------------*/ PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE(); - + /* Get the DFSDM1 clock configuration --------------------------------------*/ PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); - + /* Get the DFSDM1 Audio clock configuration --------------------------------*/ PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); #if defined(STM32F413xx) || defined(STM32F423xx) /* Get the DFSDM2 clock configuration --------------------------------------*/ PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE(); - + /* Get the DFSDM2 Audio clock configuration --------------------------------*/ PeriphClkInit->Dfsdm2AudioClockSelection = __HAL_RCC_GET_DFSDM2AUDIO_SOURCE(); - + /* Get the LPTIM1 clock configuration --------------------------------------*/ PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); - + /* Get the SAI1 Block Aclock configuration ---------------------------------*/ PeriphClkInit->SaiAClockSelection = __HAL_RCC_GET_SAI_BLOCKA_SOURCE(); - + /* Get the SAI1 Block B clock configuration --------------------------------*/ PeriphClkInit->SaiBClockSelection = __HAL_RCC_GET_SAI_BLOCKB_SOURCE(); #endif /* STM32F413xx || STM32F423xx */ @@ -1739,9 +1737,9 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) } /** - * @brief Return the peripheral clock frequency for a given peripheral(I2S..) + * @brief Return the peripheral clock frequency for a given peripheral(I2S..) * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk: Peripheral clock identifier + * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: * @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock * @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock @@ -1764,8 +1762,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE(); switch (srcclk) { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ - case RCC_I2SAPB1CLKSOURCE_EXT: + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPB1CLKSOURCE_EXT: { /* Set the I2S clock to the external clock value */ frequency = EXTERNAL_CLOCK_VALUE; @@ -1792,7 +1790,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); - } + } } /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); @@ -1815,7 +1813,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); } - + /* PLL_VCO Output = PLL_VCO Input * PLLN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); /* I2S_CLK = PLL_VCO Output/PLLR */ @@ -1840,7 +1838,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = 0U; break; - } + } } break; } @@ -1850,8 +1848,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE(); switch (srcclk) { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ - case RCC_I2SAPB2CLKSOURCE_EXT: + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPB2CLKSOURCE_EXT: { /* Set the I2S clock to the external clock value */ frequency = EXTERNAL_CLOCK_VALUE; @@ -1878,7 +1876,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)); - } + } } /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); @@ -1901,7 +1899,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); } - + /* PLL_VCO Output = PLL_VCO Input * PLLN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); /* I2S_CLK = PLL_VCO Output/PLLR */ @@ -1926,12 +1924,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = 0U; break; - } + } } break; } } - return frequency; + return frequency; } #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ @@ -1939,38 +1937,38 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /** * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the * RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks). - * - * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case - * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup + * + * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case + * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset - * + * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tickstart = 0U; uint32_t tmpreg1 = 0U; - + /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - + /*---------------------------- RTC configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - + /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; - + /* Get tick */ tickstart = HAL_GetTick(); - + while((PWR->CR & PWR_CR_DBP) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) @@ -1978,7 +1976,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk return HAL_TIMEOUT; } } - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) { @@ -1995,8 +1993,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Get tick */ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -2016,24 +2014,24 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); } /*--------------------------------------------------------------------------*/ - + /*---------------------------- FMPI2C1 Configuration -----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1) { /* Check the parameters */ assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection)); - + /* Configure the FMPI2C1 clock source */ __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection); } /*--------------------------------------------------------------------------*/ - + /*---------------------------- LPTIM1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) { /* Check the parameters */ assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); - + /* Configure the LPTIM1 clock source */ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); } @@ -2043,7 +2041,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Check the parameters */ assert_param(IS_RCC_I2SAPBCLKSOURCE(PeriphClkInit->I2SClockSelection)); - + /* Configure the I2S clock source */ __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2SClockSelection); } @@ -2052,9 +2050,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /** - * @brief Configures the RCC_OscInitStruct according to the internal + * @brief Configures the RCC_OscInitStruct according to the internal * RCC configuration registers. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * will be configured. * @retval None */ @@ -2064,10 +2062,10 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Set all possible values for the extended clock type parameter------------*/ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC; - + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); - + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) { PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; @@ -2082,12 +2080,12 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) /* Get the I2S clock configuration -----------------------------------------*/ PeriphClkInit->I2SClockSelection = __HAL_RCC_GET_I2S_SOURCE(); - + } /** - * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk: Peripheral clock identifier + * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock * @retval Frequency in KHz @@ -2109,8 +2107,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) srcclk = __HAL_RCC_GET_I2S_SOURCE(); switch (srcclk) { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ - case RCC_I2SAPBCLKSOURCE_EXT: + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SAPBCLKSOURCE_EXT: { /* Set the I2S clock to the external clock value */ frequency = EXTERNAL_CLOCK_VALUE; @@ -2131,7 +2129,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); } - + /* PLL_VCO Output = PLL_VCO Input * PLLN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U))); /* I2S_CLK = PLL_VCO Output/PLLR */ @@ -2161,7 +2159,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) break; } } - return frequency; + return frequency; } #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ @@ -2169,13 +2167,13 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /** * @brief Initializes the RCC extended peripherals clocks according to the specified * parameters in the RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals * clocks(I2S, SAI, LTDC RTC and TIM). - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including * the backup registers) and RCC_BDCR register are set to their reset values. * * @retval HAL status @@ -2184,22 +2182,22 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { uint32_t tickstart = 0U; uint32_t tmpreg1 = 0U; - + /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - + /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/ /*----------------------- Common configuration SAI/I2S ---------------------*/ - /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division - factor is common parameters for both peripherals */ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || + /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division + factor is common parameters for both peripherals */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S)) { /* check for Parameters */ assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); - + /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); + __HAL_RCC_PLLI2S_DISABLE(); /* Get tick */ tickstart = HAL_GetTick(); /* Wait till PLLI2S is disabled */ @@ -2211,10 +2209,10 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk return HAL_TIMEOUT; } } - + /*---------------------------- I2S configuration -------------------------*/ - /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added - only for I2S configuration */ + /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added + only for I2S configuration */ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) { /* check for Parameters */ @@ -2224,27 +2222,27 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); } - - /*---------------------------- SAI configuration -------------------------*/ - /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must - be added only for SAI configuration */ + + /*---------------------------- SAI configuration -------------------------*/ + /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must + be added only for SAI configuration */ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S)) { /* Check the PLLI2S division factors */ assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); - + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */ - tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); - /* Configure the PLLI2S division factors */ + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1); - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); } - + /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); /* Get tick */ @@ -2260,64 +2258,64 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } /*--------------------------------------------------------------------------*/ - + /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/ /*----------------------- Common configuration SAI/LTDC --------------------*/ /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division - factor is common parameters for both peripherals */ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || + factor is common parameters for both peripherals */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)) { /* Check the PLLSAI division factors */ assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); - + /* Disable PLLSAI Clock */ - __HAL_RCC_PLLSAI_DISABLE(); + __HAL_RCC_PLLSAI_DISABLE(); /* Get tick */ tickstart = HAL_GetTick(); /* Wait till PLLSAI is disabled */ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) { if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) - { + { /* return in case of Timeout detected */ return HAL_TIMEOUT; } } - + /*---------------------------- SAI configuration -------------------------*/ - /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must - be added only for SAI configuration */ + /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must + be added only for SAI configuration */ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI)) { assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); - + /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ - tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); - /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); } - + /*---------------------------- LTDC configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) { assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); - + /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */ - tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR); - /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ + /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); - } + } /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); /* Get tick */ @@ -2326,29 +2324,29 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) { if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) - { + { /* return in case of Timeout detected */ return HAL_TIMEOUT; } - } + } } /*--------------------------------------------------------------------------*/ - + /*---------------------------- RTC configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - + /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; - + /* Get tick */ tickstart = HAL_GetTick(); - + while((PWR->CR & PWR_CR_DBP) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) @@ -2356,7 +2354,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk return HAL_TIMEOUT; } } - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) { @@ -2373,8 +2371,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Get tick */ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -2397,35 +2395,35 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /** - * @brief Configures the PeriphClkInit according to the internal + * @brief Configures the PeriphClkInit according to the internal * RCC configuration registers. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * will be configured. * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tempreg; - + /* Set all possible values for the extended clock type parameter------------*/ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC; - + /* Get the PLLI2S Clock configuration -----------------------------------------------*/ - PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); - PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); - PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)); + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); /* Get the PLLSAI Clock configuration -----------------------------------------------*/ - PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)); - PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)); - PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)); + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); + PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/ - PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ)); - PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ)); + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos); PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR); /* Get the RTC Clock configuration -----------------------------------------------*/ tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); - + if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET) { PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; @@ -2437,9 +2435,9 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) } /** - * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk: Peripheral clock identifier + * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock * @retval Frequency in KHz @@ -2461,8 +2459,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) srcclk = __HAL_RCC_GET_I2S_SOURCE(); switch (srcclk) { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ - case RCC_I2SCLKSOURCE_EXT: + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SCLKSOURCE_EXT: { /* Set the I2S clock to the external clock value */ frequency = EXTERNAL_CLOCK_VALUE; @@ -2483,7 +2481,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); } - + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ @@ -2495,12 +2493,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = 0U; break; - } + } } break; } } - return frequency; + return frequency; } #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ @@ -2509,23 +2507,23 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /** * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the * RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks). - * - * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case - * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup + * + * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case + * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset - * + * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tickstart = 0U; uint32_t tmpreg1 = 0U; - + /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - + /*---------------------------- I2S configuration ---------------------------*/ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) @@ -2533,7 +2531,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* check for Parameters */ assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); -#if defined(STM32F411xE) +#if defined(STM32F411xE) assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); #endif /* STM32F411xE */ /* Disable the PLLI2S */ @@ -2547,13 +2545,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* return in case of Timeout detected */ return HAL_TIMEOUT; - } + } } #if defined(STM32F411xE) /* Configure the PLLI2S division factors */ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ - /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR); #else /* Configure the PLLI2S division factors */ @@ -2561,7 +2559,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); #endif /* STM32F411xE */ - + /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); /* Get tick */ @@ -2576,22 +2574,22 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } } - + /*---------------------------- RTC configuration ---------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) { /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - + /* Enable Power Clock*/ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; - + /* Get tick */ tickstart = HAL_GetTick(); - + while((PWR->CR & PWR_CR_DBP) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) @@ -2599,7 +2597,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk return HAL_TIMEOUT; } } - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) { @@ -2616,8 +2614,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { /* Get tick */ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -2640,22 +2638,22 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /** - * @brief Configures the RCC_OscInitStruct according to the internal + * @brief Configures the RCC_OscInitStruct according to the internal * RCC configuration registers. - * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that * will be configured. * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { uint32_t tempreg; - + /* Set all possible values for the extended clock type parameter------------*/ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC; - + /* Get the PLLI2S Clock configuration --------------------------------------*/ - PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)); - PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)); + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); #if defined(STM32F411xE) PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM); #endif /* STM32F411xE */ @@ -2673,13 +2671,13 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; } -#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ } /** - * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk: Peripheral clock identifier + * @param PeriphClk Peripheral clock identifier * This parameter can be one of the following values: * @arg RCC_PERIPHCLK_I2S: I2S peripheral clock * @retval Frequency in KHz @@ -2701,8 +2699,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) srcclk = __HAL_RCC_GET_I2S_SOURCE(); switch (srcclk) { - /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ - case RCC_I2SCLKSOURCE_EXT: + /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */ + case RCC_I2SCLKSOURCE_EXT: { /* Set the I2S clock to the external clock value */ frequency = EXTERNAL_CLOCK_VALUE; @@ -2737,7 +2735,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Get the I2S source clock value */ vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); } -#endif /* STM32F411xE */ +#endif /* STM32F411xE */ /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U))); /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */ @@ -2749,12 +2747,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { frequency = 0U; break; - } + } } break; } } - return frequency; + return frequency; } #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */ @@ -2762,10 +2760,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /** * @brief Select LSE mode - * + * * @note This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices. - * - * @param Mode: specifies the LSE mode. + * + * @param Mode specifies the LSE mode. * This parameter can be one of the following values: * @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection * @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection @@ -2787,20 +2785,255 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode) #endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ +/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions + * @brief Extended Clock management functions + * +@verbatim + =============================================================================== + ##### Extended clock management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the + activation or deactivation of PLLI2S, PLLSAI. +@endverbatim + * @{ + */ + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Enable PLLI2S. + * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that + * contains the configuration information for the PLLI2S + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) +{ + uint32_t tickstart; + + /* Check for parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN)); + assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR)); +#if defined(RCC_PLLI2SCFGR_PLLI2SM) + assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SInit->PLLI2SM)); +#endif /* RCC_PLLI2SCFGR_PLLI2SM */ +#if defined(RCC_PLLI2SCFGR_PLLI2SP) + assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP)); +#endif /* RCC_PLLI2SCFGR_PLLI2SP */ +#if defined(RCC_PLLI2SCFGR_PLLI2SQ) + assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ)); +#endif /* RCC_PLLI2SCFGR_PLLI2SQ */ + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Wait till PLLI2S is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Configure the PLLI2S division factors */ +#if defined(STM32F446xx) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + /* I2SPCLK = PLLI2S_VCO / PLLI2SP */ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \ + PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F413xx) || defined(STM32F423xx) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \ + PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_SAICLK_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#elif defined(STM32F411xE) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR); +#else + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x PLLI2SN */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR); +#endif /* STM32F446xx */ + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Wait till PLLI2S is ready */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLLI2S. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) +{ + uint32_t tickstart; + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Wait till PLLI2S is disabled */ + tickstart = HAL_GetTick(); + while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) +/** + * @brief Enable PLLSAI. + * @param PLLSAIInit pointer to an RCC_PLLSAIInitTypeDef structure that + * contains the configuration information for the PLLSAI + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit) +{ + uint32_t tickstart; + + /* Check for parameters */ + assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN)); + assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ)); +#if defined(RCC_PLLSAICFGR_PLLSAIM) + assert_param(IS_RCC_PLLSAIM_VALUE(PLLSAIInit->PLLSAIM)); +#endif /* RCC_PLLSAICFGR_PLLSAIM */ +#if defined(RCC_PLLSAICFGR_PLLSAIP) + assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP)); +#endif /* RCC_PLLSAICFGR_PLLSAIP */ +#if defined(RCC_PLLSAICFGR_PLLSAIR) + assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR)); +#endif /* RCC_PLLSAICFGR_PLLSAIR */ + + /* Disable the PLLSAI */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Wait till PLLSAI is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Configure the PLLSAI division factors */ +#if defined(STM32F446xx) + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLSAIN/PLLSAIM) */ + /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIM, PLLSAIInit->PLLSAIN, \ + PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ, 0U); +#elif defined(STM32F469xx) || defined(STM32F479xx) + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */ + /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \ + PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); +#else + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x PLLSAIN */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); +#endif /* STM32F446xx */ + + /* Enable the PLLSAI */ + __HAL_RCC_PLLSAI_ENABLE(); + + /* Wait till PLLSAI is ready */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLLSAI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void) +{ + uint32_t tickstart; + + /* Disable the PLLSAI */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Wait till PLLSAI is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +#endif /* RCC_PLLSAI_SUPPORT */ + +/** + * @} + */ + #if defined(STM32F446xx) /** * @brief Returns the SYSCLK frequency - * + * * @note This function implementation is valid only for STM32F446xx devices. * @note This function add the PLL/PLLR System clock source * - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value * 16 MHz) but the real value may vary depending on the variations * in voltage and temperature. @@ -2808,17 +3041,17 @@ void HAL_RCCEx_SelectLSEMode(uint8_t Mode) * 25 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. - * + * * @note The result of this function could be not correct when using fractional * value for HSE crystal. - * - * @note This function can be used by the user application to compute the + * + * @note This function can be used by the user application to compute the * baudrate for the communication peripherals or configure other parameters. - * + * * @note Each time SYSCLK changes, this function must be called to update the * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * + * + * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) @@ -2850,15 +3083,15 @@ uint32_t HAL_RCC_GetSysClockFreq(void) if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) { /* HSE used as PLL clock source */ - pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); + pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); } else { /* HSI used as PLL clock source */ - pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); + pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); } - pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1U) *2U); - + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U); + sysclockfreq = pllvco/pllp; break; } @@ -2870,15 +3103,15 @@ uint32_t HAL_RCC_GetSysClockFreq(void) if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) { /* HSE used as PLL clock source */ - pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); + pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); } else { /* HSI used as PLL clock source */ - pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); + pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); } - pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)); - + pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos); + sysclockfreq = pllvco/pllr; break; } @@ -2900,11 +3133,6 @@ uint32_t HAL_RCC_GetSysClockFreq(void) * @} */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \ - defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ - defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /** * @brief Resets the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: @@ -2914,110 +3142,188 @@ uint32_t HAL_RCC_GetSysClockFreq(void) * - CSS, MCO1 and MCO2 OFF * - All interrupts disabled * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @retval None + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL status */ -void HAL_RCC_DeInit(void) +HAL_StatusTypeDef HAL_RCC_DeInit(void) { - /* Set HSION bit */ - SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); + uint32_t tickstart; + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Set HSION bit to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM[4:0] bits to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSITRIM_4); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); - /* Reset HSEON, CSSON, PLLON, PLLI2S bits */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON | RCC_CR_PLLON | RCC_CR_PLLI2SON); + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear HSEON, HSEBYP and CSSON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear PLLON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + +#if defined(RCC_PLLI2S_SUPPORT) + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLLI2SON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); + + /* Wait till PLLI2S is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLLSAI_SUPPORT) + /* Get Start Tick */ + tickstart = HAL_GetTick(); -#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Reset PLLSAI bit */ CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); -#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ - /* Reset PLLCFGR register */ - CLEAR_REG(RCC->PLLCFGR); + /* Wait till PLLSAI is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } +#endif /* RCC_PLLSAI_SUPPORT */ + + /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */ #if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \ defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLR_1); + RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLR_1; +#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) + RCC->PLLCFGR = RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_3; #else - SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2); + RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2; #endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx || STM32F469xx || STM32F479xx */ - /* Reset PLLI2SCFGR register */ - CLEAR_REG(RCC->PLLI2SCFGR); + /* Reset PLLI2SCFGR register to default value */ #if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \ defined(STM32F423xx) || defined(STM32F446xx) - SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1); + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1; #elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) - SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1); + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1; +#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1; #elif defined(STM32F411xE) - SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1); -#else - SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1); + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1; #endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx */ /* Reset PLLSAICFGR register */ #if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) - CLEAR_REG(RCC->PLLSAICFGR); - SET_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIR_1); + RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIR_1; #elif defined(STM32F446xx) - CLEAR_REG(RCC->PLLSAICFGR); - SET_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2); + RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2; #endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F469xx || STM32F479xx */ /* Disable all interrupts */ - CLEAR_REG(RCC->CIR); + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE); + +#if defined(RCC_CIR_PLLI2SRDYIE) + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); +#endif /* RCC_CIR_PLLI2SRDYIE */ + +#if defined(RCC_CIR_PLLSAIRDYIE) + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); +#endif /* RCC_CIR_PLLSAIRDYIE */ + + /* Clear all interrupt flags */ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC); + +#if defined(RCC_CIR_PLLI2SRDYC) + SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC); +#endif /* RCC_CIR_PLLI2SRDYC */ + +#if defined(RCC_CIR_PLLSAIRDYC) + SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC); +#endif /* RCC_CIR_PLLSAIRDYC */ + + /* Clear LSION bit */ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); + + /* Reset all CSR flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); /* Update the SystemCoreClock global variable */ SystemCoreClock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } } -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || - STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || - STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ - -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - HSI ON and used as system clock source - * - HSE and PLL OFF - * - AHB, APB1 and APB2 prescaler set to 1. - * - CSS, MCO1 and MCO2 OFF - * - All interrupts disabled - * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @retval None - */ -void HAL_RCC_DeInit(void) -{ - /* Set HSION bit */ - SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); - - /* Reset CFGR register */ - CLEAR_REG(RCC->CFGR); - - /* Reset HSEON, HSEBYP, CSSON, PLLON */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON | RCC_CR_PLLON); - - /* Reset PLLCFGR register */ - CLEAR_REG(RCC->PLLCFGR); - SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_3); - - /* Disable all interrupts */ - CLEAR_REG(RCC->CIR); - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HSI_VALUE; -} -#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /** * @brief Initializes the RCC Oscillators according to the specified parameters in the * RCC_OscInitTypeDef. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC Oscillators. * @note The PLL is not disabled when used as system clock. * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not @@ -3026,17 +3332,17 @@ void HAL_RCC_DeInit(void) * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not * supported by this API. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. - * @note This function add the PLL/PLLR factor management during PLL configuration this feature - * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices + * @note This function add the PLL/PLLR factor management during PLL configuration this feature + * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - uint32_t tickstart = 0U; - + uint32_t tickstart = 0U; + /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - /*------------------------------- HSE Configuration ------------------------*/ + /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) { /* Check the parameters */ @@ -3060,20 +3366,20 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - + /* Check the HSE State */ if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) { /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till HSE is ready */ + + /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } else @@ -3087,7 +3393,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } } @@ -3098,7 +3404,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ #if defined(STM32F446xx) if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ @@ -3132,15 +3438,15 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Get Start Tick*/ tickstart = HAL_GetTick(); - /* Wait till HSI is ready */ + /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } - } - + } + } + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); } @@ -3151,15 +3457,15 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ + + /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } - } + } + } } } } @@ -3174,60 +3480,70 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - + /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ + + /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } - } + } + } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) { + FlagStatus pwrclkchanged = RESET; + /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - PWR->CR |= PWR_CR_DBP; - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while((PWR->CR & PWR_CR_DBP) == RESET) + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) { - if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) { - return HAL_TIMEOUT; + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } } } - + /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); /* Check the LSE State */ @@ -3235,8 +3551,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) @@ -3249,16 +3565,22 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ + + /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } + + /* Restore clock configuration if changed */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ @@ -3267,7 +3589,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) - { + { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) { /* Check the parameters */ @@ -3277,21 +3599,21 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); - + /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ + + /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } - } + } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, @@ -3306,25 +3628,25 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ + + /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ + + /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) @@ -3343,9 +3665,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /** - * @brief Configures the RCC_OscInitStruct according to the internal + * @brief Configures the RCC_OscInitStruct according to the internal * RCC configuration registers. - * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that will be configured. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that will be configured. * * @note This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices. * @note This function add the PLL/PLLR factor management @@ -3355,7 +3677,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Set all possible values for the Oscillator type parameter ---------------*/ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; - + /* Get the HSE configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) { @@ -3369,7 +3691,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->HSEState = RCC_HSE_OFF; } - + /* Get the HSI configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) { @@ -3379,9 +3701,9 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->HSIState = RCC_HSI_OFF; } - - RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM)); - + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); + /* Get the LSE configuration -----------------------------------------------*/ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) { @@ -3395,7 +3717,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->LSEState = RCC_LSE_OFF; } - + /* Get the LSI configuration -----------------------------------------------*/ if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) { @@ -3405,7 +3727,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->LSIState = RCC_LSI_OFF; } - + /* Get the PLL configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) { @@ -3417,10 +3739,10 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); - RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)); - RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> POSITION_VAL(RCC_PLLCFGR_PLLP)); - RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)); - RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)); + RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos); + RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos); + RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos); } #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c index 7bfe61b7..bcac467d 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_spi.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief SPI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Serial Peripheral Interface (SPI) peripheral: @@ -256,7 +254,7 @@ static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Tim /** * @brief Initialize the SPI according to the specified parameters * in the SPI_InitTypeDef and initialize the associated handle. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ @@ -338,7 +336,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /** * @brief De Initialize the SPI peripheral. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval HAL status */ @@ -372,7 +370,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) /** * @brief Initialize the SPI MSP. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -387,7 +385,7 @@ __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) /** * @brief De-Initialize the SPI MSP. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -439,11 +437,11 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) /** * @brief Transmit an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @param Timeout: Timeout duration + * @param pData pointer to data buffer + * @param Size amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -609,11 +607,11 @@ error: /** * @brief Receive an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be received - * @param Timeout: Timeout duration + * @param pData pointer to data buffer + * @param Size amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -805,12 +803,12 @@ error : /** * @brief Transmit and Receive an amount of data in blocking mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @param Size: amount of data to be sent and received - * @param Timeout: Timeout duration + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) @@ -1030,10 +1028,10 @@ error : /** * @brief Transmit an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) @@ -1120,10 +1118,10 @@ error : /** * @brief Receive an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) @@ -1211,11 +1209,11 @@ error : /** * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @param Size: amount of data to be sent and received + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer + * @param Size amount of data to be sent and received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) @@ -1298,10 +1296,10 @@ error : /** * @brief Transmit an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param pData pointer to data buffer + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) @@ -1390,11 +1388,11 @@ error : /** * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData: pointer to data buffer + * @param pData pointer to data buffer * @note When the CRC feature is enabled the pData Length must be Size + 1. - * @param Size: amount of data to be sent + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) @@ -1486,12 +1484,12 @@ error: /** * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer + * @param pTxData pointer to transmission data buffer + * @param pRxData pointer to reception data buffer * @note When the CRC feature is enabled the pRxData Length must be Size + 1 - * @param Size: amount of data to be sent + * @param Size amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) @@ -1855,7 +1853,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) /** * @brief Pause the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -1875,7 +1873,7 @@ HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) /** * @brief Resume the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -1895,7 +1893,7 @@ HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) /** * @brief Stop the DMA Transfer. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval HAL status */ @@ -1926,7 +1924,7 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) /** * @brief Handle SPI interrupt request. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for the specified SPI module. * @retval None */ @@ -2022,7 +2020,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) /** * @brief Tx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2037,7 +2035,7 @@ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Rx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2052,7 +2050,7 @@ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Tx and Rx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2067,7 +2065,7 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Tx Half Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2082,7 +2080,7 @@ __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Rx Half Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2097,7 +2095,7 @@ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Tx and Rx Half Transfer callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2112,7 +2110,7 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief SPI error callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2164,7 +2162,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Return the SPI handle state. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval SPI state */ @@ -2176,7 +2174,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) /** * @brief Return the SPI error code. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval SPI error code in bitmap format */ @@ -2201,7 +2199,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) /** * @brief DMA SPI transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2245,7 +2243,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2312,7 +2310,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI transmit receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2376,7 +2374,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2389,7 +2387,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2402,7 +2400,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI half transmit receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2415,7 +2413,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA SPI communication error callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2550,7 +2548,7 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) /** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2584,7 +2582,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2611,7 +2609,7 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2644,7 +2642,7 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2678,7 +2676,7 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2702,7 +2700,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2738,7 +2736,7 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 8-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2758,7 +2756,7 @@ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Manage the receive 8-bit in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2791,7 +2789,7 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) #if (USE_SPI_CRC != 0U) /** * @brief Manage the CRC 16-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2814,7 +2812,7 @@ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) /** * @brief Manage the 16-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2847,7 +2845,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Handle the data 8-bit transmit in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2871,7 +2869,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Handle the data 16-bit transmit in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -2897,12 +2895,12 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) /** * @brief Handle SPI Communication Timeout. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Flag: SPI flag to check - * @param State: flag state to check - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param Flag SPI flag to check + * @param State flag state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart) @@ -2946,10 +2944,10 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, } /** * @brief Handle to check BSY flag before start a new transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param Timeout: Timeout duration - * @param Tickstart: tick start value + * @param Timeout Timeout duration + * @param Tickstart tick start value * @retval HAL status */ static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) @@ -2965,7 +2963,7 @@ static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Tim /** * @brief Handle the end of the RXTX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3039,7 +3037,7 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle the end of the RX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3088,7 +3086,7 @@ static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle the end of the TX transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3143,7 +3141,7 @@ static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle abort a Tx or Rx transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ @@ -3178,7 +3176,7 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) /** * @brief Handle abort a Tx or Rx transaction. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c index ea68dd1f..89db4b61 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_tim.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: @@ -201,7 +199,7 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /** * @brief Initializes the TIM Time base Unit according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -240,7 +238,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitializes the TIM Base peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -268,7 +266,7 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Base MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -283,7 +281,7 @@ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Base MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -298,7 +296,7 @@ __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -322,7 +320,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Base generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -346,7 +344,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -367,7 +365,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Base generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -387,10 +385,10 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Base generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to peripheral. + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) @@ -434,7 +432,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /** * @brief Stops the TIM Base generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -483,7 +481,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -522,7 +520,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) /** * @brief DeInitializes the TIM peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -550,7 +548,7 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -565,7 +563,7 @@ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Output Compare MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -580,9 +578,9 @@ __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Output Compare signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -613,9 +611,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -646,9 +644,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -713,9 +711,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -780,16 +778,16 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -900,9 +898,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Output Compare signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -995,7 +993,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Initializes the TIM PWM Time Base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -1034,7 +1032,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitializes the TIM peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -1062,7 +1060,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM PWM MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1077,7 +1075,7 @@ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM PWM MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1092,9 +1090,9 @@ __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the PWM signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1125,9 +1123,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the PWM signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1161,9 +1159,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1228,9 +1226,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the PWM signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1295,16 +1293,16 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1415,9 +1413,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1510,7 +1508,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Initializes the TIM Input Capture Time base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -1549,7 +1547,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) /** * @brief DeInitializes the TIM peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -1577,7 +1575,7 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM INput Capture MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1592,7 +1590,7 @@ __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Input Capture MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1607,9 +1605,9 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Input Capture measurement. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1634,9 +1632,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Input Capture measurement. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1661,9 +1659,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Input Capture measurement in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1721,9 +1719,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1782,16 +1780,16 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Input Capture measurement on in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1898,9 +1896,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the TIM Input Capture measurement on in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1988,9 +1986,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Initializes the TIM One Pulse Time Base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OnePulseMode: Select the One pulse mode. + * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. @@ -2038,7 +2036,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul /** * @brief DeInitializes the TIM One Pulse - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -2066,7 +2064,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM One Pulse MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -2081,7 +2079,7 @@ __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM One Pulse MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -2096,9 +2094,9 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM One Pulse signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel : TIM Channels to be enabled. + * @param OutputChannel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2133,9 +2131,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu /** * @brief Stops the TIM One Pulse signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel : TIM Channels to be disable. + * @param OutputChannel TIM Channels to be disable. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2170,9 +2168,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel : TIM Channels to be enabled. + * @param OutputChannel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2213,9 +2211,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel : TIM Channels to be enabled. + * @param OutputChannel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2279,9 +2277,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out */ /** * @brief Initializes the TIM Encoder Interface and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM Encoder Interface configuration structure + * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) @@ -2369,7 +2367,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /** * @brief DeInitializes the TIM Encoder interface - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -2397,7 +2395,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Encoder Interface MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -2412,7 +2410,7 @@ __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Encoder Interface MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -2427,9 +2425,9 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Encoder Interface. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2470,9 +2468,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Stops the TIM Encoder Interface. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2514,9 +2512,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Starts the TIM Encoder Interface in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2563,9 +2561,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha /** * @brief Stops the TIM Encoder Interface in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2615,16 +2613,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM Encoder Interface in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @param pData1: The destination Buffer address for IC1. - * @param pData2: The destination Buffer address for IC2. - * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) @@ -2736,9 +2734,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /** * @brief Stops the TIM Encoder Interface in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2804,7 +2802,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha */ /** * @brief This function handles TIM interrupts requests. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -2960,10 +2958,10 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Output Compare Channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM Output Compare configuration structure - * @param Channel: TIM Channels to be enabled. + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3030,10 +3028,10 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT /** * @brief Initializes the TIM Input Capture Channels according to the specified * parameters in the TIM_IC_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM Input Capture configuration structure - * @param Channel: TIM Channels to be enabled. + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3127,10 +3125,10 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /** * @brief Initializes the TIM PWM channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM PWM configuration structure - * @param Channel: TIM Channels to be enabled. + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3226,14 +3224,14 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_Init /** * @brief Initializes the TIM One Pulse Channels according to the specified * parameters in the TIM_OnePulse_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM One Pulse configuration structure - * @param OutputChannel: TIM Channels to be enabled. + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel: TIM Channels to be enabled. + * @param InputChannel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3339,9 +3337,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O /** * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write. + * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data write. * This parameters can be on of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 @@ -3362,7 +3360,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc: TIM DMA Request sources. + * @param BurstRequestSrc TIM DMA Request sources. * This parameters can be on of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source @@ -3371,8 +3369,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer: The Buffer address. - * @param BurstLength: DMA Burst length. This parameter can be one value + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @retval HAL status */ @@ -3503,9 +3501,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM DMA Burst mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param BurstRequestSrc: TIM DMA Request sources to disable + * @param BurstRequestSrc TIM DMA Request sources to disable * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) @@ -3564,9 +3562,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read. + * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data read. * This parameters can be on of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 @@ -3587,7 +3585,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc: TIM DMA Request sources. + * @param BurstRequestSrc TIM DMA Request sources. * This parameters can be on of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source @@ -3596,8 +3594,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer: The Buffer address. - * @param BurstLength: DMA Burst length. This parameter can be one value + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @retval HAL status */ @@ -3729,9 +3727,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B /** * @brief Stop the DMA burst reading - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param BurstRequestSrc: TIM DMA Request sources to disable. + * @param BurstRequestSrc TIM DMA Request sources to disable. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) @@ -3790,9 +3788,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu /** * @brief Generate a software event - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param EventSource: specifies the event source. + * @param EventSource specifies the event source. * This parameter can be one of the following values: * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source @@ -3833,11 +3831,11 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS /** * @brief Configures the OCRef clear feature - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel: specifies the TIM Channel. + * @param Channel specifies the TIM Channel. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3942,9 +3940,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInp /** * @brief Configures the clock source to be used - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ @@ -4099,9 +4097,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo /** * @brief Selects the signal connected to the TI1 input: direct from CH1_input * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param TI1_Selection: Indicate whether or not channel 1 is connected to the + * @param TI1_Selection Indicate whether or not channel 1 is connected to the * output of a XOR gate. * This parameter can be one of the following values: * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input @@ -4134,9 +4132,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S /** * @brief Configures the TIM in Slave mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the ) and the Slave * mode (Disable, Reset, Gated, Trigger, External clock mode 1). @@ -4170,8 +4168,8 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI /** * @brief Configures the TIM in Slave mode in interrupt mode - * @param htim: TIM handle. - * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the ) and the Slave * mode (Disable, Reset, Gated, Trigger, External clock mode 1). @@ -4206,9 +4204,9 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, /** * @brief Read the captured value from Capture Compare unit - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -4299,7 +4297,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Period elapsed callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4314,7 +4312,7 @@ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) /** * @brief Output Compare callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4329,7 +4327,7 @@ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) /** * @brief Input Capture callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4344,7 +4342,7 @@ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) /** * @brief PWM Pulse finished callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4359,7 +4357,7 @@ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) /** * @brief Hall Trigger detection callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4374,7 +4372,7 @@ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) /** * @brief Timer error callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4407,7 +4405,7 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Base state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4418,7 +4416,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM OC state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4429,7 +4427,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM PWM state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4440,7 +4438,7 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Input Capture state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4451,7 +4449,7 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM One Pulse Mode state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4462,7 +4460,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Encoder Mode state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4476,8 +4474,8 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) /** * @brief Time Base configuration - * @param TIMx: TIM peripheral - * @param Structure: pointer on TIM Time Base required parameters + * @param TIMx TIM peripheral + * @param Structure pointer on TIM Time Base required parameters * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) @@ -4522,17 +4520,17 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) /** * @brief Configure the TI1 as Input. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be @@ -4578,7 +4576,7 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ /** * @brief Time Output Compare 2 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure + * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4644,7 +4642,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief TIM DMA Delay Pulse complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -4678,7 +4676,7 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -4693,7 +4691,7 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Capture complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -4728,13 +4726,13 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) /** * @brief Enables or disables the TIM Capture Compare Channel x. * @param TIMx to select the TIM peripheral - * @param Channel: specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 * @arg TIM_Channel_3: TIM Channel 3 * @arg TIM_Channel_4: TIM Channel 4 - * @param ChannelState: specifies the TIM Channel CCxE bit new state. + * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. * @retval None */ @@ -4757,7 +4755,7 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat /** * @brief TIM DMA Period Elapse complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -4772,7 +4770,7 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Trigger callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -4788,7 +4786,7 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) /** * @brief Time Output Compare 1 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4853,7 +4851,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Output Compare 3 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4921,7 +4919,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Output Compare 4 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4977,9 +4975,9 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Time Output Compare 4 configuration - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sSlaveConfig: The slave configuration structure + * @param sSlaveConfig The slave configuration structure * @retval None */ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, @@ -5110,12 +5108,12 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /** * @brief Configure the Polarity and Filter for TI1. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ @@ -5145,17 +5143,17 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /** * @brief Configure the TI2 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be @@ -5193,12 +5191,12 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Configure the Polarity and Filter for TI2. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ @@ -5228,17 +5226,17 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /** * @brief Configure the TI3 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 * (on channel4 path) is used as the input signal. Therefore CCMR2 must be @@ -5276,17 +5274,17 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Configure the TI4 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 * (on channel3 path) is used as the input signal. Therefore CCMR2 must be @@ -5324,7 +5322,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /** * @brief Selects the Input Trigger source * @param TIMx to select the TIM peripheral - * @param TIM_ITRx: The Input Trigger source. + * @param TIM_ITRx The Input Trigger source. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal Trigger 0 * @arg TIM_TS_ITR1: Internal Trigger 1 @@ -5353,17 +5351,17 @@ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx) /** * @brief Configures the TIMx External Trigger (ETR). * @param TIMx to select the TIM peripheral - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. * This parameter can be one of the following values: * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF. * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2. * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4. * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. * This parameter can be one of the following values: * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active. * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. + * @param ExtTRGFilter External Trigger Filter. * This parameter must be a value between 0x00 and 0x0F * @retval None */ diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c index b6a3a2e4..a77b21de 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer extension peripheral: @@ -151,9 +149,9 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Cha */ /** * @brief Initializes the TIM Hall Sensor Interface and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM Hall Sensor configuration structure + * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) @@ -225,7 +223,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen /** * @brief DeInitializes the TIM Hall Sensor interface - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -253,7 +251,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) /** * @brief Initializes the TIM Hall Sensor MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -268,7 +266,7 @@ __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) /** * @brief DeInitializes TIM Hall Sensor MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -283,7 +281,7 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -305,7 +303,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Hall sensor Interface. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -327,7 +325,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -352,7 +350,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) /** * @brief Stops the TIM Hall Sensor Interface in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -377,10 +375,10 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Hall Sensor Interface in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) @@ -427,7 +425,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /** * @brief Stops the TIM Hall Sensor Interface in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -477,14 +475,13 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM Output Compare signal generation on the complementary * output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -508,14 +505,13 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation on the complementary * output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -539,14 +535,13 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the TIM Output Compare signal generation in interrupt mode * on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -607,14 +602,13 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann /** * @brief Stops the TIM Output Compare signal generation in interrupt mode * on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -678,16 +672,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Starts the TIM Output Compare signal generation in DMA mode * on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -796,14 +789,13 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Stops the TIM Output Compare signal generation in DMA mode * on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -896,14 +888,13 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann /** * @brief Starts the PWM signal generation on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -926,14 +917,13 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Stops the PWM signal generation on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -957,14 +947,13 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode on the * complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1025,14 +1014,13 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Stops the PWM signal generation in interrupt mode on the * complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1096,16 +1084,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM PWM signal generation in DMA mode on the * complementary output - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1214,14 +1201,13 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /** * @brief Stops the TIM PWM signal generation in DMA mode on the complementary * output - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1304,9 +1290,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM One Pulse signal generation on the complementary * output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel: TIM Channel to be enabled. + * @param OutputChannel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1330,9 +1316,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel: TIM Channel to be disabled. + * @param OutputChannel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1360,9 +1346,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel: TIM Channel to be enabled. + * @param OutputChannel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1392,9 +1378,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel: TIM Channel to be disabled. + * @param OutputChannel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1454,16 +1440,16 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource: the Commutation Event source. + * @param CommutationSource the Commutation Event source. * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1504,16 +1490,16 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource: the Commutation Event source. + * @param CommutationSource the Commutation Event source. * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1558,16 +1544,16 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, u * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource: the Commutation Event source. + * @param CommutationSource the Commutation Event source. * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1611,9 +1597,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, /** * @brief Configures the TIM in master mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that * contains the selected trigger output (TRGO) and the Master/Slave * mode. * @retval HAL status @@ -1649,9 +1635,9 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, /** * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State * and the AOE(automatic output enable). - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. * @retval HAL status */ @@ -1696,9 +1682,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, /** * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Remap: specifies the TIM input remapping source. + * @param Remap specifies the TIM input remapping source. * This parameter can be one of the following values: * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output. @@ -1773,7 +1759,7 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) /** * @brief Hall commutation changed callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1788,7 +1774,7 @@ __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim) /** * @brief Hall Break detection callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1821,7 +1807,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) /** * @brief Return the TIM Hall Sensor interface state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -1836,7 +1822,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) /** * @brief TIM DMA Commutation callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1855,12 +1841,12 @@ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx to select the TIM peripheral - * @param Channel: specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 * @arg TIM_Channel_3: TIM Channel 3 - * @param ChannelNState: specifies the TIM Channel CCxNE bit new state. + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None */ diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c index 40f28ea8..2c878307 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_uart.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief UART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: @@ -239,7 +237,7 @@ static void UART_SetConfig (UART_HandleTypeDef *huart); /** * @brief Initializes the UART mode according to the specified parameters in * the UART_InitTypeDef and create the associated handle. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -301,7 +299,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) /** * @brief Initializes the half-duplex mode according to the specified * parameters in the UART_InitTypeDef and create the associated handle. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -357,9 +355,9 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /** * @brief Initializes the LIN mode according to the specified * parameters in the UART_InitTypeDef and create the associated handle. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @param BreakDetectLength: Specifies the LIN break detection length. + * @param BreakDetectLength Specifies the LIN break detection length. * This parameter can be one of the following values: * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection @@ -422,10 +420,10 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe /** * @brief Initializes the Multi-Processor mode according to the specified * parameters in the UART_InitTypeDef and create the associated handle. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @param Address: USART address - * @param WakeUpMethod: specifies the USART wake-up method. + * @param Address USART address + * @param WakeUpMethod specifies the USART wake-up method. * This parameter can be one of the following values: * @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection * @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark @@ -490,7 +488,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /** * @brief DeInitializes the UART peripheral. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -522,7 +520,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) /** * @brief UART MSP Init. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ @@ -537,7 +535,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) /** * @brief UART MSP DeInit. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ @@ -608,11 +606,11 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) /** * @brief Sends an amount of data in blocking mode. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -690,11 +688,11 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /** * @brief Receives an amount of data in blocking mode. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -779,10 +777,10 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui /** * @brief Sends an amount of data in non blocking mode. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -821,10 +819,10 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData /** * @brief Receives an amount of data in non blocking mode - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received + * @param pData Pointer to data buffer + * @param Size Amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -866,10 +864,10 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /** * @brief Sends an amount of data in non blocking mode. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -930,10 +928,10 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /** * @brief Receives an amount of data in non blocking mode. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received + * @param pData Pointer to data buffer + * @param Size Amount of data to be received * @note When the UART parity is enabled (PCE = 1) the data received contain the parity bit. * @retval HAL status */ @@ -1000,7 +998,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData /** * @brief Pauses the DMA Transfer. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -1035,7 +1033,7 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) /** * @brief Resumes the DMA Transfer. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -1070,7 +1068,7 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) /** * @brief Stops the DMA Transfer. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -1518,7 +1516,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) /** * @brief This function handles UART interrupt request. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ @@ -1645,7 +1643,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /** * @brief Tx Transfer completed callbacks. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ @@ -1660,7 +1658,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /** * @brief Tx Half Transfer completed callbacks. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ @@ -1675,7 +1673,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /** * @brief Rx Transfer completed callbacks. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ @@ -1690,7 +1688,7 @@ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) /** * @brief Rx Half Transfer completed callbacks. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ @@ -1705,7 +1703,7 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) /** * @brief UART error callbacks. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ @@ -1785,7 +1783,7 @@ __weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart) /** * @brief Transmits break characters. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -1812,7 +1810,7 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) /** * @brief Enters the UART in mute mode. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -1839,7 +1837,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) /** * @brief Exits the UART mute mode: wake up software. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -1866,7 +1864,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart) /** * @brief Enables the UART transmitter and disables the UART receiver. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -1901,7 +1899,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) /** * @brief Enables the UART receiver and disables the UART transmitter. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -1958,7 +1956,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) /** * @brief Returns the UART state. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL state */ @@ -1973,7 +1971,7 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) /** * @brief Return the UART error code - * @param huart : pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART. * @retval UART Error Code */ @@ -1988,7 +1986,7 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) /** * @brief DMA UART transmit process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) @@ -2016,7 +2014,7 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA UART transmit process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2029,7 +2027,7 @@ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA UART receive process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) @@ -2056,7 +2054,7 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA UART receive process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -2069,7 +2067,7 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA UART communication error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) @@ -2099,12 +2097,12 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) /** * @brief This function handles UART Communication Timeout. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @param Flag: specifies the UART flag to check. - * @param Status: The new Flag status (SET or RESET). + * @param Flag specifies the UART flag to check. + * @param Status The new Flag status (SET or RESET). * @param Tickstart Tick start value - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) @@ -2137,7 +2135,7 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, /** * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) @@ -2151,7 +2149,7 @@ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) /** * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) @@ -2299,7 +2297,7 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) /** * @brief Sends an amount of data in non blocking mode. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -2346,7 +2344,7 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) /** * @brief Wraps up transmission in non blocking mode. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -2365,7 +2363,7 @@ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) /** * @brief Receives an amount of data in non blocking mode - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -2427,7 +2425,7 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) /** * @brief Configures the UART peripheral. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ diff --git a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c index 14fedd0d..61253fca 100644 --- a/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c +++ b/Firmware/Board/v3.3/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_usb.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief USB Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -97,8 +95,8 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); /** * @brief Initializes the USB Core - * @param USBx: USB Instance - * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains + * @param USBx USB Instance + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ @@ -145,7 +143,7 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c /** * @brief USB_EnableGlobalInt * Enables the controller's Global Int in the AHB Config reg - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) @@ -158,7 +156,7 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_DisableGlobalInt * Disable the controller's Global Int in the AHB Config reg - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) @@ -169,8 +167,8 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_SetCurrentMode : Set functional mode - * @param USBx : Selected device - * @param mode : current core mode + * @param USBx Selected device + * @param mode current core mode * This parameter can be one of these values: * @arg USB_OTG_DEVICE_MODE: Peripheral mode * @arg USB_OTG_HOST_MODE: Host mode @@ -197,8 +195,8 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeT /** * @brief USB_DevInit : Initializes the USB_OTG controller registers * for device mode - * @param USBx : Selected device - * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ @@ -342,8 +340,8 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c /** * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO - * @param USBx : Selected device - * @param num : FIFO number + * @param USBx Selected device + * @param num FIFO number * This parameter can be a value from 1 to 15 15 means Flush all Tx FIFOs * @retval HAL status @@ -369,7 +367,7 @@ HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ) /** * @brief USB_FlushRxFifo : Flush Rx FIFO - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) @@ -393,8 +391,8 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register * depending the PHY type and the enumeration speed of the device. - * @param USBx : Selected device - * @param speed : device speed + * @param USBx Selected device + * @param speed device speed * This parameter can be one of these values: * @arg USB_OTG_SPEED_HIGH: High speed mode * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode @@ -410,7 +408,7 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed) /** * @brief USB_GetDevSpeed :Return the Dev Speed - * @param USBx : Selected device + * @param USBx Selected device * @retval speed : device speed * This parameter can be one of these values: * @arg USB_OTG_SPEED_HIGH: High speed mode @@ -440,8 +438,8 @@ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) /** * @brief Activate and configure an endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) @@ -470,8 +468,8 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy } /** * @brief Activate and configure a dedicated endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) @@ -513,8 +511,8 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB } /** * @brief De-activate and de-initialize an endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) @@ -584,8 +582,8 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP /** * @brief De-activate and de-initialize a dedicated endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) @@ -656,9 +654,9 @@ HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, U /** * @brief USB_EPStartXfer : setup and starts a transfer over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @param dma: USB dma enabled or disabled + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @param dma USB dma enabled or disabled * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used @@ -778,9 +776,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe /** * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0 - * @param USBx : Selected device - * @param ep: pointer to endpoint structure - * @param dma: USB dma enabled or disabled + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @param dma USB dma enabled or disabled * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used @@ -866,11 +864,11 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD /** * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated * with the EP/channel - * @param USBx : Selected device - * @param src : pointer to source buffer - * @param ch_ep_num : endpoint or host channel number - * @param len : Number of bytes to write - * @param dma: USB dma enabled or disabled + * @param USBx Selected device + * @param src pointer to source buffer + * @param ch_ep_num endpoint or host channel number + * @param len Number of bytes to write + * @param dma USB dma enabled or disabled * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used @@ -894,11 +892,11 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin /** * @brief USB_ReadPacket : read a packet from the Tx FIFO associated * with the EP/channel - * @param USBx : Selected device - * @param src : source pointer - * @param ch_ep_num : endpoint or host channel number - * @param len : Number of bytes to read - * @param dma: USB dma enabled or disabled + * @param USBx Selected device + * @param src source pointer + * @param ch_ep_num endpoint or host channel number + * @param len Number of bytes to read + * @param dma USB dma enabled or disabled * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used @@ -919,8 +917,8 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) /** * @brief USB_EPSetStall : set a stall condition over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep) @@ -947,8 +945,8 @@ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef /** * @brief USB_EPClearStall : Clear a stall condition over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) @@ -974,7 +972,7 @@ HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe /** * @brief USB_StopDevice : Stop the usb device mode - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) @@ -1003,8 +1001,8 @@ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_SetDevAddress : Stop the usb device mode - * @param USBx : Selected device - * @param address : new device address to be assigned + * @param USBx Selected device + * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ @@ -1018,7 +1016,7 @@ HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t addre /** * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx) @@ -1031,7 +1029,7 @@ HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx) @@ -1044,7 +1042,7 @@ HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_ReadInterrupts: return the global USB interrupt status - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx) @@ -1058,7 +1056,7 @@ uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx) @@ -1071,7 +1069,7 @@ uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx) @@ -1084,8 +1082,8 @@ uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx) /** * @brief Returns Device OUT EP Interrupt register - * @param USBx : Selected device - * @param epnum : endpoint number + * @param USBx Selected device + * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device OUT EP Interrupt register */ @@ -1099,8 +1097,8 @@ uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) /** * @brief Returns Device IN EP Interrupt register - * @param USBx : Selected device - * @param epnum : endpoint number + * @param USBx Selected device + * @param epnum endpoint number * This parameter can be a value from 0 to 15 * @retval Device IN EP Interrupt register */ @@ -1117,8 +1115,8 @@ uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) /** * @brief USB_ClearInterrupts: clear a USB interrupt - * @param USBx : Selected device - * @param interrupt : interrupt flag + * @param USBx Selected device + * @param interrupt interrupt flag * @retval None */ void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) @@ -1128,7 +1126,7 @@ void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) /** * @brief Returns USB core mode - * @param USBx : Selected device + * @param USBx Selected device * @retval return core mode : Host or Device * This parameter can be one of these values: * 0 : Host @@ -1142,7 +1140,7 @@ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) /** * @brief Activate EP0 for Setup transactions - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx) @@ -1162,12 +1160,12 @@ HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx) /** * @brief Prepare the EP0 to start the first control setup - * @param USBx : Selected device - * @param dma: USB dma enabled or disabled + * @param USBx Selected device + * @param dma USB dma enabled or disabled * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used - * @param psetup : pointer to setup packet + * @param psetup pointer to setup packet * @retval HAL status */ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) @@ -1190,7 +1188,7 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uin /** * @brief Reset the USB Core (needed after USB clock settings change) - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) @@ -1227,8 +1225,8 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_HostInit : Initializes the USB OTG controller registers * for Host mode - * @param USBx : Selected device - * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ @@ -1314,8 +1312,8 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef /** * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the * HCFG register on the PHY type and set the right frame interval - * @param USBx : Selected device - * @param freq : clock frequency + * @param USBx Selected device + * @param freq clock frequency * This parameter can be one of these values: * HCFG_48_MHZ : Full Speed 48 MHz Clock * HCFG_6_MHZ : Low Speed 6 MHz Clock @@ -1339,7 +1337,7 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq /** * @brief USB_OTG_ResetPort : Reset Host Port - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status * @note (1)The application must wait at least 10 ms * before clearing the reset bit. @@ -1361,7 +1359,7 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_DriveVbus : activate or de-activate vbus - * @param state : VBUS state + * @param state VBUS state * This parameter can be one of these values: * 0 : VBUS Active * 1 : VBUS Inactive @@ -1388,7 +1386,7 @@ HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state) /** * @brief Return Host Core speed - * @param USBx : Selected device + * @param USBx Selected device * @retval speed : Host speed * This parameter can be one of these values: * @arg USB_OTG_SPEED_HIGH: High speed mode @@ -1405,7 +1403,7 @@ uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx) /** * @brief Return Host Current Frame number - * @param USBx : Selected device + * @param USBx Selected device * @retval current frame number */ uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx) @@ -1415,25 +1413,25 @@ uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx) /** * @brief Initialize a host channel - * @param USBx : Selected device - * @param ch_num : Channel number + * @param USBx Selected device + * @param ch_num Channel number * This parameter can be a value from 1 to 15 - * @param epnum : Endpoint number + * @param epnum Endpoint number * This parameter can be a value from 1 to 15 - * @param dev_address : Current device address + * @param dev_address Current device address * This parameter can be a value from 0 to 255 - * @param speed : Current device speed + * @param speed Current device speed * This parameter can be one of these values: * @arg USB_OTG_SPEED_HIGH: High speed mode * @arg USB_OTG_SPEED_FULL: Full speed mode * @arg USB_OTG_SPEED_LOW: Low speed mode - * @param ep_type : Endpoint Type + * @param ep_type Endpoint Type * This parameter can be one of these values: * @arg EP_TYPE_CTRL: Control type * @arg EP_TYPE_ISOC: Isochronous type * @arg EP_TYPE_BULK: Bulk type * @arg EP_TYPE_INTR: Interrupt type - * @param mps : Max Packet Size + * @param mps Max Packet Size * This parameter can be a value from 0 to32K * @retval HAL state */ @@ -1529,9 +1527,9 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, /** * @brief Start a transfer over a host channel - * @param USBx : Selected device - * @param hc : pointer to host channel structure - * @param dma: USB dma enabled or disabled + * @param USBx Selected device + * @param hc pointer to host channel structure + * @param dma USB dma enabled or disabled * This parameter can be one of these values: * 0 : DMA feature not used * 1 : DMA feature used @@ -1650,7 +1648,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe /** * @brief Read all host channel interrupts status - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL state */ uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx) @@ -1660,8 +1658,8 @@ uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx) /** * @brief Halt a host channel - * @param USBx : Selected device - * @param hc_num : Host Channel number + * @param USBx Selected device + * @param hc_num Host Channel number * This parameter can be a value from 1 to 15 * @retval HAL state */ @@ -1721,8 +1719,8 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) /** * @brief Initiate Do Ping protocol - * @param USBx : Selected device - * @param hc_num : Host Channel number + * @param USBx Selected device + * @param hc_num Host Channel number * This parameter can be a value from 1 to 15 * @retval HAL state */ @@ -1745,7 +1743,7 @@ HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num) /** * @brief Stop Host Core - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL state */ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) diff --git a/Firmware/Board/v3.3/Inc/adc.h b/Firmware/Board/v3.3/Inc/adc.h index bb2cf1d4..0f3d0688 100644 --- a/Firmware/Board/v3.3/Inc/adc.h +++ b/Firmware/Board/v3.3/Inc/adc.h @@ -10,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/Firmware/Board/v3.3/Inc/can.h b/Firmware/Board/v3.3/Inc/can.h index 5e515bc4..9779bb35 100644 --- a/Firmware/Board/v3.3/Inc/can.h +++ b/Firmware/Board/v3.3/Inc/can.h @@ -10,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/Firmware/Board/v3.3/Inc/dma.h b/Firmware/Board/v3.3/Inc/dma.h index 1d73731f..c42738c6 100644 --- a/Firmware/Board/v3.3/Inc/dma.h +++ b/Firmware/Board/v3.3/Inc/dma.h @@ -10,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/Firmware/Board/v3.3/Inc/gpio.h b/Firmware/Board/v3.3/Inc/gpio.h index 74ce09da..756ea9f3 100644 --- a/Firmware/Board/v3.3/Inc/gpio.h +++ b/Firmware/Board/v3.3/Inc/gpio.h @@ -10,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/Firmware/Board/v3.3/Inc/main.h b/Firmware/Board/v3.3/Inc/main.h index c6276ad8..6b430f81 100644 --- a/Firmware/Board/v3.3/Inc/main.h +++ b/Firmware/Board/v3.3/Inc/main.h @@ -1,7 +1,8 @@ /** ****************************************************************************** - * File Name : main.h - * Description : This file contains the common defines of the application + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. ****************************************************************************** * This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and @@ -9,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -45,10 +46,12 @@ * ****************************************************************************** */ + /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MAIN_H -#define __MAIN_H - /* Includes ------------------------------------------------------------------*/ +#ifndef __MAIN_H__ +#define __MAIN_H__ + +/* Includes ------------------------------------------------------------------*/ /* USER CODE BEGIN Includes */ @@ -60,7 +63,7 @@ /* Private define ------------------------------------------------------------*/ #define TIM_1_8_CLOCK_HZ 168000000 -#define TIM_1_8_PERIOD_CLOCKS 8192 +#define TIM_1_8_PERIOD_CLOCKS 10192 #define TIM_1_8_DEADTIME_CLOCKS 20 #define TIM_APB1_CLOCK_HZ 84000000 #define TIM_APB1_PERIOD_CLOCKS 4096 @@ -148,6 +151,13 @@ #define M1_ENC_B_Pin GPIO_PIN_7 #define M1_ENC_B_GPIO_Port GPIOB +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + /* USER CODE BEGIN Private defines */ #endif @@ -162,17 +172,16 @@ /* USER CODE END Private defines */ +#ifdef __cplusplus + extern "C" { +#endif void _Error_Handler(char *, int); #define Error_Handler() _Error_Handler(__FILE__, __LINE__) +#ifdef __cplusplus +} +#endif -/** - * @} - */ +#endif /* __MAIN_H__ */ -/** - * @} -*/ - -#endif /* __MAIN_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3.3/Inc/spi.h b/Firmware/Board/v3.3/Inc/spi.h index c69e6ba1..b983c14a 100644 --- a/Firmware/Board/v3.3/Inc/spi.h +++ b/Firmware/Board/v3.3/Inc/spi.h @@ -10,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/Firmware/Board/v3.3/Inc/stm32f4xx_hal_conf.h b/Firmware/Board/v3.3/Inc/stm32f4xx_hal_conf.h index ded40897..d0f48f56 100644 --- a/Firmware/Board/v3.3/Inc/stm32f4xx_hal_conf.h +++ b/Firmware/Board/v3.3/Inc/stm32f4xx_hal_conf.h @@ -5,7 +5,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ *

© COPYRIGHT(c) 2018 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/Firmware/Board/v3.3/Inc/stm32f4xx_it.h b/Firmware/Board/v3.3/Inc/stm32f4xx_it.h index fd9b9628..1970c2a8 100644 --- a/Firmware/Board/v3.3/Inc/stm32f4xx_it.h +++ b/Firmware/Board/v3.3/Inc/stm32f4xx_it.h @@ -4,7 +4,7 @@ * @brief This file contains the headers of the interrupt handlers. ****************************************************************************** * - * COPYRIGHT(c) 2017 STMicroelectronics + * COPYRIGHT(c) 2018 STMicroelectronics * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/Firmware/Board/v3.3/Inc/tim.h b/Firmware/Board/v3.3/Inc/tim.h index 6b6ceb49..4ef67076 100644 --- a/Firmware/Board/v3.3/Inc/tim.h +++ b/Firmware/Board/v3.3/Inc/tim.h @@ -10,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/Firmware/Board/v3.3/Inc/usart.h b/Firmware/Board/v3.3/Inc/usart.h index 808284cd..c987f7f2 100644 --- a/Firmware/Board/v3.3/Inc/usart.h +++ b/Firmware/Board/v3.3/Inc/usart.h @@ -10,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/Firmware/Board/v3.3/Inc/usb_device.h b/Firmware/Board/v3.3/Inc/usb_device.h index 5115d20e..740a7b90 100644 --- a/Firmware/Board/v3.3/Inc/usb_device.h +++ b/Firmware/Board/v3.3/Inc/usb_device.h @@ -1,8 +1,8 @@ /** ****************************************************************************** - * @file : USB_DEVICE + * @file : usb_device.h * @version : v1.0_Cube - * @brief : Header for usb_device file. + * @brief : Header for usb_device.c file. ****************************************************************************** * This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and @@ -10,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -45,10 +45,12 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** -*/ + */ + /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __usb_device_H -#define __usb_device_H +#ifndef __USB_DEVICE__H__ +#define __USB_DEVICE__H__ + #ifdef __cplusplus extern "C" { #endif @@ -58,22 +60,55 @@ #include "stm32f4xx_hal.h" #include "usbd_def.h" +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +/** @addtogroup USBD_OTG_DRIVER + * @{ + */ + +/** @defgroup USBD_DEVICE USBD_DEVICE + * @brief Device file for Usb otg low level driver. + * @{ + */ + +/** @defgroup USBD_DEVICE_Exported_Variables USBD_DEVICE_Exported_Variables + * @brief Public variables. + * @{ + */ + +/** USB device core handle. */ extern USBD_HandleTypeDef hUsbDeviceFS; -/* USB_Device init function */ +/** + * @} + */ + +/** @defgroup USBD_DEVICE_Exported_FunctionsPrototype USBD_DEVICE_Exported_FunctionsPrototype + * @brief Declaration of public functions for Usb device. + * @{ + */ + +/** USB Device initialization function. */ void MX_USB_DEVICE_Init(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + #ifdef __cplusplus } #endif -#endif /*__usb_device_H */ -/** - * @} - */ - -/** - * @} - */ +#endif /* __USB_DEVICE__H__ */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3.3/Inc/usbd_cdc_if.h b/Firmware/Board/v3.3/Inc/usbd_cdc_if.h index 3584347d..8fa95cc8 100644 --- a/Firmware/Board/v3.3/Inc/usbd_cdc_if.h +++ b/Firmware/Board/v3.3/Inc/usbd_cdc_if.h @@ -1,7 +1,8 @@ /** ****************************************************************************** * @file : usbd_cdc_if.h - * @brief : Header for usbd_cdc_if file. + * @version : v1.0_Cube + * @brief : Header for usbd_cdc_if.c file. ****************************************************************************** * This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and @@ -9,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -44,32 +45,36 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** -*/ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_CDC_IF_H -#define __USBD_CDC_IF_H +#ifndef __USBD_CDC_IF_H__ +#define __USBD_CDC_IF_H__ #ifdef __cplusplus extern "C" { #endif + /* Includes ------------------------------------------------------------------*/ #include "usbd_cdc.h" + /* USER CODE BEGIN INCLUDE */ /* USER CODE END INCLUDE */ /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @brief For Usb device. * @{ */ -/** @defgroup USBD_CDC_IF - * @brief header +/** @defgroup USBD_CDC_IF USBD_CDC_IF + * @brief Usb VCP device module * @{ */ -/** @defgroup USBD_CDC_IF_Exported_Defines +/** @defgroup USBD_CDC_IF_Exported_Defines USBD_CDC_IF_Exported_Defines + * @brief Defines. * @{ - */ + */ /* USER CODE BEGIN EXPORTED_DEFINES */ /* Define size for the receive and transmit buffer over CDC */ /* It's up to user to redefine and/or remove those define */ @@ -79,63 +84,73 @@ /** * @} - */ + */ -/** @defgroup USBD_CDC_IF_Exported_Types +/** @defgroup USBD_CDC_IF_Exported_Types USBD_CDC_IF_Exported_Types + * @brief Types. * @{ - */ + */ + /* USER CODE BEGIN EXPORTED_TYPES */ /* USER CODE END EXPORTED_TYPES */ /** * @} - */ + */ -/** @defgroup USBD_CDC_IF_Exported_Macros +/** @defgroup USBD_CDC_IF_Exported_Macros USBD_CDC_IF_Exported_Macros + * @brief Aliases. * @{ - */ + */ + /* USER CODE BEGIN EXPORTED_MACRO */ /* USER CODE END EXPORTED_MACRO */ /** * @} - */ + */ -/** @defgroup USBD_AUDIO_IF_Exported_Variables +/** @defgroup USBD_CDC_IF_Exported_Variables USBD_CDC_IF_Exported_Variables + * @brief Public variables. * @{ - */ -extern USBD_CDC_ItfTypeDef USBD_Interface_fops_FS; + */ + +/** CDC Interface callback. */ +extern USBD_CDC_ItfTypeDef USBD_Interface_fops_FS; /* USER CODE BEGIN EXPORTED_VARIABLES */ /* USER CODE END EXPORTED_VARIABLES */ /** * @} - */ + */ -/** @defgroup USBD_CDC_IF_Exported_FunctionsPrototype +/** @defgroup USBD_CDC_IF_Exported_FunctionsPrototype USBD_CDC_IF_Exported_FunctionsPrototype + * @brief Public functions declaration. * @{ - */ + */ + uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len); /* USER CODE BEGIN EXPORTED_FUNCTIONS */ /* USER CODE END EXPORTED_FUNCTIONS */ -/** - * @} - */ /** * @} - */ + */ /** * @} - */ - + */ + +/** + * @} + */ + #ifdef __cplusplus } #endif - -#endif /* __USBD_CDC_IF_H */ + +#endif /* __USBD_CDC_IF_H__ */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3.3/Inc/usbd_conf.h b/Firmware/Board/v3.3/Inc/usbd_conf.h index 0bd92766..bf276186 100644 --- a/Firmware/Board/v3.3/Inc/usbd_conf.h +++ b/Firmware/Board/v3.3/Inc/usbd_conf.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file : usbd_conf.h * @version : v1.0_Cube - * @brief : Header for usbd_conf file. + * @brief : Header for usbd_conf.c file. ****************************************************************************** * This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and @@ -10,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -45,13 +45,16 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** -*/ + */ + /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __USBD_CONF__H__ #define __USBD_CONF__H__ + #ifdef __cplusplus extern "C" { #endif + /* Includes ------------------------------------------------------------------*/ #include #include @@ -59,18 +62,33 @@ #include "stm32f4xx.h" #include "stm32f4xx_hal.h" +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + /** @addtogroup USBD_OTG_DRIVER + * @brief Driver for Usb device. * @{ */ - -/** @defgroup USBD_CONF - * @brief usb otg low level driver configuration file - * @{ - */ -/** @defgroup USBD_CONF_Exported_Defines +/** @defgroup USBD_CONF USBD_CONF + * @brief Configuration file for Usb otg low level driver. * @{ - */ + */ + +/** @defgroup USBD_CONF_Exported_Variables USBD_CONF_Exported_Variables + * @brief Public variables. + * @{ + */ + +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_Defines USBD_CONF_Exported_Defines + * @brief Defines for configuration of the Usb device. + * @{ + */ /*---------- -----------*/ #define USBD_MAX_NUM_INTERFACES 1 @@ -92,95 +110,94 @@ #define DEVICE_FS 0 #define DEVICE_HS 1 -/** @defgroup USBD_Exported_Macros +/** + * @} + */ + +/** @defgroup USBD_CONF_Exported_Macros USBD_CONF_Exported_Macros + * @brief Aliases. * @{ - */ + */ - /* Memory management macros */ -#define USBD_malloc malloc -#define USBD_free free -#define USBD_memset memset -#define USBD_memcpy memcpy +/* Memory management macros */ -#define USBD_Delay HAL_Delay - - /* DEBUG macros */ +/** Alias for memory allocation. */ +#define USBD_malloc malloc + +/** Alias for memory release. */ +#define USBD_free free + +/** Alias for memory set. */ +#define USBD_memset memset + +/** Alias for memory copy. */ +#define USBD_memcpy memcpy + +/** Alias for delay. */ +#define USBD_Delay HAL_Delay + +/* DEBUG macros */ #if (USBD_DEBUG_LEVEL > 0) -#define USBD_UsrLog(...) printf(__VA_ARGS__);\ +#define USBD_UsrLog(...) printf(__VA_ARGS__);\ printf("\n"); #else -#define USBD_UsrLog(...) -#endif - - +#define USBD_UsrLog(...) +#endif + #if (USBD_DEBUG_LEVEL > 1) -#define USBD_ErrLog(...) printf("ERROR: ") ;\ +#define USBD_ErrLog(...) printf("ERROR: ") ;\ printf(__VA_ARGS__);\ printf("\n"); #else -#define USBD_ErrLog(...) -#endif - - -#if (USBD_DEBUG_LEVEL > 2) -#define USBD_DbgLog(...) printf("DEBUG : ") ;\ - printf(__VA_ARGS__);\ - printf("\n"); -#else -#define USBD_DbgLog(...) +#define USBD_ErrLog(...) #endif - -/** - * @} - */ - - - -/** - * @} - */ -/** @defgroup USBD_CONF_Exported_Types - * @{ - */ -/** - * @} - */ +#if (USBD_DEBUG_LEVEL > 2) +#define USBD_DbgLog(...) printf("DEBUG : ") ;\ + printf(__VA_ARGS__);\ + printf("\n"); +#else +#define USBD_DbgLog(...) +#endif -/** @defgroup USBD_CONF_Exported_Macros - * @{ - */ /** * @} - */ + */ -/** @defgroup USBD_CONF_Exported_Variables +/** @defgroup USBD_CONF_Exported_Types USBD_CONF_Exported_Types + * @brief Types. * @{ - */ -/** - * @} - */ + */ -/** @defgroup USBD_CONF_Exported_FunctionsPrototype - * @{ - */ /** * @} - */ + */ + +/** @defgroup USBD_CONF_Exported_FunctionsPrototype USBD_CONF_Exported_FunctionsPrototype + * @brief Declaration of public functions for Usb device. + * @{ + */ + +/* Exported functions -------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + #ifdef __cplusplus } #endif #endif /* __USBD_CONF__H__ */ -/** - * @} - */ - -/** - * @} - */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/Firmware/Board/v3.3/Inc/usbd_desc.h b/Firmware/Board/v3.3/Inc/usbd_desc.h index 1485f6db..d791d3d4 100644 --- a/Firmware/Board/v3.3/Inc/usbd_desc.h +++ b/Firmware/Board/v3.3/Inc/usbd_desc.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file : usbd_desc.h * @version : v1.0_Cube - * @brief : Header for usbd_desc file. + * @brief : Header for usbd_desc.c file. ****************************************************************************** * This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and @@ -10,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -45,7 +45,7 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** -*/ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __USBD_DESC__H__ @@ -54,66 +54,103 @@ #ifdef __cplusplus extern "C" { #endif + /* Includes ------------------------------------------------------------------*/ #include "usbd_def.h" +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY * @{ */ - -/** @defgroup USB_DESC - * @brief general defines for the usb device library file - * @{ - */ -/** @defgroup USB_DESC_Exported_Defines +/** @defgroup USBD_DESC USBD_DESC + * @brief Usb device descriptors module. * @{ */ -/** - * @} - */ - -/** @defgroup USBD_DESC_Exported_TypesDefinitions +/** @defgroup USBD_DESC_Exported_Defines USBD_DESC_Exported_Defines + * @brief Defines. * @{ */ + +/* USER CODE BEGIN EXPORTED_DEFINES */ + +/* USER CODE END EXPORTED_DEFINES */ + /** * @} - */ + */ -/** @defgroup USBD_DESC_Exported_Macros +/** @defgroup USBD_DESC_Exported_TypesDefinitions USBD_DESC_Exported_TypesDefinitions + * @brief Types. * @{ - */ + */ + +/* USER CODE BEGIN EXPORTED_TYPES */ + +/* USER CODE END EXPORTED_TYPES */ + /** * @} - */ + */ -/** @defgroup USBD_DESC_Exported_Variables +/** @defgroup USBD_DESC_Exported_Macros USBD_DESC_Exported_Macros + * @brief Aliases. * @{ - */ + */ + +/* USER CODE BEGIN EXPORTED_MACRO */ + +/* USER CODE END EXPORTED_MACRO */ + +/** + * @} + */ + +/** @defgroup USBD_DESC_Exported_Variables USBD_DESC_Exported_Variables + * @brief Public variables. + * @{ + */ + +/** Descriptor for the Usb device. */ extern USBD_DescriptorsTypeDef FS_Desc; -/** - * @} - */ -/** @defgroup USBD_DESC_Exported_FunctionsPrototype - * @{ - */ - +/* USER CODE BEGIN EXPORTED_VARIABLES */ + +/* USER CODE END EXPORTED_VARIABLES */ + /** * @} - */ + */ + +/** @defgroup USBD_DESC_Exported_FunctionsPrototype USBD_DESC_Exported_FunctionsPrototype + * @brief Public functions declaration. + * @{ + */ + +/* USER CODE BEGIN EXPORTED_FUNCTIONS */ + +/* USER CODE END EXPORTED_FUNCTIONS */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + #ifdef __cplusplus } #endif -#endif /* __USBD_DESC_H */ +#endif /* __USBD_DESC__H__ */ -/** - * @} - */ - -/** -* @} -*/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3.3/Makefile b/Firmware/Board/v3.3/Makefile index 82cdc7d2..7229c4b4 100644 --- a/Firmware/Board/v3.3/Makefile +++ b/Firmware/Board/v3.3/Makefile @@ -1,78 +1,131 @@ - -###################################### -# source -###################################### -C_SOURCES = \ - Middlewares/Third_Party/FreeRTOS/Source/queue.c \ - Middlewares/Third_Party/FreeRTOS/Source/tasks.c \ - Middlewares/Third_Party/FreeRTOS/Source/list.c \ - Middlewares/Third_Party/FreeRTOS/Source/event_groups.c \ - Middlewares/Third_Party/FreeRTOS/Source/croutine.c \ - Middlewares/Third_Party/FreeRTOS/Source/timers.c \ - Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c \ - Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c \ - Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c \ - Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c \ - Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c \ - Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c \ - Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c \ - Src/system_stm32f4xx.c \ - Src/stm32f4xx_it.c \ - Src/stm32f4xx_hal_msp.c \ - Src/stm32f4xx_hal_timebase_TIM.c \ - Src/tim.c \ - Src/gpio.c \ - Src/main.c \ - Src/adc.c \ - Src/freertos.c \ - Src/spi.c \ - Src/can.c \ - Src/usart.c \ - Src/dma.c \ - Src/usbd_conf.c \ - Src/usbd_desc.c \ - Src/usb_device.c \ - Drivers/DRV8301/drv8301.c \ - Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c \ - Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c \ - Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c \ - Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c \ - Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c \ - Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c \ - Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c \ - Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c \ - Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c \ - Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c \ - Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c \ - Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c \ - Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c \ - Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c \ - Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c \ - Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c \ - Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c \ - Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c \ - Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c \ - Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c \ - Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c \ - Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c \ - Src/usbd_cdc_if.c \ - Src/syscalls.c -CPP_SOURCES = -ASM_SOURCES = \ - startup/startup_stm32f405xx.s - -####################################### -# Includes -####################################### -AS_INCLUDES = -C_INCLUDES = -IMiddlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F \ - -IMiddlewares/Third_Party/FreeRTOS/Source/include \ - -IMiddlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS \ - -IDrivers/DRV8301 \ - -IMiddlewares/ST/STM32_USB_Device_Library/Core/Inc \ - -IMiddlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc \ - -IDrivers/STM32F4xx_HAL_Driver/Inc \ - -IDrivers/STM32F4xx_HAL_Driver/Inc/Legacy \ - -IDrivers/CMSIS/Device/ST/STM32F4xx/Include \ - -IDrivers/CMSIS/Include \ - -IInc + +###################################### +# source +###################################### +C_SOURCES = \ + Middlewares/Third_Party/FreeRTOS/Source/queue.c \ + Middlewares/Third_Party/FreeRTOS/Source/tasks.c \ + Middlewares/Third_Party/FreeRTOS/Source/list.c \ + Middlewares/Third_Party/FreeRTOS/Source/event_groups.c \ + Middlewares/Third_Party/FreeRTOS/Source/croutine.c \ + Middlewares/Third_Party/FreeRTOS/Source/timers.c \ + Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c \ + Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c \ + Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c \ + Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c \ + Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c \ + Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c \ + Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c \ + Src/system_stm32f4xx.c \ + Src/stm32f4xx_it.c \ + Src/stm32f4xx_hal_msp.c \ + Src/stm32f4xx_hal_timebase_TIM.c \ + Src/tim.c \ + Src/gpio.c \ + Src/main.c \ + Src/adc.c \ + Src/freertos.c \ + Src/spi.c \ + Src/can.c \ + Src/usart.c \ + Src/dma.c \ + Src/usbd_conf.c \ + Src/usbd_desc.c \ + Src/usb_device.c \ + Drivers/DRV8301/drv8301.c \ + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c \ + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c \ + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c \ + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c \ + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c \ + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c \ + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c \ + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c \ + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c \ + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c \ + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c \ + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c \ + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c \ + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c \ + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c \ + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c \ + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c \ + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c \ + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c \ + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c \ + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c \ + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c \ + Src/usbd_cdc_if.c \ + Src/syscalls.c \ +CPP_SOURCES = \ +ASM_SOURCES = \ + startup/startup_stm32f405xx.s \ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c \ +Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c \ +Src/stm32f4xx_hal_timebase_TIM.c \ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c \ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c \ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c \ +Src/tim.c \ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c \ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c \ +Src/dma.c \ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c \ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c \ +Src/freertos.c \ +Src/main.c \ +Src/usbd_conf.c \ +Src/spi.c \ +Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c \ +Src/usart.c \ +Middlewares/Third_Party/FreeRTOS/Source/croutine.c \ +Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c \ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c \ +Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c \ +Src/usbd_cdc_if.c \ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c \ +Src/adc.c \ +Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c \ +Middlewares/Third_Party/FreeRTOS/Source/list.c \ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c \ +Src/stm32f4xx_hal_msp.c \ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c \ +Src/usbd_desc.c \ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c \ +Src/stm32f4xx_it.c \ +Src/usb_device.c \ +Src/can.c \ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c \ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c \ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c \ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c \ +Middlewares/Third_Party/FreeRTOS/Source/queue.c \ +Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c \ +Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c \ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c \ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c \ +Src/system_stm32f4xx.c \ +Src/gpio.c \ +Middlewares/Third_Party/FreeRTOS/Source/tasks.c \ +Middlewares/Third_Party/FreeRTOS/Source/timers.c \ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c \ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c \ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c \ +Middlewares/Third_Party/FreeRTOS/Source/event_groups.c + +####################################### +# Includes +####################################### +AS_INCLUDES = +C_INCLUDES = -IMiddlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F \ + -IMiddlewares/Third_Party/FreeRTOS/Source/include \ + -IMiddlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS \ + -IDrivers/DRV8301 \ + -IMiddlewares/ST/STM32_USB_Device_Library/Core/Inc \ + -IMiddlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc \ + -IDrivers/STM32F4xx_HAL_Driver/Inc \ + -IDrivers/STM32F4xx_HAL_Driver/Inc/Legacy \ + -IDrivers/CMSIS/Device/ST/STM32F4xx/Include \ + -IDrivers/CMSIS/Include \ + -IInc + Inc \ No newline at end of file diff --git a/Firmware/Board/v3.3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c b/Firmware/Board/v3.3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c index 345b0b0f..b2ca5f16 100644 --- a/Firmware/Board/v3.3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c +++ b/Firmware/Board/v3.3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c @@ -62,8 +62,6 @@ #include "usbd_cdc.h" #include "usbd_desc.h" #include "usbd_ctlreq.h" -#include -#include /** @addtogroup STM32_USB_DEVICE_LIBRARY @@ -671,7 +669,7 @@ static uint8_t USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum) { hcdc->TxState = 0; - osSemaphoreRelease(sem_usb_tx); + return USBD_OK; } else diff --git a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c index 32b7b87c..d0e0fd76 100644 --- a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c +++ b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.c @@ -26,7 +26,7 @@ * *---------------------------------------------------------------------------- * - * Portions Copyright � 2016 STMicroelectronics International N.V. All rights reserved. + * Portions Copyright © 2016 STMicroelectronics International N.V. All rights reserved. * Portions Copyright (c) 2013 ARM LIMITED * All rights reserved. * Redistribution and use in source and binary forms, with or without @@ -57,7 +57,7 @@ ****************************************************************************** * @file cmsis_os.c * @author MCD Application Team - * @date 03-March-2017 + * @date 13-July-2017 * @brief CMSIS-RTOS API implementation for FreeRTOS V9.0.0 ****************************************************************************** * @attention @@ -107,6 +107,7 @@ #define __ASM __asm #define __INLINE __inline #define __STATIC_INLINE static __inline + #include "cmsis_armcc.h" /* @@ -118,7 +119,6 @@ #define __INLINE inline /*!< inline keyword for GNU Compiler */ #define __STATIC_INLINE static inline - #include "cmsis_gcc.h" @@ -819,8 +819,7 @@ osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t * @retval number of available tokens, or -1 in case of incorrect parameters. * @note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. */ -// TODO: submit patch upstream -osStatus osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) { TickType_t ticks; portBASE_TYPE taskWoken = pdFALSE; diff --git a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h index 467cb745..15e25b96 100644 --- a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h +++ b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS/cmsis_os.h @@ -26,7 +26,7 @@ * *---------------------------------------------------------------------------- * - * Portions Copyright � 2016 STMicroelectronics International N.V. All rights reserved. + * Portions Copyright © 2016 STMicroelectronics International N.V. All rights reserved. * Portions Copyright (c) 2013 ARM LIMITED * All rights reserved. * Redistribution and use in source and binary forms, with or without @@ -57,7 +57,7 @@ ****************************************************************************** * @file cmsis_os.h * @author MCD Application Team - * @date 03-March-2017 + * @date 13-July-2017 * @brief Header of cmsis_os.c * A new set of APIs are added in addition to existing ones, these APIs * are specific to FreeRTOS. @@ -719,9 +719,9 @@ osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t /// Wait until a Semaphore token becomes available. /// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. /// \param[in] millisec timeout value or 0 in case of no time-out. -/// \return osOK if the operation succeded. +/// \return number of available tokens, or -1 in case of incorrect parameters. /// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. -osStatus osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); /// Release a Semaphore token. /// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. diff --git a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c index b8df5fd9..b23ecb1c 100644 --- a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c +++ b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c @@ -126,7 +126,7 @@ typedef struct xEventGroupDefinition * wait condition is met if any of the bits set in uxBitsToWait for are also set * in uxCurrentEventBits. */ -static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ); /*-----------------------------------------------------------*/ diff --git a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h index 7331c91c..cab9d59e 100644 --- a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h +++ b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h @@ -185,7 +185,7 @@ typedef TickType_t EventBits_t; * \ingroup EventGroup */ #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) - EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION EventGroupHandle_t xEventGroupCreate( void ) ; #endif /** @@ -238,7 +238,7 @@ typedef TickType_t EventBits_t; */ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) - EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ); #endif /** @@ -333,7 +333,7 @@ typedef TickType_t EventBits_t; * \defgroup xEventGroupWaitBits xEventGroupWaitBits * \ingroup EventGroup */ -EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ); /** * event_groups.h @@ -390,7 +390,7 @@ EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits * \defgroup xEventGroupClearBits xEventGroupClearBits * \ingroup EventGroup */ -EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ); /** * event_groups.h @@ -446,7 +446,7 @@ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBit * \ingroup EventGroup */ #if( configUSE_TRACE_FACILITY == 1 ) - BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; + PRIVILEGED_FUNCTION BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ); #else #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ) #endif @@ -523,7 +523,7 @@ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBit * \defgroup xEventGroupSetBits xEventGroupSetBits * \ingroup EventGroup */ -EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ); /** * event_groups.h @@ -598,7 +598,7 @@ EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_ * \ingroup EventGroup */ #if( configUSE_TRACE_FACILITY == 1 ) - BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + PRIVILEGED_FUNCTION BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ); #else #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ) #endif @@ -727,7 +727,7 @@ EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_ * \defgroup xEventGroupSync xEventGroupSync * \ingroup EventGroup */ -EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ); /** @@ -763,7 +763,7 @@ EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t u * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR * \ingroup EventGroup */ -EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ); /** * event_groups.h @@ -777,15 +777,15 @@ EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEG * * @param xEventGroup The event group being deleted. */ -void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vEventGroupDelete( EventGroupHandle_t xEventGroup ); /* For internal use only. */ -void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION; -void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ); +PRIVILEGED_FUNCTION void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ); #if (configUSE_TRACE_FACILITY == 1) - UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) PRIVILEGED_FUNCTION; + PRIVILEGED_FUNCTION UBaseType_t uxEventGroupGetNumber( void* xEventGroup ); #endif #ifdef __cplusplus diff --git a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/list.h b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/list.h index a080d27d..e552625e 100644 --- a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/list.h +++ b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/list.h @@ -383,7 +383,7 @@ List_t * const pxConstList = ( pxList ); \ * \page vListInitialise vListInitialise * \ingroup LinkedList */ -void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vListInitialise( List_t * const pxList ); /* * Must be called before a list item is used. This sets the list container to @@ -394,7 +394,7 @@ void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION; * \page vListInitialiseItem vListInitialiseItem * \ingroup LinkedList */ -void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vListInitialiseItem( ListItem_t * const pxItem ); /* * Insert a list item into a list. The item will be inserted into the list in @@ -407,7 +407,7 @@ void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION; * \page vListInsert vListInsert * \ingroup LinkedList */ -void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ); /* * Insert a list item into a list. The item will be inserted in a position @@ -428,7 +428,7 @@ void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIV * \page vListInsertEnd vListInsertEnd * \ingroup LinkedList */ -void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ); /* * Remove an item from a list. The list item has a pointer to the list that @@ -443,7 +443,7 @@ void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) P * \page uxListRemove uxListRemove * \ingroup LinkedList */ -UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ); #ifdef __cplusplus } diff --git a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h index 78f5a9ae..1a05c9fd 100644 --- a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h +++ b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h @@ -183,8 +183,19 @@ only for ports that are using the MPU. */ #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */ /* Ensure API functions go in the privileged execution section. */ - #define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions"))) - #define PRIVILEGED_DATA __attribute__((section("privileged_data"))) +#if defined(__ICCARM__) + +#define PRIVILEGED_FUNCTION _Pragma("location= \"privileged_functions\"") +#define PRIVILEGED_DATA _Pragma("location= \"privileged_data\"") +#define PRIVILEGED_INITIALIZED_DATA _Pragma("location= \"privileged_initialized_data\"") + +#else + +#define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions"))) +#define PRIVILEGED_DATA __attribute__((section("privileged_data"))) +#define PRIVILEGED_INITIALIZED_DATA PRIVILEGED_DATA + +#endif #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */ @@ -192,6 +203,7 @@ only for ports that are using the MPU. */ #define PRIVILEGED_FUNCTION #define PRIVILEGED_DATA + #define PRIVILEGED_INITIALIZED_DATA #define portUSING_MPU_WRAPPERS 0 #endif /* portUSING_MPU_WRAPPERS */ diff --git a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h index b9f8be39..00a22086 100644 --- a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h +++ b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h @@ -139,9 +139,9 @@ extern "C" { * */ #if( portUSING_MPU_WRAPPERS == 1 ) - StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION; + PRIVILEGED_FUNCTION StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) ; #else - StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION; + PRIVILEGED_FUNCTION StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) ; #endif /* Used by heap_5.c. */ @@ -162,30 +162,30 @@ typedef struct HeapRegion * terminated by a HeapRegions_t structure that has a size of 0. The region * with the lowest start address must appear first in the array. */ -void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ); /* * Map to the memory management routines required for the port. */ -void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION; -void vPortFree( void *pv ) PRIVILEGED_FUNCTION; -void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION; -size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION; -size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void *pvPortMalloc( size_t xSize ); +PRIVILEGED_FUNCTION void vPortFree( void *pv ); +PRIVILEGED_FUNCTION void vPortInitialiseBlocks( void ); +PRIVILEGED_FUNCTION size_t xPortGetFreeHeapSize( void ); +PRIVILEGED_FUNCTION size_t xPortGetMinimumEverFreeHeapSize( void ); /* * Setup the hardware ready for the scheduler to take control. This generally * sets up a tick interrupt and sets timers for the correct tick frequency. */ -BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xPortStartScheduler( void ); /* * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so * the hardware is left in its original condition after the scheduler stops * executing. */ -void vPortEndScheduler( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vPortEndScheduler( void ); /* * The structures and methods of manipulating the MPU are contained within the @@ -196,7 +196,7 @@ void vPortEndScheduler( void ) PRIVILEGED_FUNCTION; */ #if( portUSING_MPU_WRAPPERS == 1 ) struct xMEMORY_REGION; - void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) PRIVILEGED_FUNCTION; + PRIVILEGED_FUNCTION void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ); #endif #ifdef __cplusplus diff --git a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h index 30be3601..a64640c6 100644 --- a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h +++ b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h @@ -689,7 +689,7 @@ typedef void * QueueSetMemberHandle_t; * \defgroup xQueueSend xQueueSend * \ingroup QueueManagement */ -BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ); /** * queue. h @@ -818,7 +818,7 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQ * \defgroup xQueuePeekFromISR xQueuePeekFromISR * \ingroup QueueManagement */ -BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ); /** * queue. h @@ -1010,7 +1010,7 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIV * \defgroup xQueueReceive xQueueReceive * \ingroup QueueManagement */ -BaseType_t xQueueGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, const BaseType_t xJustPeek ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xQueueGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, const BaseType_t xJustPeek ); /** * queue. h @@ -1025,7 +1025,7 @@ BaseType_t xQueueGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, Ti * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting * \ingroup QueueManagement */ -UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ); /** * queue. h @@ -1042,7 +1042,7 @@ UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNC * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting * \ingroup QueueManagement */ -UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ); /** * queue. h @@ -1056,7 +1056,7 @@ UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNC * \defgroup vQueueDelete vQueueDelete * \ingroup QueueManagement */ -void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vQueueDelete( QueueHandle_t xQueue ); /** * queue. h @@ -1437,8 +1437,8 @@ uint32_t ulVarToSend, ulValReceived; * \defgroup xQueueSendFromISR xQueueSendFromISR * \ingroup QueueManagement */ -BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION; -BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ); +PRIVILEGED_FUNCTION BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ); /** * queue. h @@ -1527,15 +1527,15 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherP * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR * \ingroup QueueManagement */ -BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ); /* * Utilities to query queues that are safe to use from an ISR. These utilities * should be used only from witin an ISR, or within a critical section. */ -BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; -BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; -UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ); +PRIVILEGED_FUNCTION BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ); +PRIVILEGED_FUNCTION UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ); /* * The functions defined above are for passing data to and from tasks. The @@ -1556,18 +1556,18 @@ BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTi * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling * these functions directly. */ -QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; -QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION; -QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION; -QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION; -void* xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ); +PRIVILEGED_FUNCTION QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ); +PRIVILEGED_FUNCTION QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ); +PRIVILEGED_FUNCTION QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ); +PRIVILEGED_FUNCTION void* xQueueGetMutexHolder( QueueHandle_t xSemaphore ); /* * For internal use only. Use xSemaphoreTakeMutexRecursive() or * xSemaphoreGiveMutexRecursive() instead of calling these functions directly. */ -BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; -BaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ); +PRIVILEGED_FUNCTION BaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ); /* * Reset a queue back to its original empty state. The return value is now @@ -1598,7 +1598,7 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) PRIVILEGED_FUNCTION * preferably in ROM/Flash), not on the stack. */ #if( configQUEUE_REGISTRY_SIZE > 0 ) - void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + PRIVILEGED_FUNCTION void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ); /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ #endif /* @@ -1612,7 +1612,7 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) PRIVILEGED_FUNCTION * @param xQueue The handle of the queue being removed from the registry. */ #if( configQUEUE_REGISTRY_SIZE > 0 ) - void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + PRIVILEGED_FUNCTION void vQueueUnregisterQueue( QueueHandle_t xQueue ); #endif /* @@ -1627,7 +1627,7 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) PRIVILEGED_FUNCTION * returned. */ #if( configQUEUE_REGISTRY_SIZE > 0 ) - const char *pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + PRIVILEGED_FUNCTION const char *pcQueueGetName( QueueHandle_t xQueue ); /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ #endif /* @@ -1636,7 +1636,7 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) PRIVILEGED_FUNCTION * RTOS objects that use the queue structure as their base. */ #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) - QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; + PRIVILEGED_FUNCTION QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ); #endif /* @@ -1645,7 +1645,7 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) PRIVILEGED_FUNCTION * RTOS objects that use the queue structure as their base. */ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) - QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; + PRIVILEGED_FUNCTION QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ); #endif /* @@ -1696,7 +1696,7 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) PRIVILEGED_FUNCTION * @return If the queue set is created successfully then a handle to the created * queue set is returned. Otherwise NULL is returned. */ -QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ); /* * Adds a queue or semaphore to a queue set that was previously created by a @@ -1720,7 +1720,7 @@ QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILE * queue set because it is already a member of a different queue set then pdFAIL * is returned. */ -BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ); /* * Removes a queue or semaphore from a queue set. A queue or semaphore can only @@ -1739,7 +1739,7 @@ BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHan * then pdPASS is returned. If the queue was not in the queue set, or the * queue (or semaphore) was not empty, then pdFAIL is returned. */ -BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ); /* * xQueueSelectFromSet() selects from the members of a queue set a queue or @@ -1775,19 +1775,19 @@ BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueS * in the queue set that is available, or NULL if no such queue or semaphore * exists before before the specified block time expires. */ -QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ); /* * A version of xQueueSelectFromSet() that can be used from an ISR. */ -QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ); /* Not public API functions. */ -void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION; -BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION; -void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION; -UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; -uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) ; +PRIVILEGED_FUNCTION BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ); +PRIVILEGED_FUNCTION void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ); +PRIVILEGED_FUNCTION UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ); +PRIVILEGED_FUNCTION uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ); #ifdef __cplusplus diff --git a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/task.h b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/task.h index d0643c09..cfa065eb 100644 --- a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/task.h +++ b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/task.h @@ -357,12 +357,12 @@ is used in assert() statements. */ * \ingroup Tasks */ #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) - BaseType_t xTaskCreate( TaskFunction_t pxTaskCode, + PRIVILEGED_FUNCTION BaseType_t xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, - TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + TaskHandle_t * const pxCreatedTask ); /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ #endif /** @@ -473,13 +473,13 @@ is used in assert() statements. */ * \ingroup Tasks */ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) - TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode, + PRIVILEGED_FUNCTION TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, - StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + StaticTask_t * const pxTaskBuffer ); /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ #endif /* configSUPPORT_STATIC_ALLOCATION */ /** @@ -550,7 +550,7 @@ TaskHandle_t xHandle; * \ingroup Tasks */ #if( portUSING_MPU_WRAPPERS == 1 ) - BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION; + PRIVILEGED_FUNCTION BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ); #endif /** @@ -599,7 +599,7 @@ void vATask( void *pvParameters ) * \defgroup xTaskCreateRestricted xTaskCreateRestricted * \ingroup Tasks */ -void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ); /** * task. h @@ -640,7 +640,7 @@ void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const p * \defgroup vTaskDelete vTaskDelete * \ingroup Tasks */ -void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vTaskDelete( TaskHandle_t xTaskToDelete ); /*----------------------------------------------------------- * TASK CONTROL API @@ -692,7 +692,7 @@ void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION; * \defgroup vTaskDelay vTaskDelay * \ingroup TaskCtrl */ -void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vTaskDelay( const TickType_t xTicksToDelay ); /** * task. h @@ -751,7 +751,7 @@ void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION; * \defgroup vTaskDelayUntil vTaskDelayUntil * \ingroup TaskCtrl */ -void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ); /** * task. h @@ -776,7 +776,7 @@ void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xT * \defgroup xTaskAbortDelay xTaskAbortDelay * \ingroup TaskCtrl */ -BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xTaskAbortDelay( TaskHandle_t xTask ); /** * task. h @@ -823,7 +823,7 @@ BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; * \defgroup uxTaskPriorityGet uxTaskPriorityGet * \ingroup TaskCtrl */ -UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask ); /** * task. h @@ -831,7 +831,7 @@ UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; * * A version of uxTaskPriorityGet() that can be used from an ISR. */ -UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask ); /** * task. h @@ -849,7 +849,7 @@ UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; * state of the task might change between the function being called, and the * functions return value being tested by the calling task. */ -eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION eTaskState eTaskGetState( TaskHandle_t xTask ); /** * task. h @@ -905,7 +905,7 @@ eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; * \defgroup vTaskGetInfo vTaskGetInfo * \ingroup TaskCtrl */ -void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ); /** * task. h @@ -947,7 +947,7 @@ void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xG * \defgroup vTaskPrioritySet vTaskPrioritySet * \ingroup TaskCtrl */ -void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ); /** * task. h @@ -998,7 +998,7 @@ void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGE * \defgroup vTaskSuspend vTaskSuspend * \ingroup TaskCtrl */ -void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vTaskSuspend( TaskHandle_t xTaskToSuspend ); /** * task. h @@ -1047,7 +1047,7 @@ void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION; * \defgroup vTaskResume vTaskResume * \ingroup TaskCtrl */ -void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vTaskResume( TaskHandle_t xTaskToResume ); /** * task. h @@ -1076,7 +1076,7 @@ void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION; * \defgroup vTaskResumeFromISR vTaskResumeFromISR * \ingroup TaskCtrl */ -BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ); /*----------------------------------------------------------- * SCHEDULER CONTROL @@ -1109,7 +1109,7 @@ BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION; * \defgroup vTaskStartScheduler vTaskStartScheduler * \ingroup SchedulerControl */ -void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vTaskStartScheduler( void ); /** * task. h @@ -1165,7 +1165,7 @@ void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION; * \defgroup vTaskEndScheduler vTaskEndScheduler * \ingroup SchedulerControl */ -void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vTaskEndScheduler( void ); /** * task. h @@ -1216,7 +1216,7 @@ void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION; * \defgroup vTaskSuspendAll vTaskSuspendAll * \ingroup SchedulerControl */ -void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vTaskSuspendAll( void ); /** * task. h @@ -1270,7 +1270,7 @@ void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION; * \defgroup xTaskResumeAll xTaskResumeAll * \ingroup SchedulerControl */ -BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xTaskResumeAll( void ); /*----------------------------------------------------------- * TASK UTILITIES @@ -1285,7 +1285,7 @@ BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION; * \defgroup xTaskGetTickCount xTaskGetTickCount * \ingroup TaskUtils */ -TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION TickType_t xTaskGetTickCount( void ); /** * task. h @@ -1301,7 +1301,7 @@ TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION; * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR * \ingroup TaskUtils */ -TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION TickType_t xTaskGetTickCountFromISR( void ); /** * task. h @@ -1315,7 +1315,7 @@ TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION; * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks * \ingroup TaskUtils */ -UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION UBaseType_t uxTaskGetNumberOfTasks( void ); /** * task. h @@ -1328,7 +1328,7 @@ UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION; * \defgroup pcTaskGetName pcTaskGetName * \ingroup TaskUtils */ -char *pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +PRIVILEGED_FUNCTION char *pcTaskGetName( TaskHandle_t xTaskToQuery ); /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ /** * task. h @@ -1344,7 +1344,7 @@ char *pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e9 * \defgroup pcTaskGetHandle pcTaskGetHandle * \ingroup TaskUtils */ -TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +PRIVILEGED_FUNCTION TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ); /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ /** * task.h @@ -1365,7 +1365,7 @@ TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /* * actual spaces on the stack rather than bytes) since the task referenced by * xTask was created. */ -UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ); /* When using trace macros it is sometimes necessary to include task.h before FreeRTOS.h. When this is done TaskHookFunction_t will not yet have been defined, @@ -1383,7 +1383,7 @@ constant. */ * Passing xTask as NULL has the effect of setting the calling tasks hook * function. */ - void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION; + PRIVILEGED_FUNCTION void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ); /** * task.h @@ -1391,7 +1391,7 @@ constant. */ * * Returns the pxHookFunction value assigned to the task xTask. */ - TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + PRIVILEGED_FUNCTION TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ); #endif /* configUSE_APPLICATION_TASK_TAG ==1 */ #endif /* ifdef configUSE_APPLICATION_TASK_TAG */ @@ -1402,8 +1402,8 @@ constant. */ kernel does not use the pointers itself, so the application writer can use the pointers for any purpose they wish. The following two functions are used to set and query a pointer respectively. */ - void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) PRIVILEGED_FUNCTION; - void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) PRIVILEGED_FUNCTION; + PRIVILEGED_FUNCTION void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ); + PRIVILEGED_FUNCTION void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ); #endif @@ -1418,7 +1418,7 @@ constant. */ * wants. The return value is the value returned by the task hook function * registered by the user. */ -BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ); /** * xTaskGetIdleTaskHandle() is only available if @@ -1427,7 +1427,7 @@ BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) * Simply returns the handle of the idle task. It is not valid to call * xTaskGetIdleTaskHandle() before the scheduler has been started. */ -TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION TaskHandle_t xTaskGetIdleTaskHandle( void ); /** * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for @@ -1526,7 +1526,7 @@ TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION; } */ -UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ); /** * task. h @@ -1573,7 +1573,7 @@ UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const * \defgroup vTaskList vTaskList * \ingroup TaskUtils */ -void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +PRIVILEGED_FUNCTION void vTaskList( char * pcWriteBuffer ); /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ /** * task. h @@ -1627,7 +1627,7 @@ void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unquali * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats * \ingroup TaskUtils */ -void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +PRIVILEGED_FUNCTION void vTaskGetRunTimeStats( char *pcWriteBuffer ); /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ /** * task. h @@ -1708,7 +1708,7 @@ void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e9 * \defgroup xTaskNotify xTaskNotify * \ingroup TaskNotifications */ -BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ); #define xTaskNotify( xTaskToNotify, ulValue, eAction ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL ) #define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) ) @@ -1799,7 +1799,7 @@ BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNo * \defgroup xTaskNotify xTaskNotify * \ingroup TaskNotifications */ -BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ); #define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) ) #define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) ) @@ -1876,7 +1876,7 @@ BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulVal * \defgroup xTaskNotifyWait xTaskNotifyWait * \ingroup TaskNotifications */ -BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ); /** * task. h @@ -1977,7 +1977,7 @@ BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClea * \defgroup xTaskNotifyWait xTaskNotifyWait * \ingroup TaskNotifications */ -void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken ); /** * task. h @@ -2046,7 +2046,7 @@ void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPri * \defgroup ulTaskNotifyTake ulTaskNotifyTake * \ingroup TaskNotifications */ -uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ); /** * task. h @@ -2083,7 +2083,7 @@ BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask ); * + Time slicing is in use and there is a task of equal priority to the * currently running task. */ -BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xTaskIncrementTick( void ); /* * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN @@ -2116,8 +2116,8 @@ BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION; * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time * period. */ -void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; -void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ); +PRIVILEGED_FUNCTION void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ); /* * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN @@ -2130,7 +2130,7 @@ void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xIte * indefinitely, whereas vTaskPlaceOnEventList() does. * */ -void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ); /* * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN @@ -2156,8 +2156,8 @@ void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTi * @return pdTRUE if the task being removed has a higher priority than the task * making the call, otherwise pdFALSE. */ -BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION; -BaseType_t xTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ); +PRIVILEGED_FUNCTION BaseType_t xTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ); /* * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY @@ -2167,64 +2167,64 @@ BaseType_t xTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, cons * Sets the pointer to the current TCB to the TCB of the highest priority task * that is ready to run. */ -void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vTaskSwitchContext( void ); /* * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE. THEY ARE USED BY * THE EVENT BITS MODULE. */ -TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION TickType_t uxTaskResetEventItemValue( void ); /* * Return the handle of the calling task. */ -TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION TaskHandle_t xTaskGetCurrentTaskHandle( void ); /* * Capture the current time status for future reference. */ -void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ); /* * Compare the time status now with that previously captured to see if the * timeout has expired. */ -BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ); /* * Shortcut used by the queue implementation to prevent unnecessary call to * taskYIELD(); */ -void vTaskMissedYield( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vTaskMissedYield( void ); /* * Returns the scheduler state as taskSCHEDULER_RUNNING, * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED. */ -BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xTaskGetSchedulerState( void ); /* * Raises the priority of the mutex holder to that of the calling task should * the mutex holder have a priority less than the calling task. */ -void vTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vTaskPriorityInherit( TaskHandle_t const pxMutexHolder ); /* * Set the priority of a task back to its proper priority in the case that it * inherited a higher priority while it was holding a semaphore. */ -BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ); /* * Get the uxTCBNumber assigned to the task referenced by the xTask parameter. */ -UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ); /* * Set the uxTaskNumber of the task referenced by the xTask parameter to * uxHandle. */ -void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ); /* * Only available when configUSE_TICKLESS_IDLE is set to 1. @@ -2234,7 +2234,7 @@ void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVIL * to date with the actual execution time by being skipped forward by a time * equal to the idle period. */ -void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vTaskStepTick( const TickType_t xTicksToJump ); /* * Only avilable when configUSE_TICKLESS_IDLE is set to 1. @@ -2250,13 +2250,13 @@ void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION; * critical section between the timer being stopped and the sleep mode being * entered to ensure it is ok to proceed into the sleep mode. */ -eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION eSleepModeStatus eTaskConfirmSleepModeStatus( void ); /* * For internal use only. Increment the mutex held count when a mutex is * taken and return the handle of the task that has taken the mutex. */ -void *pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void *pvTaskIncrementMutexHeldCount( void ); #ifdef __cplusplus } diff --git a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h index 798c955b..2f430f37 100644 --- a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h +++ b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h @@ -266,11 +266,11 @@ typedef void (*PendedFunction_t)( void *, uint32_t ); * @endverbatim */ #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) - TimerHandle_t xTimerCreate( const char * const pcTimerName, + PRIVILEGED_FUNCTION TimerHandle_t xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, - TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + TimerCallbackFunction_t pxCallbackFunction ); /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ #endif /** @@ -396,12 +396,12 @@ typedef void (*PendedFunction_t)( void *, uint32_t ); * @endverbatim */ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) - TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, + PRIVILEGED_FUNCTION TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, - StaticTimer_t *pxTimerBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + StaticTimer_t *pxTimerBuffer ); /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ #endif /* configSUPPORT_STATIC_ALLOCATION */ /** @@ -424,7 +424,7 @@ typedef void (*PendedFunction_t)( void *, uint32_t ); * * See the xTimerCreate() API function example usage scenario. */ -void *pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void *pvTimerGetTimerID( const TimerHandle_t xTimer ); /** * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ); @@ -445,7 +445,7 @@ void *pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; * * See the xTimerCreate() API function example usage scenario. */ -void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ); /** * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ); @@ -482,7 +482,7 @@ void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) PRIVILEGED_FUNCTION * } * @endverbatim */ -BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ); /** * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ); @@ -490,7 +490,7 @@ BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; * Simply returns the handle of the timer service/daemon task. It it not valid * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started. */ -TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ); /** * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait ); @@ -1225,7 +1225,7 @@ TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION; * } * @endverbatim */ -BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken ); /** * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, @@ -1259,7 +1259,7 @@ BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void * timer daemon task, otherwise pdFALSE is returned. * */ -BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ); /** * const char * const pcTimerGetName( TimerHandle_t xTimer ); @@ -1270,7 +1270,7 @@ BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvPar * * @return The name assigned to the timer specified by the xTimer parameter. */ -const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +PRIVILEGED_FUNCTION const char * pcTimerGetName( TimerHandle_t xTimer ); /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ /** * TickType_t xTimerGetPeriod( TimerHandle_t xTimer ); @@ -1281,7 +1281,7 @@ const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint * * @return The period of the timer in ticks. */ -TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION TickType_t xTimerGetPeriod( TimerHandle_t xTimer ); /** * TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ); @@ -1296,14 +1296,14 @@ TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; * will next expire is returned. If the timer is not running then the return * value is undefined. */ -TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ); /* * Functions beyond this part are not part of the public API and are intended * for use by the kernel only. */ -BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION; -BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION BaseType_t xTimerCreateTimerTask( void ); +PRIVILEGED_FUNCTION BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ); #ifdef __cplusplus } diff --git a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/queue.c b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/queue.c index ce623bec..056d4be1 100644 --- a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/queue.c +++ b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/queue.c @@ -205,46 +205,46 @@ typedef xQUEUE Queue_t; * to indicate that a task may require unblocking. When the queue in unlocked * these lock counts are inspected, and the appropriate action taken. */ -static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION static void prvUnlockQueue( Queue_t * const pxQueue ); /* * Uses a critical section to determine if there is any data in a queue. * * @return pdTRUE if the queue contains no items, otherwise pdFALSE. */ -static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ); /* * Uses a critical section to determine if there is any space in a queue. * * @return pdTRUE if there is no space, otherwise pdFALSE; */ -static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ); /* * Copies an item into the queue, either at the front of the queue or the * back of the queue. */ -static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ); /* * Copies an item out of a queue. */ -static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ); #if ( configUSE_QUEUE_SETS == 1 ) /* * Checks to see if a queue is a member of a queue set, and if so, notifies * the queue set that the queue contains data. */ - static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION; + PRIVILEGED_FUNCTION static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition ); #endif /* * Called after a Queue_t structure has been allocated either statically or * dynamically to fill in the structure's members. */ -static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ); /* * Mutexes are a special type of queue. When a mutex is created, first the @@ -252,7 +252,7 @@ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseT * as a mutex. */ #if( configUSE_MUTEXES == 1 ) - static void prvInitialiseMutex( Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION; + PRIVILEGED_FUNCTION static void prvInitialiseMutex( Queue_t *pxNewQueue ); #endif /*-----------------------------------------------------------*/ diff --git a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/tasks.c b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/tasks.c index 6c261a65..5c68c6a2 100644 --- a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/tasks.c +++ b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/tasks.c @@ -369,7 +369,7 @@ typedef tskTCB TCB_t; /*lint -e956 A manual analysis and inspection has been used to determine which static variables must be declared volatile. */ -PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL; +PRIVILEGED_INITIALIZED_DATA TCB_t * volatile pxCurrentTCB = NULL; /* Lists for ready and blocked tasks. --------------------*/ PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ];/*< Prioritised ready tasks. */ @@ -382,7 +382,7 @@ PRIVILEGED_DATA static List_t xPendingReadyList; /*< Tasks that have been r #if( INCLUDE_vTaskDelete == 1 ) PRIVILEGED_DATA static List_t xTasksWaitingTermination; /*< Tasks that have been deleted - but their memory not yet freed. */ - PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U; + PRIVILEGED_INITIALIZED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U; #endif @@ -393,16 +393,16 @@ PRIVILEGED_DATA static List_t xPendingReadyList; /*< Tasks that have been r #endif /* Other file private variables. --------------------------------*/ -PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks = ( UBaseType_t ) 0U; -PRIVILEGED_DATA static volatile TickType_t xTickCount = ( TickType_t ) 0U; -PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority = tskIDLE_PRIORITY; -PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning = pdFALSE; -PRIVILEGED_DATA static volatile UBaseType_t uxPendedTicks = ( UBaseType_t ) 0U; -PRIVILEGED_DATA static volatile BaseType_t xYieldPending = pdFALSE; -PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows = ( BaseType_t ) 0; -PRIVILEGED_DATA static UBaseType_t uxTaskNumber = ( UBaseType_t ) 0U; -PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime = ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */ -PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle = NULL; /*< Holds the handle of the idle task. The idle task is created automatically when the scheduler is started. */ +PRIVILEGED_INITIALIZED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks = ( UBaseType_t ) 0U; +PRIVILEGED_INITIALIZED_DATA static volatile TickType_t xTickCount = ( TickType_t ) 0U; +PRIVILEGED_INITIALIZED_DATA static volatile UBaseType_t uxTopReadyPriority = tskIDLE_PRIORITY; +PRIVILEGED_INITIALIZED_DATA static volatile BaseType_t xSchedulerRunning = pdFALSE; +PRIVILEGED_INITIALIZED_DATA static volatile UBaseType_t uxPendedTicks = ( UBaseType_t ) 0U; +PRIVILEGED_INITIALIZED_DATA static volatile BaseType_t xYieldPending = pdFALSE; +PRIVILEGED_INITIALIZED_DATA static volatile BaseType_t xNumOfOverflows = ( BaseType_t ) 0; +PRIVILEGED_INITIALIZED_DATA static UBaseType_t uxTaskNumber = ( UBaseType_t ) 0U; +PRIVILEGED_INITIALIZED_DATA static volatile TickType_t xNextTaskUnblockTime = ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */ +PRIVILEGED_INITIALIZED_DATA static TaskHandle_t xIdleTaskHandle = NULL; /*< Holds the handle of the idle task. The idle task is created automatically when the scheduler is started. */ /* Context switches are held pending while the scheduler is suspended. Also, interrupts must not manipulate the xStateListItem of a TCB, or any of the @@ -412,12 +412,12 @@ moves the task's event list item into the xPendingReadyList, ready for the kernel to move the task from the pending ready list into the real ready list when the scheduler is unsuspended. The pending ready list itself can only be accessed from a critical section. */ -PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended = ( UBaseType_t ) pdFALSE; +PRIVILEGED_INITIALIZED_DATA static volatile UBaseType_t uxSchedulerSuspended = ( UBaseType_t ) pdFALSE; #if ( configGENERATE_RUN_TIME_STATS == 1 ) - PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL; /*< Holds the value of a timer/counter the last time a task was switched in. */ - PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL; /*< Holds the total amount of execution time as defined by the run time counter clock. */ + PRIVILEGED_INITIALIZED_DATA static uint32_t ulTaskSwitchedInTime = 0UL; /*< Holds the value of a timer/counter the last time a task was switched in. */ + PRIVILEGED_INITIALIZED_DATA static uint32_t ulTotalRunTime = 0UL; /*< Holds the total amount of execution time as defined by the run time counter clock. */ #endif @@ -446,14 +446,14 @@ PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended = ( UBaseType_t * is in any other state. */ #if ( INCLUDE_vTaskSuspend == 1 ) - static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + PRIVILEGED_FUNCTION static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ); #endif /* INCLUDE_vTaskSuspend */ /* * Utility to ready all the lists used by the scheduler. This is called * automatically upon the creation of the first task. */ -static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION static void prvInitialiseTaskLists( void ); /* * The idle task, which as all tasks is implemented as a never ending loop. @@ -477,7 +477,7 @@ static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ); */ #if ( INCLUDE_vTaskDelete == 1 ) - static void prvDeleteTCB( TCB_t *pxTCB ) PRIVILEGED_FUNCTION; + PRIVILEGED_FUNCTION static void prvDeleteTCB( TCB_t *pxTCB ); #endif @@ -486,13 +486,13 @@ static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ); * in the list of tasks waiting to be deleted. If so the task is cleaned up * and its TCB deleted. */ -static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION static void prvCheckTasksWaitingTermination( void ); /* * The currently executing task is entering the Blocked state. Add the task to * either the current or the overflow delayed task list. */ -static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ); /* * Fills an TaskStatus_t structure with information on each task that is @@ -504,7 +504,7 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseT */ #if ( configUSE_TRACE_FACILITY == 1 ) - static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ) PRIVILEGED_FUNCTION; + PRIVILEGED_FUNCTION static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ); #endif @@ -514,7 +514,7 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseT */ #if ( INCLUDE_xTaskGetHandle == 1 ) - static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] ) PRIVILEGED_FUNCTION; + PRIVILEGED_FUNCTION static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] ); #endif @@ -525,7 +525,7 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseT */ #if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) - static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION; + PRIVILEGED_FUNCTION static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ); #endif @@ -540,7 +540,7 @@ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseT */ #if ( configUSE_TICKLESS_IDLE != 0 ) - static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION; + PRIVILEGED_FUNCTION static TickType_t prvGetExpectedIdleTime( void ); #endif @@ -556,7 +556,7 @@ static void prvResetNextTaskUnblockTime( void ); * Helper function used to pad task names with spaces when printing out * human readable tables of task information. */ - static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName ) PRIVILEGED_FUNCTION; + PRIVILEGED_FUNCTION static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName ); #endif @@ -564,20 +564,20 @@ static void prvResetNextTaskUnblockTime( void ); * Called after a Task_t structure has been allocated either statically or * dynamically to fill in the structure's members. */ -static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, +PRIVILEGED_FUNCTION static void prvInitialiseNewTask( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, TCB_t *pxNewTCB, - const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const MemoryRegion_t * const xRegions ); /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ /* * Called after a new task has been created and initialised to place the task * under the control of the scheduler. */ -static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ); /*-----------------------------------------------------------*/ diff --git a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/timers.c b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/timers.c index d4a821a2..44cb477e 100644 --- a/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/timers.c +++ b/Firmware/Board/v3.3/Middlewares/Third_Party/FreeRTOS/Source/timers.c @@ -170,8 +170,8 @@ PRIVILEGED_DATA static List_t *pxCurrentTimerList; PRIVILEGED_DATA static List_t *pxOverflowTimerList; /* A queue that is used to send commands to the timer service task. */ -PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL; -PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL; +PRIVILEGED_INITIALIZED_DATA static QueueHandle_t xTimerQueue = NULL; +PRIVILEGED_INITIALIZED_DATA static TaskHandle_t xTimerTaskHandle = NULL; /*lint +e956 */ @@ -191,44 +191,44 @@ PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL; * Initialise the infrastructure used by the timer service task if it has not * been initialised already. */ -static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION static void prvCheckForValidListAndQueue( void ); /* * The timer service task (daemon). Timer functionality is controlled by this * task. Other tasks communicate with the timer service task using the * xTimerQueue queue. */ -static void prvTimerTask( void *pvParameters ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION static void prvTimerTask( void *pvParameters ); /* * Called by the timer service task to interpret and process a command it * received on the timer queue. */ -static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION static void prvProcessReceivedCommands( void ); /* * Insert the timer into either xActiveTimerList1, or xActiveTimerList2, * depending on if the expire time causes a timer counter overflow. */ -static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ); /* * An active timer has reached its expire time. Reload the timer if it is an * auto reload timer, then call its callback. */ -static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ); /* * The tick count has overflowed. Switch the timer lists after ensuring the * current timer list does not still reference some timers. */ -static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION static void prvSwitchTimerLists( void ); /* * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE * if a tick count overflow occurred since prvSampleTimeNow() was last called. */ -static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ); /* * If the timer list contains any active timers then return the expire time of @@ -236,24 +236,24 @@ static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched * timer list does not contain any timers then return 0 and set *pxListWasEmpty * to pdTRUE. */ -static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ); /* * If a timer has expired, process it. Otherwise, block the timer service task * until either a timer does expire or a command is received. */ -static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION; +PRIVILEGED_FUNCTION static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ); /* * Called after a Timer_t structure has been allocated either statically or * dynamically to fill in the structure's members. */ -static void prvInitialiseNewTimer( const char * const pcTimerName, +PRIVILEGED_FUNCTION static void prvInitialiseNewTimer( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, - Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + Timer_t *pxNewTimer ); /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ /*-----------------------------------------------------------*/ BaseType_t xTimerCreateTimerTask( void ) @@ -660,7 +660,7 @@ TickType_t xNextExpireTime; static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) { TickType_t xTimeNow; -PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ +PRIVILEGED_INITIALIZED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ xTimeNow = xTaskGetTickCount(); diff --git a/Firmware/Board/v3.3/Odrive.ioc b/Firmware/Board/v3.3/Odrive.ioc index b27ffb67..186d9db7 100644 --- a/Firmware/Board/v3.3/Odrive.ioc +++ b/Firmware/Board/v3.3/Odrive.ioc @@ -410,7 +410,7 @@ ProjectManager.BackupPrevious=false ProjectManager.CompilerOptimize=2 ProjectManager.ComputerToolchain=false ProjectManager.CoupleFile=true -ProjectManager.CustomerFirmwarePackage= +ProjectManager.CustomerFirmwarePackage=/home/samuel/STM32Cube/Repository/STM32Cube_FW_F4_V1.19.0 ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32F405RGTx diff --git a/Firmware/Board/v3.3/Src/adc.c b/Firmware/Board/v3.3/Src/adc.c index c7f132ab..6d0db380 100644 --- a/Firmware/Board/v3.3/Src/adc.c +++ b/Firmware/Board/v3.3/Src/adc.c @@ -10,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/Firmware/Board/v3.3/Src/can.c b/Firmware/Board/v3.3/Src/can.c index 57f7bd96..202a23ce 100644 --- a/Firmware/Board/v3.3/Src/can.c +++ b/Firmware/Board/v3.3/Src/can.c @@ -10,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -65,15 +65,15 @@ void MX_CAN1_Init(void) hcan1.Instance = CAN1; hcan1.Init.Prescaler = 16; hcan1.Init.Mode = CAN_MODE_NORMAL; - hcan1.Init.SJW = CAN_SJW_1TQ; - hcan1.Init.BS1 = CAN_BS1_1TQ; - hcan1.Init.BS2 = CAN_BS2_1TQ; - hcan1.Init.TTCM = DISABLE; - hcan1.Init.ABOM = DISABLE; - hcan1.Init.AWUM = DISABLE; - hcan1.Init.NART = DISABLE; - hcan1.Init.RFLM = DISABLE; - hcan1.Init.TXFP = DISABLE; + hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; + hcan1.Init.TimeSeg1 = CAN_BS1_1TQ; + hcan1.Init.TimeSeg2 = CAN_BS2_1TQ; + hcan1.Init.TimeTriggeredMode = DISABLE; + hcan1.Init.AutoBusOff = DISABLE; + hcan1.Init.AutoWakeUp = DISABLE; + hcan1.Init.AutoRetransmission = DISABLE; + hcan1.Init.ReceiveFifoLocked = DISABLE; + hcan1.Init.TransmitFifoPriority = DISABLE; if (HAL_CAN_Init(&hcan1) != HAL_OK) { _Error_Handler(__FILE__, __LINE__); diff --git a/Firmware/Board/v3.3/Src/dma.c b/Firmware/Board/v3.3/Src/dma.c index 322d04ab..a725a585 100644 --- a/Firmware/Board/v3.3/Src/dma.c +++ b/Firmware/Board/v3.3/Src/dma.c @@ -10,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/Firmware/Board/v3.3/Src/freertos.c b/Firmware/Board/v3.3/Src/freertos.c index 9e136bd6..bd169893 100644 --- a/Firmware/Board/v3.3/Src/freertos.c +++ b/Firmware/Board/v3.3/Src/freertos.c @@ -9,7 +9,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/Firmware/Board/v3.3/Src/gpio.c b/Firmware/Board/v3.3/Src/gpio.c index 693ab7b1..02b7d691 100644 --- a/Firmware/Board/v3.3/Src/gpio.c +++ b/Firmware/Board/v3.3/Src/gpio.c @@ -10,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -71,8 +71,6 @@ * Output * EVENT_OUT * EXTI - PA0-WKUP ------> SharedStack_PA0 - PA1 ------> SharedStack_PA1 */ void MX_GPIO_Init(void) { @@ -102,22 +100,6 @@ void MX_GPIO_Init(void) GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = GPIO_1_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_PULLDOWN; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF8_UART4; - HAL_GPIO_Init(GPIO_1_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = GPIO_2_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF8_UART4; - HAL_GPIO_Init(GPIO_2_GPIO_Port, &GPIO_InitStruct); - /*Configure GPIO pin : PtPin */ GPIO_InitStruct.Pin = GPIO_3_Pin; GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; diff --git a/Firmware/Board/v3.3/Src/main.c b/Firmware/Board/v3.3/Src/main.c index cb7e0490..5262d553 100644 --- a/Firmware/Board/v3.3/Src/main.c +++ b/Firmware/Board/v3.3/Src/main.c @@ -1,7 +1,7 @@ /** ****************************************************************************** - * File Name : main.c - * Description : Main program body + * @file : main.c + * @brief : Main program body ****************************************************************************** * This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and @@ -9,7 +9,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -82,9 +82,13 @@ void MX_FREERTOS_Init(void); /* USER CODE END 0 */ +/** + * @brief The application entry point. + * + * @retval None + */ int main(void) { - /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ @@ -119,7 +123,6 @@ int main(void) MX_ADC3_Init(); MX_TIM2_Init(); MX_UART4_Init(); - /* USER CODE BEGIN 2 */ //Required to use OC4 for ADC triggering. @@ -149,8 +152,10 @@ int main(void) } -/** System Clock Configuration -*/ +/** + * @brief System Clock Configuration + * @retval None + */ void SystemClock_Config(void) { @@ -218,58 +223,56 @@ void SystemClock_Config(void) */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { -/* USER CODE BEGIN Callback 0 */ + /* USER CODE BEGIN Callback 0 */ -/* USER CODE END Callback 0 */ + /* USER CODE END Callback 0 */ if (htim->Instance == TIM14) { HAL_IncTick(); } -/* USER CODE BEGIN Callback 1 */ + /* USER CODE BEGIN Callback 1 */ -/* USER CODE END Callback 1 */ + /* USER CODE END Callback 1 */ } /** * @brief This function is executed in case of error occurrence. - * @param None + * @param file: The file name as string. + * @param line: The line in file as a number. * @retval None */ -void _Error_Handler(char * file, int line) +void _Error_Handler(char *file, int line) { /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ while(1) { } - /* USER CODE END Error_Handler_Debug */ + /* USER CODE END Error_Handler_Debug */ } -#ifdef USE_FULL_ASSERT - +#ifdef USE_FULL_ASSERT /** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ void assert_failed(uint8_t* file, uint32_t line) -{ +{ /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ /* USER CODE END 6 */ - } - -#endif +#endif /* USE_FULL_ASSERT */ /** * @} - */ + */ /** * @} -*/ + */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3.3/Src/spi.c b/Firmware/Board/v3.3/Src/spi.c index 1eb86a50..87b2a018 100644 --- a/Firmware/Board/v3.3/Src/spi.c +++ b/Firmware/Board/v3.3/Src/spi.c @@ -10,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/Firmware/Board/v3.3/Src/stm32f4xx_hal_msp.c b/Firmware/Board/v3.3/Src/stm32f4xx_hal_msp.c index 00b4229b..fac7e341 100644 --- a/Firmware/Board/v3.3/Src/stm32f4xx_hal_msp.c +++ b/Firmware/Board/v3.3/Src/stm32f4xx_hal_msp.c @@ -10,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/Firmware/Board/v3.3/Src/stm32f4xx_hal_timebase_TIM.c b/Firmware/Board/v3.3/Src/stm32f4xx_hal_timebase_TIM.c index a74e4773..94afb902 100644 --- a/Firmware/Board/v3.3/Src/stm32f4xx_hal_timebase_TIM.c +++ b/Firmware/Board/v3.3/Src/stm32f4xx_hal_timebase_TIM.c @@ -9,7 +9,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/Firmware/Board/v3.3/Src/stm32f4xx_it.c b/Firmware/Board/v3.3/Src/stm32f4xx_it.c index 064e1036..07d3bb9d 100644 --- a/Firmware/Board/v3.3/Src/stm32f4xx_it.c +++ b/Firmware/Board/v3.3/Src/stm32f4xx_it.c @@ -4,7 +4,7 @@ * @brief Interrupt Service Routines. ****************************************************************************** * - * COPYRIGHT(c) 2017 STMicroelectronics + * COPYRIGHT(c) 2018 STMicroelectronics * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -84,6 +84,8 @@ void HardFault_Handler(void) /* USER CODE END HardFault_IRQn 0 */ while (1) { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ } /* USER CODE BEGIN HardFault_IRQn 1 */ @@ -100,6 +102,8 @@ void MemManage_Handler(void) /* USER CODE END MemoryManagement_IRQn 0 */ while (1) { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ } /* USER CODE BEGIN MemoryManagement_IRQn 1 */ @@ -116,6 +120,8 @@ void BusFault_Handler(void) /* USER CODE END BusFault_IRQn 0 */ while (1) { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ } /* USER CODE BEGIN BusFault_IRQn 1 */ @@ -132,6 +138,8 @@ void UsageFault_Handler(void) /* USER CODE END UsageFault_IRQn 0 */ while (1) { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ } /* USER CODE BEGIN UsageFault_IRQn 1 */ diff --git a/Firmware/Board/v3.3/Src/tim.c b/Firmware/Board/v3.3/Src/tim.c index 0589c3b0..5a63b6df 100644 --- a/Firmware/Board/v3.3/Src/tim.c +++ b/Firmware/Board/v3.3/Src/tim.c @@ -10,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/Firmware/Board/v3.3/Src/usart.c b/Firmware/Board/v3.3/Src/usart.c index 1704d012..52a869db 100644 --- a/Firmware/Board/v3.3/Src/usart.c +++ b/Firmware/Board/v3.3/Src/usart.c @@ -10,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/Firmware/Board/v3.3/Src/usb_device.c b/Firmware/Board/v3.3/Src/usb_device.c index 2c987f26..2fc3750c 100644 --- a/Firmware/Board/v3.3/Src/usb_device.c +++ b/Firmware/Board/v3.3/Src/usb_device.c @@ -1,8 +1,8 @@ /** ****************************************************************************** - * @file : USB_DEVICE + * @file : usb_device.c * @version : v1.0_Cube - * @brief : This file implements the USB Device + * @brief : This file implements the USB Device ****************************************************************************** * This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and @@ -10,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -45,7 +45,7 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** -*/ + */ /* Includes ------------------------------------------------------------------*/ @@ -55,17 +55,48 @@ #include "usbd_cdc.h" #include "usbd_cdc_if.h" -/* USB Device Core handle declaration */ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN PV */ +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE END PV */ + +/* USER CODE BEGIN PFP */ +/* Private function prototypes -----------------------------------------------*/ + +/* USER CODE END PFP */ + +/* USB Device Core handle declaration. */ USBD_HandleTypeDef hUsbDeviceFS; -/* init function */ +/* + * -- Insert your variables declaration here -- + */ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* + * -- Insert your external function declaration here -- + */ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** + * Init USB device Library, add supported class and start the library + * @retval None + */ void MX_USB_DEVICE_Init(void) { /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */ /* USER CODE END USB_DEVICE_Init_PreTreatment */ - /* Init Device Library,Add Supported Class and Start the library*/ + /* Init Device Library, add supported class and start the library. */ USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS); USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC); @@ -78,6 +109,7 @@ void MX_USB_DEVICE_Init(void) /* USER CODE END USB_DEVICE_Init_PostTreatment */ } + /** * @} */ diff --git a/Firmware/Board/v3.3/Src/usbd_cdc_if.c b/Firmware/Board/v3.3/Src/usbd_cdc_if.c index b38385f7..a7c0bd8c 100644 --- a/Firmware/Board/v3.3/Src/usbd_cdc_if.c +++ b/Firmware/Board/v3.3/Src/usbd_cdc_if.c @@ -1,7 +1,8 @@ /** ****************************************************************************** * @file : usbd_cdc_if.c - * @brief : + * @version : v1.0_Cube + * @brief : Usb device for Virtual Com Port. ****************************************************************************** * This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and @@ -9,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -44,10 +45,11 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** -*/ + */ /* Includes ------------------------------------------------------------------*/ #include "usbd_cdc_if.h" + /* USER CODE BEGIN INCLUDE */ #include "cmsis_os.h" #include "freertos_vars.h" @@ -56,135 +58,153 @@ #include /* USER CODE END INCLUDE */ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE END PV */ + /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY + * @brief Usb device library. * @{ */ -/** @defgroup USBD_CDC - * @brief usbd core module +/** @addtogroup USBD_CDC_IF * @{ - */ + */ -/** @defgroup USBD_CDC_Private_TypesDefinitions +/** @defgroup USBD_CDC_IF_Private_TypesDefinitions USBD_CDC_IF_Private_TypesDefinitions + * @brief Private types. * @{ - */ + */ + /* USER CODE BEGIN PRIVATE_TYPES */ -/* USER CODE END PRIVATE_TYPES */ +/* USER CODE END PRIVATE_TYPES */ + /** * @} - */ + */ -/** @defgroup USBD_CDC_Private_Defines +/** @defgroup USBD_CDC_IF_Private_Defines USBD_CDC_IF_Private_Defines + * @brief Private defines. * @{ - */ + */ + /* USER CODE BEGIN PRIVATE_DEFINES */ /* USER CODE END PRIVATE_DEFINES */ + /** * @} - */ + */ -/** @defgroup USBD_CDC_Private_Macros +/** @defgroup USBD_CDC_IF_Private_Macros USBD_CDC_IF_Private_Macros + * @brief Private macros. * @{ - */ + */ + /* USER CODE BEGIN PRIVATE_MACRO */ /* USER CODE END PRIVATE_MACRO */ /** * @} - */ - -/** @defgroup USBD_CDC_Private_Variables + */ + +/** @defgroup USBD_CDC_IF_Private_Variables USBD_CDC_IF_Private_Variables + * @brief Private variables. * @{ */ /* Create buffer for reception and transmission */ /* It's up to user to redefine and/or remove those define */ -/* Received Data over USB are stored in this buffer */ -uint8_t UserRxBufferFS[USB_RX_DATA_SIZE]; +/** Received data over USB are stored in this buffer */ +uint8_t UserRxBufferFS[APP_RX_DATA_SIZE]; -/* Send Data over USB CDC are stored in this buffer */ -uint8_t UserTxBufferFS[USB_TX_DATA_SIZE]; +/** Data to send over USB CDC are stored in this buffer */ +uint8_t UserTxBufferFS[APP_TX_DATA_SIZE]; /* USER CODE BEGIN PRIVATE_VARIABLES */ /* USER CODE END PRIVATE_VARIABLES */ /** * @} - */ - -/** @defgroup USBD_CDC_IF_Exported_Variables + */ + +/** @defgroup USBD_CDC_IF_Exported_Variables USBD_CDC_IF_Exported_Variables + * @brief Public variables. * @{ - */ - extern USBD_HandleTypeDef hUsbDeviceFS; + */ + +extern USBD_HandleTypeDef hUsbDeviceFS; + /* USER CODE BEGIN EXPORTED_VARIABLES */ /* USER CODE END EXPORTED_VARIABLES */ /** * @} - */ - -/** @defgroup USBD_CDC_Private_FunctionPrototypes + */ + +/** @defgroup USBD_CDC_IF_Private_FunctionPrototypes USBD_CDC_IF_Private_FunctionPrototypes + * @brief Private functions declaration. * @{ */ -static int8_t CDC_Init_FS (void); -static int8_t CDC_DeInit_FS (void); -static int8_t CDC_Control_FS (uint8_t cmd, uint8_t* pbuf, uint16_t length); -static int8_t CDC_Receive_FS (uint8_t* pbuf, uint32_t *Len); + +static int8_t CDC_Init_FS(void); +static int8_t CDC_DeInit_FS(void); +static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length); +static int8_t CDC_Receive_FS(uint8_t* pbuf, uint32_t *Len); /* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */ /* USER CODE END PRIVATE_FUNCTIONS_DECLARATION */ /** * @} - */ - -USBD_CDC_ItfTypeDef USBD_Interface_fops_FS = + */ + +USBD_CDC_ItfTypeDef USBD_Interface_fops_FS = { CDC_Init_FS, CDC_DeInit_FS, - CDC_Control_FS, + CDC_Control_FS, CDC_Receive_FS }; /* Private functions ---------------------------------------------------------*/ /** - * @brief CDC_Init_FS - * Initializes the CDC media low layer over the FS USB IP - * @param None - * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + * @brief Initializes the CDC media low layer over the FS USB IP + * @retval USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_Init_FS(void) -{ - /* USER CODE BEGIN 3 */ +{ + /* USER CODE BEGIN 3 */ /* Set Application Buffers */ USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, 0); USBD_CDC_SetRxBuffer(&hUsbDeviceFS, UserRxBufferFS); return (USBD_OK); - /* USER CODE END 3 */ + /* USER CODE END 3 */ } /** - * @brief CDC_DeInit_FS - * DeInitializes the CDC media low layer - * @param None - * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL + * @brief DeInitializes the CDC media low layer + * @retval USBD_OK if all operations are OK else USBD_FAIL */ static int8_t CDC_DeInit_FS(void) { - /* USER CODE BEGIN 4 */ + /* USER CODE BEGIN 4 */ return (USBD_OK); - /* USER CODE END 4 */ + /* USER CODE END 4 */ } /** - * @brief CDC_Control_FS - * Manage the CDC class requests - * @param cmd: Command code + * @brief Manage the CDC class requests + * @param cmd: Command code * @param pbuf: Buffer containing command data (request parameters) * @param length: Number of data to be sent (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL */ -static int8_t CDC_Control_FS (uint8_t cmd, uint8_t* pbuf, uint16_t length) -{ +static int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length) +{ /* USER CODE BEGIN 5 */ switch (cmd) { @@ -256,21 +276,20 @@ static int8_t CDC_Control_FS (uint8_t cmd, uint8_t* pbuf, uint16_t length) } /** - * @brief CDC_Receive_FS - * Data received over USB OUT endpoint are sent over CDC interface + * @brief Data received over USB OUT endpoint are sent over CDC interface * through this function. - * + * * @note - * This function will block any OUT packet reception on USB endpoint + * This function will block any OUT packet reception on USB endpoint * untill exiting this function. If you exit this function before transfer - * is complete on CDC interface (ie. using DMA controller) it will result + * is complete on CDC interface (ie. using DMA controller) it will result * in receiving more data while previous ones are still not sent. - * + * * @param Buf: Buffer of data to be received * @param Len: Number of data received (in bytes) * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL */ -static int8_t CDC_Receive_FS (uint8_t* Buf, uint32_t *Len) +static int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len) { /* USER CODE BEGIN 6 */ @@ -278,24 +297,24 @@ static int8_t CDC_Receive_FS (uint8_t* Buf, uint32_t *Len) osSemaphoreRelease(sem_usb_rx); return (USBD_OK); - /* USER CODE END 6 */ + /* USER CODE END 6 */ } /** * @brief CDC_Transmit_FS - * Data send over USB IN endpoint are sent over CDC interface - * through this function. + * Data to send over USB IN endpoint are sent over CDC interface + * through this function. * @note - * - * - * @param Buf: Buffer of data to be send - * @param Len: Number of data to be send (in bytes) - * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY + * + * + * @param Buf: Buffer of data to be sent + * @param Len: Number of data to be sent (in bytes) + * @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY */ uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) { uint8_t result = USBD_OK; - /* USER CODE BEGIN 7 */ + /* USER CODE BEGIN 7 */ //Check length if (Len > USB_TX_DATA_SIZE) @@ -309,7 +328,7 @@ uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) // Update Len USBD_CDC_SetTxBuffer(&hUsbDeviceFS, UserTxBufferFS, Len); result = USBD_CDC_TransmitPacket(&hUsbDeviceFS); - /* USER CODE END 7 */ + /* USER CODE END 7 */ return result; } @@ -318,11 +337,10 @@ uint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len) /** * @} - */ + */ /** * @} - */ + */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/Firmware/Board/v3.3/Src/usbd_conf.c b/Firmware/Board/v3.3/Src/usbd_conf.c index bfbd4c23..f3eb88a9 100644 --- a/Firmware/Board/v3.3/Src/usbd_conf.c +++ b/Firmware/Board/v3.3/Src/usbd_conf.c @@ -10,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -45,13 +45,27 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** -*/ + */ + /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" #include "stm32f4xx_hal.h" #include "usbd_def.h" #include "usbd_core.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE END PV */ + PCD_HandleTypeDef hpcd_USB_OTG_FS; void _Error_Handler(char * file, int line); @@ -61,8 +75,13 @@ void SystemClock_Config(void); /* USER CODE BEGIN 0 */ /* USER CODE END 0 */ +/* USER CODE BEGIN PFP */ /* Private function prototypes -----------------------------------------------*/ + +/* USER CODE END PFP */ + /* Private functions ---------------------------------------------------------*/ + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ @@ -141,7 +160,7 @@ void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) /** * @brief Data Out stage callback. * @param hpcd: PCD handle - * @param epnum: Endpoint Number + * @param epnum: Endpoint number * @retval None */ void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -150,9 +169,9 @@ void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) } /** - * @brief Data In stage callback.. + * @brief Data In stage callback. * @param hpcd: PCD handle - * @param epnum: Endpoint Number + * @param epnum: Endpoint number * @retval None */ void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -179,23 +198,23 @@ void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) { USBD_SpeedTypeDef speed = USBD_SPEED_FULL; - /*Set USB Current Speed*/ + /* Set USB current speed. */ switch (hpcd->Init.speed) { case PCD_SPEED_HIGH: speed = USBD_SPEED_HIGH; break; case PCD_SPEED_FULL: - speed = USBD_SPEED_FULL; + speed = USBD_SPEED_FULL; break; default: - speed = USBD_SPEED_FULL; + speed = USBD_SPEED_FULL; break; } - USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); + USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed); - /*Reset Device*/ + /* Reset Device. */ USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData); } @@ -206,11 +225,11 @@ void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) * @retval None */ void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) -{ - /* Inform USB library that core enters in suspend Mode */ +{ + /* Inform USB library that core enters in suspend Mode. */ USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData); __HAL_PCD_GATE_PHYCLOCK(hpcd); - /*Enter in STOP mode */ + /* Enter in STOP mode. */ /* USER CODE BEGIN 2 */ if (hpcd->Init.low_power_enable) { @@ -222,7 +241,7 @@ void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) /** * @brief Resume callback. - When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it) + * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it) * @param hpcd: PCD handle * @retval None */ @@ -231,13 +250,12 @@ void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) /* USER CODE BEGIN 3 */ /* USER CODE END 3 */ USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData); - } /** - * @brief ISOC Out Incomplete callback. + * @brief ISOOUTIncomplete callback. * @param hpcd: PCD handle - * @param epnum: Endpoint Number + * @param epnum: Endpoint number * @retval None */ void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -246,9 +264,9 @@ void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) } /** - * @brief ISOC In Incomplete callback. + * @brief ISOINIncomplete callback. * @param hpcd: PCD handle - * @param epnum: Endpoint Number + * @param epnum: Endpoint number * @retval None */ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) @@ -279,18 +297,19 @@ void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) /******************************************************************************* LL Driver Interface (USB Device Library --> PCD) *******************************************************************************/ + /** - * @brief Initializes the Low Level portion of the Device driver. + * @brief Initializes the low level portion of the device driver. * @param pdev: Device handle - * @retval USBD Status + * @retval USBD status */ -USBD_StatusTypeDef USBD_LL_Init (USBD_HandleTypeDef *pdev) -{ - /* Init USB_IP */ +USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev) +{ + /* Init USB Ip. */ if (pdev->id == DEVICE_FS) { - /* Link The driver to the stack */ + /* Link the driver to the stack. */ hpcd_USB_OTG_FS.pData = pdev; - pdev->pData = &hpcd_USB_OTG_FS; + pdev->pData = &hpcd_USB_OTG_FS; hpcd_USB_OTG_FS.Instance = USB_OTG_FS; hpcd_USB_OTG_FS.Init.dev_endpoints = 4; @@ -316,17 +335,17 @@ USBD_StatusTypeDef USBD_LL_Init (USBD_HandleTypeDef *pdev) } /** - * @brief De-Initializes the Low Level portion of the Device driver. + * @brief De-Initializes the low level portion of the device driver. * @param pdev: Device handle - * @retval USBD Status + * @retval USBD status */ -USBD_StatusTypeDef USBD_LL_DeInit (USBD_HandleTypeDef *pdev) +USBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev) { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; - + hal_status = HAL_PCD_DeInit(pdev->pData); - + switch (hal_status) { case HAL_OK : usb_status = USBD_OK; @@ -348,11 +367,11 @@ USBD_StatusTypeDef USBD_LL_DeInit (USBD_HandleTypeDef *pdev) } /** - * @brief Starts the Low Level portion of the Device driver. + * @brief Starts the low level portion of the device driver. * @param pdev: Device handle - * @retval USBD Status + * @retval USBD status */ -USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) +USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; @@ -376,21 +395,21 @@ USBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev) usb_status = USBD_FAIL; break; } - return usb_status; + return usb_status; } /** - * @brief Stops the Low Level portion of the Device driver. + * @brief Stops the low level portion of the device driver. * @param pdev: Device handle - * @retval USBD Status + * @retval USBD status */ -USBD_StatusTypeDef USBD_LL_Stop (USBD_HandleTypeDef *pdev) +USBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev) { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; - + hal_status = HAL_PCD_Stop(pdev->pData); - + switch (hal_status) { case HAL_OK : usb_status = USBD_OK; @@ -408,31 +427,24 @@ USBD_StatusTypeDef USBD_LL_Stop (USBD_HandleTypeDef *pdev) usb_status = USBD_FAIL; break; } - return usb_status; + return usb_status; } /** - * @brief Opens an endpoint of the Low Level Driver. + * @brief Opens an endpoint of the low level driver. * @param pdev: Device handle - * @param ep_addr: Endpoint Number - * @param ep_type: Endpoint Type - * @param ep_mps: Endpoint Max Packet Size - * @retval USBD Status + * @param ep_addr: Endpoint number + * @param ep_type: Endpoint type + * @param ep_mps: Endpoint max packet size + * @retval USBD status */ -USBD_StatusTypeDef USBD_LL_OpenEP (USBD_HandleTypeDef *pdev, - uint8_t ep_addr, - uint8_t ep_type, - uint16_t ep_mps) +USBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps) { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; - hal_status = HAL_PCD_EP_Open(pdev->pData, - ep_addr, - ep_mps, - ep_type); - - + hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type); + switch (hal_status) { case HAL_OK : usb_status = USBD_OK; @@ -450,16 +462,16 @@ USBD_StatusTypeDef USBD_LL_OpenEP (USBD_HandleTypeDef *pdev, usb_status = USBD_FAIL; break; } - return usb_status; + return usb_status; } /** - * @brief Closes an endpoint of the Low Level Driver. + * @brief Closes an endpoint of the low level driver. * @param pdev: Device handle - * @param ep_addr: Endpoint Number - * @retval USBD Status + * @param ep_addr: Endpoint number + * @retval USBD status */ -USBD_StatusTypeDef USBD_LL_CloseEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr) +USBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; @@ -489,10 +501,10 @@ USBD_StatusTypeDef USBD_LL_CloseEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr) /** * @brief Flushes an endpoint of the Low Level Driver. * @param pdev: Device handle - * @param ep_addr: Endpoint Number - * @retval USBD Status + * @param ep_addr: Endpoint number + * @retval USBD status */ -USBD_StatusTypeDef USBD_LL_FlushEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr) +USBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; @@ -522,16 +534,16 @@ USBD_StatusTypeDef USBD_LL_FlushEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr) /** * @brief Sets a Stall condition on an endpoint of the Low Level Driver. * @param pdev: Device handle - * @param ep_addr: Endpoint Number - * @retval USBD Status + * @param ep_addr: Endpoint number + * @retval USBD status */ -USBD_StatusTypeDef USBD_LL_StallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr) +USBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr); - + switch (hal_status) { case HAL_OK : usb_status = USBD_OK; @@ -555,10 +567,10 @@ USBD_StatusTypeDef USBD_LL_StallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr) /** * @brief Clears a Stall condition on an endpoint of the Low Level Driver. * @param pdev: Device handle - * @param ep_addr: Endpoint Number - * @retval USBD Status + * @param ep_addr: Endpoint number + * @retval USBD status */ -USBD_StatusTypeDef USBD_LL_ClearStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr) +USBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; @@ -588,10 +600,10 @@ USBD_StatusTypeDef USBD_LL_ClearStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_a /** * @brief Returns Stall condition. * @param pdev: Device handle - * @param ep_addr: Endpoint Number + * @param ep_addr: Endpoint number * @retval Stall (1: Yes, 0: No) */ -uint8_t USBD_LL_IsStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr) +uint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData; @@ -604,13 +616,14 @@ uint8_t USBD_LL_IsStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr) return hpcd->OUT_ep[ep_addr & 0x7F].is_stall; } } + /** * @brief Assigns a USB address to the device. * @param pdev: Device handle - * @param ep_addr: Endpoint Number - * @retval USBD Status + * @param dev_addr: Device address + * @retval USBD status */ -USBD_StatusTypeDef USBD_LL_SetUSBAddress (USBD_HandleTypeDef *pdev, uint8_t dev_addr) +USBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr) { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; @@ -640,15 +653,12 @@ USBD_StatusTypeDef USBD_LL_SetUSBAddress (USBD_HandleTypeDef *pdev, uint8_t dev /** * @brief Transmits data over an endpoint. * @param pdev: Device handle - * @param ep_addr: Endpoint Number + * @param ep_addr: Endpoint number * @param pbuf: Pointer to data to be sent * @param size: Data size - * @retval USBD Status + * @retval USBD status */ -USBD_StatusTypeDef USBD_LL_Transmit (USBD_HandleTypeDef *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint16_t size) +USBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size) { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; @@ -678,15 +688,12 @@ USBD_StatusTypeDef USBD_LL_Transmit (USBD_HandleTypeDef *pdev, /** * @brief Prepares an endpoint for reception. * @param pdev: Device handle - * @param ep_addr: Endpoint Number + * @param ep_addr: Endpoint number * @param pbuf: Pointer to data to be received * @param size: Data size - * @retval USBD Status + * @retval USBD status */ -USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint16_t size) +USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size) { HAL_StatusTypeDef hal_status = HAL_OK; USBD_StatusTypeDef usb_status = USBD_OK; @@ -716,58 +723,60 @@ USBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, /** * @brief Returns the last transfered packet size. * @param pdev: Device handle - * @param ep_addr: Endpoint Number + * @param ep_addr: Endpoint number * @retval Recived Data Size */ -uint32_t USBD_LL_GetRxDataSize (USBD_HandleTypeDef *pdev, uint8_t ep_addr) +uint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr) { return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr); } #if (USBD_LPM_ENABLED == 1) /** - * @brief HAL_PCDEx_LPM_Callback : Send LPM message to user layer + * @brief Send LPM message to user layer * @param hpcd: PCD handle * @param msg: LPM message - * @retval HAL status + * @retval None */ void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) { - switch ( msg) + switch (msg) { case PCD_LPM_L0_ACTIVE: if (hpcd->Init.low_power_enable) { SystemClock_Config(); - /* Reset SLEEPDEEP bit of Cortex System Control Register */ + /* Reset SLEEPDEEP bit of Cortex System Control Register. */ SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); } __HAL_PCD_UNGATE_PHYCLOCK(hpcd); - USBD_LL_Resume(hpcd->pData); + USBD_LL_Resume(hpcd->pData); break; case PCD_LPM_L1_ACTIVE: __HAL_PCD_GATE_PHYCLOCK(hpcd); USBD_LL_Suspend(hpcd->pData); - /*Enter in STOP mode */ + /* Enter in STOP mode. */ if (hpcd->Init.low_power_enable) { - /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register */ + /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */ SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); - } + } break; } } -#endif +#endif /* (USBD_LPM_ENABLED == 1) */ + /** * @brief Delays routine for the USB Device Library. * @param Delay: Delay in ms * @retval None */ -void USBD_LL_Delay (uint32_t Delay) +void USBD_LL_Delay(uint32_t Delay) { - HAL_Delay(Delay); + HAL_Delay(Delay); } + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3.3/Src/usbd_desc.c b/Firmware/Board/v3.3/Src/usbd_desc.c index 82703697..b9c7bd06 100644 --- a/Firmware/Board/v3.3/Src/usbd_desc.c +++ b/Firmware/Board/v3.3/Src/usbd_desc.c @@ -2,7 +2,7 @@ ****************************************************************************** * @file : usbd_desc.c * @version : v1.0_Cube - * @brief : This file implements the USB Device descriptors + * @brief : This file implements the USB device descriptors. ****************************************************************************** * This notice applies to any and all portions of this file * that are not between comment pairs USER CODE BEGIN and @@ -10,7 +10,7 @@ * inserted by the user or by software development tools * are owned by their respective copyright owners. * - * Copyright (c) 2017 STMicroelectronics International N.V. + * Copyright (c) 2018 STMicroelectronics International N.V. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -45,321 +45,361 @@ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** -*/ + */ /* Includes ------------------------------------------------------------------*/ #include "usbd_core.h" #include "usbd_desc.h" #include "usbd_conf.h" +/* USER CODE BEGIN INCLUDE */ + +/* USER CODE END INCLUDE */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE END PV */ + /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY * @{ */ -/** @defgroup USBD_DESC - * @brief USBD descriptors module - * @{ - */ - -/** @defgroup USBD_DESC_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_DESC_Private_Defines +/** @addtogroup USBD_DESC * @{ */ -#define USBD_VID 0x1209 -#define USBD_LANGID_STRING 1033 -#define USBD_MANUFACTURER_STRING "ODrive Robotics" -#define USBD_PID_FS 0x0D32 -#define USBD_PRODUCT_XSTR(s) USBD_PRODUCT_STR(s) -#define USBD_PRODUCT_STR(s) #s -#define USBD_PRODUCT_STRING_FS ODrive version HW_VERSION_MAJOR.HW_VERSION_MINOR -#define USBD_SERIALNUMBER_STRING_FS "000000000001" -#define USBD_CONFIGURATION_STRING_FS "CDC Config" -#define USBD_INTERFACE_STRING_FS "CDC Interface" + +/** @defgroup USBD_DESC_Private_TypesDefinitions USBD_DESC_Private_TypesDefinitions + * @brief Private types. + * @{ + */ + +/* USER CODE BEGIN PRIVATE_TYPES */ + +/* USER CODE END PRIVATE_TYPES */ + +/** + * @} + */ + +/** @defgroup USBD_DESC_Private_Defines USBD_DESC_Private_Defines + * @brief Private defines. + * @{ + */ + +#define USBD_VID 0x1209 +#define USBD_LANGID_STRING 1033 +#define USBD_MANUFACTURER_STRING "ODrive Robotics" +#define USBD_PID_FS 0x0D33 +#define USBD_PRODUCT_STRING_FS "ODrive v3.3" +#define USBD_SERIALNUMBER_STRING_FS "000000000001" +#define USBD_CONFIGURATION_STRING_FS "CDC Config" +#define USBD_INTERFACE_STRING_FS "CDC Interface" #define USB_SIZ_BOS_DESC 0x0C +/* USER CODE BEGIN PRIVATE_DEFINES */ + +/* USER CODE END PRIVATE_DEFINES */ + +/** + * @} + */ + /* USER CODE BEGIN 0 */ -/* USER CODE END 0*/ +/* USER CODE END 0 */ + +/** @defgroup USBD_DESC_Private_Macros USBD_DESC_Private_Macros + * @brief Private macros. + * @{ + */ + +/* USER CODE BEGIN PRIVATE_MACRO */ + +/* USER CODE END PRIVATE_MACRO */ + /** * @} - */ + */ -/** @defgroup USBD_DESC_Private_Macros +/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes + * @brief Private functions declaration. * @{ - */ -/** - * @} - */ + */ -/** @defgroup USBD_DESC_Private_Variables - * @{ - */ -uint8_t * USBD_FS_DeviceDescriptor( USBD_SpeedTypeDef speed , uint16_t *length); -uint8_t * USBD_FS_LangIDStrDescriptor( USBD_SpeedTypeDef speed , uint16_t *length); -uint8_t * USBD_FS_ManufacturerStrDescriptor ( USBD_SpeedTypeDef speed , uint16_t *length); -uint8_t * USBD_FS_ProductStrDescriptor ( USBD_SpeedTypeDef speed , uint16_t *length); -uint8_t * USBD_FS_SerialStrDescriptor( USBD_SpeedTypeDef speed , uint16_t *length); -uint8_t * USBD_FS_ConfigStrDescriptor( USBD_SpeedTypeDef speed , uint16_t *length); -uint8_t * USBD_FS_InterfaceStrDescriptor( USBD_SpeedTypeDef speed , uint16_t *length); +uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); #ifdef USB_SUPPORT_USER_STRING_DESC -uint8_t * USBD_FS_USRStringDesc (USBD_SpeedTypeDef speed, uint8_t idx , uint16_t *length); -#endif /* USB_SUPPORT_USER_STRING_DESC */ +uint8_t * USBD_FS_USRStringDesc(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length); +#endif /* USB_SUPPORT_USER_STRING_DESC */ #if (USBD_LPM_ENABLED == 1) -uint8_t *USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed , uint16_t *length); -#endif +uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length); +#endif /* (USBD_LPM_ENABLED == 1) */ + +/** + * @} + */ + +/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables + * @brief Private variables. + * @{ + */ USBD_DescriptorsTypeDef FS_Desc = { - USBD_FS_DeviceDescriptor, - USBD_FS_LangIDStrDescriptor, - USBD_FS_ManufacturerStrDescriptor, - USBD_FS_ProductStrDescriptor, - USBD_FS_SerialStrDescriptor, - USBD_FS_ConfigStrDescriptor, - USBD_FS_InterfaceStrDescriptor, -#if (USBD_LPM_ENABLED == 1) - USBD_FS_USR_BOSDescriptor, -#endif + USBD_FS_DeviceDescriptor +, USBD_FS_LangIDStrDescriptor +, USBD_FS_ManufacturerStrDescriptor +, USBD_FS_ProductStrDescriptor +, USBD_FS_SerialStrDescriptor +, USBD_FS_ConfigStrDescriptor +, USBD_FS_InterfaceStrDescriptor +#if (USBD_LPM_ENABLED == 1) +, USBD_FS_USR_BOSDescriptor +#endif /* (USBD_LPM_ENABLED == 1) */ }; -#if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 -#endif -/* USB Standard Device Descriptor */ +#if defined ( __ICCARM__ ) /* IAR Compiler */ + #pragma data_alignment=4 +#endif /* defined ( __ICCARM__ ) */ +/** USB standard device descriptor. */ __ALIGN_BEGIN uint8_t USBD_FS_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END = - { - 0x12, /*bLength */ - USB_DESC_TYPE_DEVICE, /*bDescriptorType*/ +{ + 0x12, /*bLength */ + USB_DESC_TYPE_DEVICE, /*bDescriptorType*/ #if (USBD_LPM_ENABLED == 1) - 0x01, /*bcdUSB */ /* changed to USB version 2.01 - in order to support LPM L1 suspend - resume test of USBCV3.0*/ -#else - 0x00, /* bcdUSB */ -#endif - 0x02, - 0x02, /*bDeviceClass*/ - 0x02, /*bDeviceSubClass*/ - 0x00, /*bDeviceProtocol*/ - USB_MAX_EP0_SIZE, /*bMaxPacketSize*/ - LOBYTE(USBD_VID), /*idVendor*/ - HIBYTE(USBD_VID), /*idVendor*/ - LOBYTE(USBD_PID_FS), /*idVendor*/ - HIBYTE(USBD_PID_FS), /*idVendor*/ - 0x00, /*bcdDevice rel. 2.00*/ - 0x02, - USBD_IDX_MFC_STR, /*Index of manufacturer string*/ - USBD_IDX_PRODUCT_STR, /*Index of product string*/ - USBD_IDX_SERIAL_STR, /*Index of serial number string*/ - USBD_MAX_NUM_CONFIGURATION /*bNumConfigurations*/ - } ; + 0x01, /*bcdUSB */ /* changed to USB version 2.01 + in order to support LPM L1 suspend + resume test of USBCV3.0*/ +#else + 0x00, /*bcdUSB */ +#endif /* (USBD_LPM_ENABLED == 1) */ + 0x02, + 0x02, /*bDeviceClass*/ + 0x02, /*bDeviceSubClass*/ + 0x00, /*bDeviceProtocol*/ + USB_MAX_EP0_SIZE, /*bMaxPacketSize*/ + LOBYTE(USBD_VID), /*idVendor*/ + HIBYTE(USBD_VID), /*idVendor*/ + LOBYTE(USBD_PID_FS), /*idProduct*/ + HIBYTE(USBD_PID_FS), /*idProduct*/ + 0x00, /*bcdDevice rel. 2.00*/ + 0x02, + USBD_IDX_MFC_STR, /*Index of manufacturer string*/ + USBD_IDX_PRODUCT_STR, /*Index of product string*/ + USBD_IDX_SERIAL_STR, /*Index of serial number string*/ + USBD_MAX_NUM_CONFIGURATION /*bNumConfigurations*/ +}; + /* USB_DeviceDescriptor */ -/* BOS descriptor */ +/** BOS descriptor. */ #if (USBD_LPM_ENABLED == 1) -#if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 -#endif -__ALIGN_BEGIN uint8_t USBD_FS_BOSDesc[USB_SIZ_BOS_DESC] __ALIGN_END = +#if defined ( __ICCARM__ ) /* IAR Compiler */ + #pragma data_alignment=4 +#endif /* defined ( __ICCARM__ ) */ +__ALIGN_BEGIN uint8_t USBD_FS_BOSDesc[USB_SIZ_BOS_DESC] __ALIGN_END = { 0x5, USB_DESC_TYPE_BOS, 0xC, 0x0, - 0x1, /* 1 device capability */ + 0x1, /* 1 device capability*/ /* device capability*/ 0x7, USB_DEVICE_CAPABITY_TYPE, 0x2, - 0x2, /*LPM capability bit set */ + 0x2, /* LPM capability bit set*/ 0x0, 0x0, 0x0 }; -#endif +#endif /* (USBD_LPM_ENABLED == 1) */ -#if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 -#endif +/** + * @} + */ -/* USB Standard Device Descriptor */ +/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables + * @brief Private variables. + * @{ + */ + +#if defined ( __ICCARM__ ) /* IAR Compiler */ + #pragma data_alignment=4 +#endif /* defined ( __ICCARM__ ) */ + +/** USB lang indentifier descriptor. */ __ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END = { - USB_LEN_LANGID_STR_DESC, - USB_DESC_TYPE_STRING, + USB_LEN_LANGID_STR_DESC, + USB_DESC_TYPE_STRING, LOBYTE(USBD_LANGID_STRING), - HIBYTE(USBD_LANGID_STRING), + HIBYTE(USBD_LANGID_STRING) }; -#if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 -#endif +#if defined ( __ICCARM__ ) /* IAR Compiler */ + #pragma data_alignment=4 +#endif /* defined ( __ICCARM__ ) */ +/* Internal string descriptor. */ __ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END; + /** * @} - */ + */ -/** @defgroup USBD_DESC_Private_FunctionPrototypes +/** @defgroup USBD_DESC_Private_Functions USBD_DESC_Private_Functions + * @brief Private functions. * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_DESC_Private_Functions - * @{ - */ + */ /** -* @brief USBD_FS_DeviceDescriptor -* return the device descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_FS_DeviceDescriptor( USBD_SpeedTypeDef speed , uint16_t *length) + * @brief Return the device descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { *length = sizeof(USBD_FS_DeviceDesc); return USBD_FS_DeviceDesc; } /** -* @brief USBD_FS_LangIDStrDescriptor -* return the LangID string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_FS_LangIDStrDescriptor( USBD_SpeedTypeDef speed , uint16_t *length) + * @brief Return the LangID string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - *length = sizeof(USBD_LangIDDesc); + *length = sizeof(USBD_LangIDDesc); return USBD_LangIDDesc; } /** -* @brief USBD_FS_ProductStrDescriptor -* return the product string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_FS_ProductStrDescriptor( USBD_SpeedTypeDef speed , uint16_t *length) + * @brief Return the product string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { if(speed == 0) { - USBD_GetString ((uint8_t *)USBD_PRODUCT_XSTR(USBD_PRODUCT_STRING_FS), USBD_StrDesc, length); + USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); } else { - USBD_GetString ((uint8_t *)USBD_PRODUCT_XSTR(USBD_PRODUCT_STRING_FS), USBD_StrDesc, length); + USBD_GetString((uint8_t *)USBD_PRODUCT_STRING_FS, USBD_StrDesc, length); } return USBD_StrDesc; } /** -* @brief USBD_FS_ManufacturerStrDescriptor -* return the manufacturer string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_FS_ManufacturerStrDescriptor( USBD_SpeedTypeDef speed , uint16_t *length) + * @brief Return the manufacturer string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - USBD_GetString ((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); + USBD_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_StrDesc, length); return USBD_StrDesc; } /** -* @brief USBD_FS_SerialStrDescriptor -* return the serial number string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_FS_SerialStrDescriptor( USBD_SpeedTypeDef speed , uint16_t *length) + * @brief Return the serial number string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - if(speed == USBD_SPEED_HIGH) + if(speed == USBD_SPEED_HIGH) { - USBD_GetString ((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); + USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); } else { - USBD_GetString ((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); + USBD_GetString((uint8_t *)USBD_SERIALNUMBER_STRING_FS, USBD_StrDesc, length); } return USBD_StrDesc; } /** -* @brief USBD_FS_ConfigStrDescriptor -* return the configuration string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_FS_ConfigStrDescriptor( USBD_SpeedTypeDef speed , uint16_t *length) + * @brief Return the configuration string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { - if(speed == USBD_SPEED_HIGH) + if(speed == USBD_SPEED_HIGH) { - USBD_GetString ((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); + USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); } else { - USBD_GetString ((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); + USBD_GetString((uint8_t *)USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length); } - return USBD_StrDesc; + return USBD_StrDesc; } /** -* @brief USBD_HS_InterfaceStrDescriptor -* return the interface string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_FS_InterfaceStrDescriptor( USBD_SpeedTypeDef speed , uint16_t *length) + * @brief Return the interface string descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer + */ +uint8_t * USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { if(speed == 0) { - USBD_GetString ((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); + USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); } else { - USBD_GetString ((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); + USBD_GetString((uint8_t *)USBD_INTERFACE_STRING_FS, USBD_StrDesc, length); } - return USBD_StrDesc; + return USBD_StrDesc; } + #if (USBD_LPM_ENABLED == 1) /** - * @brief USBD_FS_USR_BOSDescriptor - * return the BOS descriptor - * @param speed : current device speed - * @param length : pointer to data length variable - * @retval pointer to descriptor buffer + * @brief Return the BOS descriptor + * @param speed : Current device speed + * @param length : Pointer to data length variable + * @retval Pointer to descriptor buffer */ -uint8_t *USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed , uint16_t *length) +uint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length) { *length = sizeof(USBD_FS_BOSDesc); return (uint8_t*)USBD_FS_BOSDesc; } -#endif -/** - * @} - */ +#endif /* (USBD_LPM_ENABLED == 1) */ /** * @} - */ + */ /** * @} - */ + */ + +/** + * @} + */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/Firmware/Board/v3.3/startup/startup_stm32f405xx.s b/Firmware/Board/v3.3/startup_stm32f405xx.s similarity index 99% rename from Firmware/Board/v3.3/startup/startup_stm32f405xx.s rename to Firmware/Board/v3.3/startup_stm32f405xx.s index 3876f1c1..ea0e76a9 100644 --- a/Firmware/Board/v3.3/startup/startup_stm32f405xx.s +++ b/Firmware/Board/v3.3/startup_stm32f405xx.s @@ -2,8 +2,6 @@ ****************************************************************************** * @file startup_stm32f405xx.s * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief STM32F405xx Devices vector table for GCC based toolchains. * This module performs: * - Set the initial SP