From 484da5515005149f9ec068dc056aad34d2f0d43d Mon Sep 17 00:00:00 2001 From: Unknown Date: Sat, 22 Sep 2018 16:35:22 -0400 Subject: [PATCH 01/72] Make interface_can a class, so it can be instantiated multiple times --- Firmware/MotorControl/main.cpp | 11 + Firmware/MotorControl/odrive_main.h | 4 + Firmware/communication/communication.cpp | 10 +- Firmware/communication/interface_can.cpp | 264 +++-------------------- Firmware/communication/interface_can.hpp | 75 +++---- 5 files changed, 78 insertions(+), 286 deletions(-) diff --git a/Firmware/MotorControl/main.cpp b/Firmware/MotorControl/main.cpp index 18b88433..3b91e075 100644 --- a/Firmware/MotorControl/main.cpp +++ b/Firmware/MotorControl/main.cpp @@ -7,8 +7,10 @@ #include #include #include +#include BoardConfig_t board_config; +CANConfig_t can_config; Encoder::Config_t encoder_configs[AXIS_COUNT]; SensorlessEstimator::Config_t sensorless_configs[AXIS_COUNT]; ControllerConfig_t controller_configs[AXIS_COUNT]; @@ -19,9 +21,13 @@ bool user_config_loaded_; SystemStats_t system_stats_ = { 0 }; Axis *axes[AXIS_COUNT]; +ODriveCAN *odCAN; + + typedef Config< BoardConfig_t, + CANConfig_t, Encoder::Config_t[AXIS_COUNT], SensorlessEstimator::Config_t[AXIS_COUNT], ControllerConfig_t[AXIS_COUNT], @@ -31,6 +37,7 @@ typedef Config< void save_configuration(void) { if (ConfigFormat::safe_store_config( &board_config, + &can_config, &encoder_configs, &sensorless_configs, &controller_configs, @@ -47,6 +54,7 @@ void load_configuration(void) { if (NVM_init() || ConfigFormat::safe_load_config( &board_config, + &can_config, &encoder_configs, &sensorless_configs, &controller_configs, @@ -54,6 +62,7 @@ void load_configuration(void) { &axis_configs)) { //If loading failed, restore defaults board_config = BoardConfig_t(); + can_config = CANConfig_t(); for (size_t i = 0; i < AXIS_COUNT; ++i) { encoder_configs[i] = Encoder::Config_t(); sensorless_configs[i] = SensorlessEstimator::Config_t(); @@ -104,6 +113,7 @@ void vApplicationIdleHook(void) { system_stats_.min_stack_space_uart = uxTaskGetStackHighWaterMark(uart_thread) * sizeof(StackType_t); system_stats_.min_stack_space_usb_irq = uxTaskGetStackHighWaterMark(usb_irq_thread) * sizeof(StackType_t); system_stats_.min_stack_space_startup = uxTaskGetStackHighWaterMark(defaultTaskHandle) * sizeof(StackType_t); + system_stats_.min_stack_space_can = uxTaskGetStackHighWaterMark(odCAN->thread_id_) * sizeof(StackType_t); } } } @@ -154,6 +164,7 @@ int odrive_main(void) { #endif // Construct all objects. + odCAN = new ODriveCAN(&hcan1, can_config); for (size_t i = 0; i < AXIS_COUNT; ++i) { Encoder *encoder = new Encoder(hw_configs[i].encoder_config, encoder_configs[i]); diff --git a/Firmware/MotorControl/odrive_main.h b/Firmware/MotorControl/odrive_main.h index 4e4db160..0df04433 100644 --- a/Firmware/MotorControl/odrive_main.h +++ b/Firmware/MotorControl/odrive_main.h @@ -47,6 +47,7 @@ typedef struct { uint32_t min_stack_space_uart; uint32_t min_stack_space_usb_irq; uint32_t min_stack_space_startup; + uint32_t min_stack_space_can; } SystemStats_t; extern SystemStats_t system_stats_; @@ -79,11 +80,14 @@ struct BoardConfig_t { extern BoardConfig_t board_config; extern bool user_config_loaded_; +// Forward Declarations class Axis; class Motor; +class ODriveCAN; constexpr size_t AXIS_COUNT = 2; extern Axis *axes[AXIS_COUNT]; +extern ODriveCAN *odCAN; // if you use the oscilloscope feature you can bump up this value #define OSCILLOSCOPE_SIZE 128 diff --git a/Firmware/communication/communication.cpp b/Firmware/communication/communication.cpp index 622bdefb..843f46b3 100644 --- a/Firmware/communication/communication.cpp +++ b/Firmware/communication/communication.cpp @@ -91,13 +91,9 @@ void init_communication(void) { osDelay(1); } - float oscilloscope[OSCILLOSCOPE_SIZE] = {0}; size_t oscilloscope_pos = 0; - -static CAN_context can1_ctx; - // Helper class because the protocol library doesn't yet // support non-member functions // TODO: make this go away @@ -136,6 +132,7 @@ static inline auto make_obj_tree() { make_protocol_ro_property("min_stack_space_comms", &system_stats_.min_stack_space_comms), make_protocol_ro_property("min_stack_space_usb", &system_stats_.min_stack_space_usb), make_protocol_ro_property("min_stack_space_uart", &system_stats_.min_stack_space_uart), + make_protocol_ro_property("min_stack_space_can", &system_stats_.min_stack_space_can), make_protocol_ro_property("min_stack_space_usb_irq", &system_stats_.min_stack_space_usb_irq), make_protocol_ro_property("min_stack_space_startup", &system_stats_.min_stack_space_startup), make_protocol_object("usb", @@ -167,7 +164,7 @@ static inline auto make_obj_tree() { ), make_protocol_object("axis0", axes[0]->make_protocol_definitions()), make_protocol_object("axis1", axes[1]->make_protocol_definitions()), - make_protocol_object("can", can1_ctx.make_protocol_definitions()), + make_protocol_object("can", odCAN->make_protocol_definitions()), make_protocol_property("test_property", &test_property), make_protocol_function("test_function", static_functions, &StaticFunctions::test_function, "delta"), make_protocol_function("get_oscilloscope_val", static_functions, &StaticFunctions::get_oscilloscope_val, "index"), @@ -202,8 +199,7 @@ void communication_task(void * ctx) { if (board_config.enable_i2c_instead_of_can) { start_i2c_server(); } else { - // TODO: finish implementing CAN - // start_can_server(can1_ctx, CAN1, serial_number); + odCAN->start_can_server(); } for (;;) { diff --git a/Firmware/communication/interface_can.cpp b/Firmware/communication/interface_can.cpp index 3bf822bd..b020f4c1 100644 --- a/Firmware/communication/interface_can.cpp +++ b/Firmware/communication/interface_can.cpp @@ -36,262 +36,48 @@ #include "utils.h" #include -#include #include +#include -#define CAN_HEARTBEAT_INTERVAL 1000 // [ms] -#define CAN_HEARTBEAT_MARGIN 10 // maximum time that a heartbeat message can be delayed until we stop sending other messages [ms] - -// defined in can.c -extern CAN_HandleTypeDef hcan1; -extern CAN_HandleTypeDef hcan2; -extern CAN_HandleTypeDef hcan3; - -static CAN_context* ctxs[3] = { nullptr, nullptr, nullptr }; - -struct CAN_context* get_can_ctx(CAN_HandleTypeDef *hcan) { -#if defined(CAN1) - if (hcan->Instance == CAN1) return ctxs[0]; -#endif -#if defined(CAN2) - if (hcan->Instance == CAN2) return ctxs[1]; -#endif -#if defined(CAN3) - if (hcan->Instance == CAN3) return ctxs[2]; -#endif - return nullptr; +// Constructor is called by communication.cpp and the handle is assigned appropriately +ODriveCAN::ODriveCAN(CAN_HandleTypeDef *handle, CANConfig_t &config) + : handle_{handle}, + config_{config} { } - -void consider_node_id_in_use(CAN_context* ctx, uint8_t node_id) { - ctx->node_ids_in_use_0[node_id >> 5] |= (1 << (node_id & 0x1f)); +static void can_server_thread_wrapper(void* ctx){ + reinterpret_cast(ctx)->can_server_thread(); + reinterpret_cast(ctx)->thread_id_valid_ = false; } -bool is_node_id_in_use(CAN_context* ctx, uint32_t node_id) { - if (node_id == 0) // node ID 0 is reserved (is it though?) - return true; - return (ctx->node_ids_in_use_0[node_id >> 5] & (1 << (node_id & 0x1f))) - || (ctx->node_ids_in_use_1[node_id >> 5] & (1 << (node_id & 0x1f))); -} - -bool select_another_node_id(CAN_context* ctx) { - ctx->node_id_expiry = osKernelSysTick() - 1; - - // Find a new node ID that is not in use - for (uint8_t i = 0; i < 32; i++) { - // Each time we select a new node ID, we use the next byte from the serial - // number to get advance the node ID. - uint8_t poor_mans_random_byte = ((uint8_t*)ctx->serial_number)[ctx->node_id_rng_state]; - if (++(ctx->node_id_rng_state) >= sizeof(ctx->serial_number)) - ctx->node_id_rng_state = 0; - ctx->node_id = calc_crc(ctx->node_id, poor_mans_random_byte); - if (!is_node_id_in_use(ctx, ctx->node_id)) - return true; - } - return false; -} - - -void server_thread(CAN_context* ctx) { - uint32_t next_1s_tick = osKernelSysTick() + 1000; +void ODriveCAN::can_server_thread() { for (;;) { - if (deadline_to_timeout(next_1s_tick) == 0) - - // wait until either the next heartbeat is due or a hearbeat was requested - // by releasing the semaphore - osSemaphoreWait(ctx->sem_send_heartbeat, deadline_to_timeout(next_1s_tick)); - if (!is_in_the_future(next_1s_tick)) - memcpy(ctx->node_ids_in_use_1, ctx->node_ids_in_use_0, sizeof(ctx->node_ids_in_use_1)); - next_1s_tick += 1000; - if (!is_in_the_future(next_1s_tick)) - next_1s_tick = osKernelSysTick(); // fast-forward if we missed several 1 second ticks - - if (is_node_id_in_use(ctx, ctx->node_id)) { - if (!select_another_node_id(ctx)) - continue; - else - next_1s_tick += ctx->node_id; // shift the 1s tick by a bit - } - - uint8_t data[8]; - //uint8_t data[] = { ctx->node_id }; // this would be the correct data for CANopen - TODO: make it compatible - *(uint64_t*)data = ctx->serial_number; - - CAN_TxHeaderTypeDef header = { - .StdId = 0x700u + ctx->node_id, - .ExtId = 0, - .IDE = CAN_ID_STD, - .RTR = CAN_RTR_DATA, - .DLC = sizeof(data), - .TransmitGlobalTime = DISABLE - }; - HAL_CAN_AddTxMessage(ctx->handle, &header, data, &ctx->last_heartbeat_mailbox); + // Do nothing } } -bool start_can_server(CAN_context& ctx, CAN_TypeDef *port, uint64_t serial_number) { - //MX_CAN1_Init(); // TODO: flatten -#if defined(CAN1) - if (port == CAN1) ctx.handle = &hcan1, ctxs[0] = &ctx; else -#endif -#if defined(CAN2) - // TODO: move CubeMX stuff into this file so all symbols are defined - //if (port == CAN2) ctx.handle = &hcan2, ctxs[1] = &ctx; else -#endif -#if defined(CAN3) - if (port == CAN3) ctx.handle = &hcan3, ctxs[2] = &ctx; else -#endif - return false; // fail if none of the above checks matched - +bool ODriveCAN::start_can_server() { HAL_StatusTypeDef status; - ctx.node_id = calc_crc(0, (const uint8_t*)UID_BASE, 12); - ctx.serial_number = serial_number; - osSemaphoreDef(sem_send_heartbeat); - ctx.sem_send_heartbeat = osSemaphoreCreate(osSemaphore(sem_send_heartbeat), 1); - osSemaphoreWait(ctx.sem_send_heartbeat, 0); - - //// Set up heartbeat filter - CAN_FilterTypeDef sFilterConfig = { - .FilterIdHigh = ((0x700u + ctx.node_id) << 5) | (0x0 << 2), // own heartbeat (standard ID, no RTR) - .FilterIdLow = (0x700u << 5) | (0x0 << 2), // any heartbeat (standard ID, no RTR) - .FilterMaskIdHigh = (0x7ffu << 5) | (0x3 << 2), - .FilterMaskIdLow = (0x780u << 5) | (0x3 << 2), - .FilterFIFOAssignment = CAN_RX_FIFO0, - .FilterBank = 0, - .FilterMode = CAN_FILTERMODE_IDMASK, - .FilterScale = CAN_FILTERSCALE_16BIT, // two 16-bit filters - .FilterActivation = ENABLE, - .SlaveStartFilterBank = 0 - }; - status = HAL_CAN_ConfigFilter(ctx.handle, &sFilterConfig); + status = HAL_CAN_Start(handle_); if (status != HAL_OK) return false; - status = HAL_CAN_Start(ctx.handle); + status = HAL_CAN_ActivateNotification(handle_, + CAN_IT_TX_MAILBOX_EMPTY | + CAN_IT_RX_FIFO0_MSG_PENDING | CAN_IT_RX_FIFO1_MSG_PENDING | /* we probably only want this */ + CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO1_FULL | + CAN_IT_RX_FIFO0_OVERRUN | CAN_IT_RX_FIFO1_OVERRUN | + CAN_IT_WAKEUP | CAN_IT_SLEEP_ACK | + CAN_IT_ERROR_WARNING | CAN_IT_ERROR_PASSIVE | + CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE | + CAN_IT_ERROR); if (status != HAL_OK) return false; - status = HAL_CAN_ActivateNotification(ctx.handle, - CAN_IT_TX_MAILBOX_EMPTY | - CAN_IT_RX_FIFO0_MSG_PENDING | CAN_IT_RX_FIFO1_MSG_PENDING | /* we probably only want this */ - CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO1_FULL | - CAN_IT_RX_FIFO0_OVERRUN | CAN_IT_RX_FIFO1_OVERRUN | - CAN_IT_WAKEUP | CAN_IT_SLEEP_ACK | - CAN_IT_ERROR_WARNING | CAN_IT_ERROR_PASSIVE | - CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE | - CAN_IT_ERROR); - if (status != HAL_OK) - return false; + osThreadDef(can_server_thread_def, can_server_thread_wrapper, osPriorityNormal, 0, 512); + thread_id_ = osThreadCreate(osThread(can_server_thread_def), this); + thread_id_valid_ = true; - server_thread(&ctx); return true; -} - -void tx_complete_callback(CAN_HandleTypeDef *hcan, uint8_t mailbox_idx) { - CAN_context *ctx = get_can_ctx(hcan); - if (!ctx) return; - ctx->tx_msg_cnt++; - if (mailbox_idx == ctx->last_heartbeat_mailbox) { - // we succeeded in sending a heartbeat - // now we're allowed to send messages for the next second plus a small margin - ctx->node_id_expiry = osKernelSysTick() + CAN_HEARTBEAT_INTERVAL + CAN_HEARTBEAT_MARGIN; - } -} - -void tx_aborted_callback(CAN_HandleTypeDef *hcan, uint8_t mailbox_idx) { - //__asm volatile ("bkpt"); - if (!get_can_ctx(hcan)) - return; - get_can_ctx(hcan)->TxMailboxAbortCallbackCnt++; -} - -void tx_error(CAN_context *ctx, uint8_t mailbox_idx) { - if (mailbox_idx == ctx->last_heartbeat_mailbox) { - // Consider the node ID in use - consider_node_id_in_use(ctx, ctx->node_id); - // Try to find a new node ID that is not in use and immediately - // resend heartbeat if we find one - if (select_another_node_id(ctx)) - osSemaphoreRelease(ctx->sem_send_heartbeat); - } -} - -void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) { tx_complete_callback(hcan, 0); } -void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) { tx_complete_callback(hcan, 1); } -void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) { tx_complete_callback(hcan, 2); } -void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) { tx_aborted_callback(hcan, 0); } -void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) { tx_aborted_callback(hcan, 1); } -void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) { tx_aborted_callback(hcan, 2); } - -void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) { - CAN_context *ctx = get_can_ctx(hcan); - if (!ctx) return; - ctx->received_msg_cnt++; - - CAN_RxHeaderTypeDef header; - uint8_t data[8]; - HAL_StatusTypeDef status = HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &header, data); - if (status != HAL_OK) { - ctx->unexpected_errors++; - return; - } - - uint8_t node_id = header.StdId & 0x07fu; - if ((header.StdId & 0x780u) == 0x700u) { - ctx->received_ack++; - consider_node_id_in_use(ctx, node_id); - } else { - ctx->unhandled_messages++; - } -} - -void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) { if (get_can_ctx(hcan)) get_can_ctx(hcan)->RxFifo0FullCallbackCnt++; } - -void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) { if (get_can_ctx(hcan)) get_can_ctx(hcan)->RxFifo1MsgPendingCallbackCnt++; } -void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) { if (get_can_ctx(hcan)) get_can_ctx(hcan)->RxFifo1FullCallbackCnt++; } -void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) { if (get_can_ctx(hcan)) get_can_ctx(hcan)->SleepCallbackCnt++; } -void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) { if (get_can_ctx(hcan)) get_can_ctx(hcan)->WakeUpFromRxMsgCallbackCnt++; } - -void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { - //__asm volatile ("bkpt"); - CAN_context *ctx = get_can_ctx(hcan); - if (!ctx) return; - volatile uint32_t original_error = hcan->ErrorCode; - (void) original_error; - - // handle transmit errors in all three mailboxes - if (hcan->ErrorCode & HAL_CAN_ERROR_TX_ALST0) { - SET_BIT(hcan->Instance->sTxMailBox[0].TIR, CAN_TI0R_TXRQ); - hcan->ErrorCode &= ~HAL_CAN_ERROR_TX_ALST0; - } else if (hcan->ErrorCode & HAL_CAN_ERROR_TX_TERR0) { - tx_error(ctx, 0); - hcan->ErrorCode &= ~HAL_CAN_ERROR_EWG; - hcan->ErrorCode &= ~HAL_CAN_ERROR_ACK; - hcan->ErrorCode &= ~HAL_CAN_ERROR_TX_TERR0; - } - - if (hcan->ErrorCode & HAL_CAN_ERROR_TX_ALST1) { - SET_BIT(hcan->Instance->sTxMailBox[1].TIR, CAN_TI1R_TXRQ); - hcan->ErrorCode &= ~HAL_CAN_ERROR_TX_ALST1; - } else if (hcan->ErrorCode & HAL_CAN_ERROR_TX_TERR1) { - tx_error(ctx, 1); - hcan->ErrorCode &= ~HAL_CAN_ERROR_EWG; - hcan->ErrorCode &= ~HAL_CAN_ERROR_ACK; - hcan->ErrorCode &= ~HAL_CAN_ERROR_TX_TERR1; - } - - if (hcan->ErrorCode & HAL_CAN_ERROR_TX_ALST2) { - SET_BIT(hcan->Instance->sTxMailBox[2].TIR, CAN_TI2R_TXRQ); - hcan->ErrorCode &= ~HAL_CAN_ERROR_TX_ALST2; - } else if (hcan->ErrorCode & HAL_CAN_ERROR_TX_TERR2) { - tx_error(ctx, 2); - hcan->ErrorCode &= ~HAL_CAN_ERROR_EWG; - hcan->ErrorCode &= ~HAL_CAN_ERROR_ACK; - hcan->ErrorCode &= ~HAL_CAN_ERROR_TX_TERR2; - } - - if (hcan->ErrorCode) - ctx->unexpected_errors++; -} - +} \ No newline at end of file diff --git a/Firmware/communication/interface_can.hpp b/Firmware/communication/interface_can.hpp index 2cd487b0..548a444f 100644 --- a/Firmware/communication/interface_can.hpp +++ b/Firmware/communication/interface_can.hpp @@ -1,55 +1,50 @@ #ifndef __INTERFACE_CAN_HPP #define __INTERFACE_CAN_HPP -#include "fibre/protocol.hpp" -#include #include +#include +#include "fibre/protocol.hpp" -struct CAN_context { - CAN_HandleTypeDef *handle = nullptr; - uint8_t node_id = 0; - uint64_t serial_number = 0; +struct { + uint32_t id; + bool isExt; + uint8_t len; + uint8_t buf[8]; +} CAN_message_t; - uint32_t node_ids_in_use_0[4]; // 128 bits (indicate if a node ID was in use up to 1 second ago) - uint32_t node_ids_in_use_1[4]; // 128 bits (indicats if a node ID was in use 1-2 seconds ago) +// Anonymous enum for defining the most common CAN baud rates +enum { + CAN_BAUD_125K = 125000, + CAN_BAUD_250K = 250000, + CAN_BAUD_500K = 500000, + CAN_BAUD_1000K = 1000000, + CAN_BAUD_1M = 1000000 +}; +struct CANConfig_t { + uint8_t node_id; + uint32_t baud; +}; - uint32_t last_heartbeat_mailbox = 0; - uint32_t tx_msg_cnt = 0; - uint32_t node_id_expiry = 0; - - uint8_t node_id_rng_state = 0; +class ODriveCAN { + public: + ODriveCAN(CAN_HandleTypeDef *handle, CANConfig_t &config); - osSemaphoreId sem_send_heartbeat; + bool start_can_server(); + void can_server_thread(); - // count occurrence various callbacks - uint32_t TxMailboxCompleteCallbackCnt = 0; - uint32_t TxMailboxAbortCallbackCnt = 0; - int RxFifo0MsgPendingCallbackCnt = 0; - int RxFifo0FullCallbackCnt = 0; - int RxFifo1MsgPendingCallbackCnt = 0; - int RxFifo1FullCallbackCnt = 0; - int SleepCallbackCnt = 0; - int WakeUpFromRxMsgCallbackCnt = 0; - int ErrorCallbackCnt = 0; - - uint32_t received_msg_cnt = 0; - uint32_t received_ack = 0; - uint32_t unexpected_errors = 0; - uint32_t unhandled_messages = 0; + osThreadId thread_id_; + volatile bool thread_id_valid_ = false; auto make_protocol_definitions() { return make_protocol_member_list( - make_protocol_ro_property("node_id", &node_id), - make_protocol_ro_property("TxMailboxCompleteCallbackCnt", &TxMailboxCompleteCallbackCnt), - make_protocol_ro_property("TxMailboxAbortCallbackCnt", &TxMailboxAbortCallbackCnt), - make_protocol_ro_property("received_msg_cnt", &received_msg_cnt), - make_protocol_ro_property("received_ack", &received_ack), - make_protocol_ro_property("unexpected_errors", &unexpected_errors), - make_protocol_ro_property("unhandled_messages", &unhandled_messages) - ); + make_protocol_object("config", + make_protocol_property("node_id", &config_.node_id), + make_protocol_property("baud_rate", &config_.baud))); } + + private: + CAN_HandleTypeDef *handle_ = nullptr; + CANConfig_t &config_; }; -bool start_can_server(CAN_context& ctx, CAN_TypeDef *hcan, uint64_t serial_number); - -#endif // __INTERFACE_CAN_HPP +#endif // __INTERFACE_CAN_HPP From deb7a9adde6cc9163d64c9936a93255586a3cabc Mon Sep 17 00:00:00 2001 From: Unknown Date: Sat, 22 Sep 2018 16:52:36 -0400 Subject: [PATCH 02/72] Add baud rate validation via set function --- Firmware/communication/interface_can.cpp | 20 +++++++++++++++++++- Firmware/communication/interface_can.hpp | 15 +++++++++++---- 2 files changed, 30 insertions(+), 5 deletions(-) diff --git a/Firmware/communication/interface_can.cpp b/Firmware/communication/interface_can.cpp index b020f4c1..6709daa5 100644 --- a/Firmware/communication/interface_can.cpp +++ b/Firmware/communication/interface_can.cpp @@ -52,7 +52,7 @@ static void can_server_thread_wrapper(void* ctx){ void ODriveCAN::can_server_thread() { for (;;) { - // Do nothing + osDelay(1000); } } @@ -80,4 +80,22 @@ bool ODriveCAN::start_can_server() { thread_id_valid_ = true; return true; +} + +void ODriveCAN::set_baud_rate(uint32_t baudRate){ + switch(baudRate){ + case CAN_BAUD_125K: + case CAN_BAUD_250K: + case CAN_BAUD_500K: + case CAN_BAUD_1000K: + config_.baud = baudRate; // baudRate is a valid CAN baud + break; + default: + break; // baudRate is invalid, so do nothing + } +} + +void ODriveCAN::set_node_id(uint8_t nodeID){ + // Allow for future nodeID validation by making this a set function + config_.node_id = nodeID; } \ No newline at end of file diff --git a/Firmware/communication/interface_can.hpp b/Firmware/communication/interface_can.hpp index 548a444f..35b7c3b3 100644 --- a/Firmware/communication/interface_can.hpp +++ b/Firmware/communication/interface_can.hpp @@ -21,8 +21,8 @@ enum { CAN_BAUD_1M = 1000000 }; struct CANConfig_t { - uint8_t node_id; - uint32_t baud; + uint8_t node_id = 0; + uint32_t baud = CAN_BAUD_250K; }; class ODriveCAN { @@ -38,13 +38,20 @@ class ODriveCAN { auto make_protocol_definitions() { return make_protocol_member_list( make_protocol_object("config", - make_protocol_property("node_id", &config_.node_id), - make_protocol_property("baud_rate", &config_.baud))); + make_protocol_ro_property("node_id", &config_.node_id), + make_protocol_ro_property("baud_rate", &config_.baud) + ), + make_protocol_function("set_node_id", *this, &ODriveCAN::set_node_id, "nodeID"), + make_protocol_function("set_baud_rate", *this, &ODriveCAN::set_baud_rate, "baudRate") + ); } private: CAN_HandleTypeDef *handle_ = nullptr; CANConfig_t &config_; + + void set_node_id(uint8_t nodeID); + void set_baud_rate(uint32_t baudRate); }; #endif // __INTERFACE_CAN_HPP From 3ba3d4e4133263a0df01560b3e6624539db71810 Mon Sep 17 00:00:00 2001 From: Unknown Date: Sat, 22 Sep 2018 18:50:05 -0400 Subject: [PATCH 03/72] Allow for different baud rates by adjusting prescaler and time quanta --- Firmware/Board/v3/Src/can.c | 8 ++-- Firmware/MotorControl/main.cpp | 2 - Firmware/communication/interface_can.cpp | 60 ++++++++++++++++-------- Firmware/communication/interface_can.hpp | 3 ++ 4 files changed, 48 insertions(+), 25 deletions(-) diff --git a/Firmware/Board/v3/Src/can.c b/Firmware/Board/v3/Src/can.c index fc7bf388..d4cff30a 100644 --- a/Firmware/Board/v3/Src/can.c +++ b/Firmware/Board/v3/Src/can.c @@ -63,11 +63,11 @@ void MX_CAN1_Init(void) { hcan1.Instance = CAN1; - hcan1.Init.Prescaler = 7; + hcan1.Init.Prescaler = 8; hcan1.Init.Mode = CAN_MODE_NORMAL; - hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; - hcan1.Init.TimeSeg1 = CAN_BS1_6TQ; - hcan1.Init.TimeSeg2 = CAN_BS2_5TQ; + hcan1.Init.SyncJumpWidth = CAN_SJW_4TQ; + hcan1.Init.TimeSeg1 = CAN_BS1_16TQ; + hcan1.Init.TimeSeg2 = CAN_BS2_4TQ; hcan1.Init.TimeTriggeredMode = DISABLE; hcan1.Init.AutoBusOff = DISABLE; hcan1.Init.AutoWakeUp = ENABLE; diff --git a/Firmware/MotorControl/main.cpp b/Firmware/MotorControl/main.cpp index 3b91e075..af9682d5 100644 --- a/Firmware/MotorControl/main.cpp +++ b/Firmware/MotorControl/main.cpp @@ -23,8 +23,6 @@ SystemStats_t system_stats_ = { 0 }; Axis *axes[AXIS_COUNT]; ODriveCAN *odCAN; - - typedef Config< BoardConfig_t, CANConfig_t, diff --git a/Firmware/communication/interface_can.cpp b/Firmware/communication/interface_can.cpp index 6709daa5..985b33f6 100644 --- a/Firmware/communication/interface_can.cpp +++ b/Firmware/communication/interface_can.cpp @@ -45,57 +45,79 @@ ODriveCAN::ODriveCAN(CAN_HandleTypeDef *handle, CANConfig_t &config) config_{config} { } -static void can_server_thread_wrapper(void* ctx){ - reinterpret_cast(ctx)->can_server_thread(); - reinterpret_cast(ctx)->thread_id_valid_ = false; +static void can_server_thread_wrapper(void *ctx) { + reinterpret_cast(ctx)->can_server_thread(); + reinterpret_cast(ctx)->thread_id_valid_ = false; } void ODriveCAN::can_server_thread() { for (;;) { - osDelay(1000); + osDelay(10); } } bool ODriveCAN::start_can_server() { HAL_StatusTypeDef status; + set_baud_rate(config_.baud); + status = HAL_CAN_Init(handle_); + if (status != HAL_OK) + return false; + status = HAL_CAN_Start(handle_); if (status != HAL_OK) return false; status = HAL_CAN_ActivateNotification(handle_, - CAN_IT_TX_MAILBOX_EMPTY | - CAN_IT_RX_FIFO0_MSG_PENDING | CAN_IT_RX_FIFO1_MSG_PENDING | /* we probably only want this */ - CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO1_FULL | - CAN_IT_RX_FIFO0_OVERRUN | CAN_IT_RX_FIFO1_OVERRUN | - CAN_IT_WAKEUP | CAN_IT_SLEEP_ACK | - CAN_IT_ERROR_WARNING | CAN_IT_ERROR_PASSIVE | - CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE | - CAN_IT_ERROR); + CAN_IT_TX_MAILBOX_EMPTY | + CAN_IT_RX_FIFO0_MSG_PENDING | CAN_IT_RX_FIFO1_MSG_PENDING | /* we probably only want this */ + CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO1_FULL | + CAN_IT_RX_FIFO0_OVERRUN | CAN_IT_RX_FIFO1_OVERRUN | + CAN_IT_WAKEUP | CAN_IT_SLEEP_ACK | + CAN_IT_ERROR_WARNING | CAN_IT_ERROR_PASSIVE | + CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE | + CAN_IT_ERROR); if (status != HAL_OK) return false; osThreadDef(can_server_thread_def, can_server_thread_wrapper, osPriorityNormal, 0, 512); thread_id_ = osThreadCreate(osThread(can_server_thread_def), this); thread_id_valid_ = true; - + return true; } -void ODriveCAN::set_baud_rate(uint32_t baudRate){ - switch(baudRate){ - case CAN_BAUD_125K: +void ODriveCAN::set_baud_rate(uint32_t baudRate) { + switch (baudRate) { + case CAN_BAUD_125K: + handle_->Init.Prescaler = 21; // 16 TQ's + handle_->Init.TimeSeg1 = CAN_BS1_12TQ; + handle_->Init.TimeSeg2 = CAN_BS2_3TQ; + config_.baud = baudRate; + break; case CAN_BAUD_250K: + handle_->Init.Prescaler = 8; // 21 TQ's + handle_->Init.TimeSeg1 = CAN_BS1_16TQ; + handle_->Init.TimeSeg2 = CAN_BS2_4TQ; + config_.baud = baudRate; + break; case CAN_BAUD_500K: + handle_->Init.Prescaler = 4; // 21 TQ's + handle_->Init.TimeSeg1 = CAN_BS1_16TQ; + handle_->Init.TimeSeg2 = CAN_BS2_4TQ; + config_.baud = baudRate; case CAN_BAUD_1000K: - config_.baud = baudRate; // baudRate is a valid CAN baud + handle_->Init.Prescaler = 2; // 21 TQ's + handle_->Init.TimeSeg1 = CAN_BS1_16TQ; + handle_->Init.TimeSeg2 = CAN_BS2_4TQ; + config_.baud = baudRate; break; default: - break; // baudRate is invalid, so do nothing + break; // baudRate is invalid, so do nothing } } -void ODriveCAN::set_node_id(uint8_t nodeID){ +void ODriveCAN::set_node_id(uint8_t nodeID) { // Allow for future nodeID validation by making this a set function config_.node_id = nodeID; } \ No newline at end of file diff --git a/Firmware/communication/interface_can.hpp b/Firmware/communication/interface_can.hpp index 35b7c3b3..2403023e 100644 --- a/Firmware/communication/interface_can.hpp +++ b/Firmware/communication/interface_can.hpp @@ -5,6 +5,9 @@ #include #include "fibre/protocol.hpp" +#define CAN_CLK_HZ (42000000) +#define CAN_CLK_MHZ (42) + struct { uint32_t id; bool isExt; From 6a87ca8e9171ba394cb6552c30ef6b8dcd4ac488 Mon Sep 17 00:00:00 2001 From: Unknown Date: Sat, 22 Sep 2018 19:11:35 -0400 Subject: [PATCH 04/72] Add write function for CAN class --- Firmware/communication/interface_can.cpp | 42 ++++++++++++++++++++---- Firmware/communication/interface_can.hpp | 5 ++- 2 files changed, 39 insertions(+), 8 deletions(-) diff --git a/Firmware/communication/interface_can.cpp b/Firmware/communication/interface_can.cpp index 985b33f6..4902ca2f 100644 --- a/Firmware/communication/interface_can.cpp +++ b/Firmware/communication/interface_can.cpp @@ -39,23 +39,36 @@ #include #include +static uint32_t counter = 0; // Constructor is called by communication.cpp and the handle is assigned appropriately ODriveCAN::ODriveCAN(CAN_HandleTypeDef *handle, CANConfig_t &config) : handle_{handle}, config_{config} { } +void ODriveCAN::can_server_thread() { + for (;;) { + CAN_message_t txmsg; + txmsg.id = 0x100; + txmsg.len = 4; + txmsg.isExt = false; + + txmsg.buf[0] = counter >> 24; + txmsg.buf[1] = counter >> 16; + txmsg.buf[2] = counter >> 8; + txmsg.buf[3] = counter; + + write(txmsg); // Transmit message w/ counter at ID = 0x100 + + osDelay(10); + } +} + static void can_server_thread_wrapper(void *ctx) { reinterpret_cast(ctx)->can_server_thread(); reinterpret_cast(ctx)->thread_id_valid_ = false; } -void ODriveCAN::can_server_thread() { - for (;;) { - osDelay(10); - } -} - bool ODriveCAN::start_can_server() { HAL_StatusTypeDef status; @@ -120,4 +133,19 @@ void ODriveCAN::set_baud_rate(uint32_t baudRate) { void ODriveCAN::set_node_id(uint8_t nodeID) { // Allow for future nodeID validation by making this a set function config_.node_id = nodeID; -} \ No newline at end of file +} + +uint32_t ODriveCAN::write(CAN_message_t& txmsg) { + CAN_TxHeaderTypeDef header; + header.StdId = txmsg.id; + header.ExtId = txmsg.id; + header.IDE = txmsg.isExt ? CAN_ID_EXT : CAN_ID_STD; + header.RTR = CAN_RTR_DATA; + header.DLC = txmsg.len; + header.TransmitGlobalTime = FunctionalState::DISABLE; + + uint32_t retTxMailbox; + HAL_CAN_AddTxMessage(handle_, &header, txmsg.buf, &retTxMailbox); + + return retTxMailbox; +} diff --git a/Firmware/communication/interface_can.hpp b/Firmware/communication/interface_can.hpp index 2403023e..0959d7c1 100644 --- a/Firmware/communication/interface_can.hpp +++ b/Firmware/communication/interface_can.hpp @@ -8,7 +8,7 @@ #define CAN_CLK_HZ (42000000) #define CAN_CLK_MHZ (42) -struct { +typedef struct { uint32_t id; bool isExt; uint8_t len; @@ -35,6 +35,9 @@ class ODriveCAN { bool start_can_server(); void can_server_thread(); + uint32_t write(CAN_message_t& txmsg); + int read(CAN_message_t& rxmsg); + osThreadId thread_id_; volatile bool thread_id_valid_ = false; From 75dfb48238592ad30657e68aa77c85fddb0b8198 Mon Sep 17 00:00:00 2001 From: Unknown Date: Fri, 28 Sep 2018 18:19:34 -0400 Subject: [PATCH 05/72] Unify the Config_t style for ODriveCAN --- Firmware/MotorControl/main.cpp | 6 ++-- Firmware/communication/interface_can.cpp | 2 +- Firmware/communication/interface_can.hpp | 38 ++++++++++++------------ 3 files changed, 23 insertions(+), 23 deletions(-) diff --git a/Firmware/MotorControl/main.cpp b/Firmware/MotorControl/main.cpp index 8c7351ac..290172c7 100644 --- a/Firmware/MotorControl/main.cpp +++ b/Firmware/MotorControl/main.cpp @@ -10,7 +10,7 @@ #include BoardConfig_t board_config; -CANConfig_t can_config; +ODriveCAN::Config_t can_config; Encoder::Config_t encoder_configs[AXIS_COUNT]; SensorlessEstimator::Config_t sensorless_configs[AXIS_COUNT]; Controller::Config_t controller_configs[AXIS_COUNT]; @@ -26,7 +26,7 @@ ODriveCAN *odCAN; typedef Config< BoardConfig_t, - CANConfig_t, + ODriveCAN::Config_t, Encoder::Config_t[AXIS_COUNT], SensorlessEstimator::Config_t[AXIS_COUNT], Controller::Config_t[AXIS_COUNT], @@ -64,7 +64,7 @@ void load_configuration(void) { &axis_configs)) { //If loading failed, restore defaults board_config = BoardConfig_t(); - can_config = CANConfig_t(); + can_config = ODriveCAN::Config_t(); for (size_t i = 0; i < AXIS_COUNT; ++i) { encoder_configs[i] = Encoder::Config_t(); sensorless_configs[i] = SensorlessEstimator::Config_t(); diff --git a/Firmware/communication/interface_can.cpp b/Firmware/communication/interface_can.cpp index 4902ca2f..f9a9ff6f 100644 --- a/Firmware/communication/interface_can.cpp +++ b/Firmware/communication/interface_can.cpp @@ -41,7 +41,7 @@ static uint32_t counter = 0; // Constructor is called by communication.cpp and the handle is assigned appropriately -ODriveCAN::ODriveCAN(CAN_HandleTypeDef *handle, CANConfig_t &config) +ODriveCAN::ODriveCAN(CAN_HandleTypeDef *handle, ODriveCAN::Config_t &config) : handle_{handle}, config_{config} { } diff --git a/Firmware/communication/interface_can.hpp b/Firmware/communication/interface_can.hpp index 0959d7c1..dceb8120 100644 --- a/Firmware/communication/interface_can.hpp +++ b/Firmware/communication/interface_can.hpp @@ -16,27 +16,29 @@ typedef struct { } CAN_message_t; // Anonymous enum for defining the most common CAN baud rates -enum { - CAN_BAUD_125K = 125000, - CAN_BAUD_250K = 250000, - CAN_BAUD_500K = 500000, - CAN_BAUD_1000K = 1000000, - CAN_BAUD_1M = 1000000 -}; -struct CANConfig_t { - uint8_t node_id = 0; - uint32_t baud = CAN_BAUD_250K; -}; + + enum { + CAN_BAUD_125K = 125000, + CAN_BAUD_250K = 250000, + CAN_BAUD_500K = 500000, + CAN_BAUD_1000K = 1000000, + CAN_BAUD_1M = 1000000 + }; class ODriveCAN { public: - ODriveCAN(CAN_HandleTypeDef *handle, CANConfig_t &config); + struct Config_t { + uint8_t node_id = 0; + uint32_t baud = CAN_BAUD_250K; + }; + + ODriveCAN(CAN_HandleTypeDef *handle, ODriveCAN::Config_t &config); bool start_can_server(); void can_server_thread(); - uint32_t write(CAN_message_t& txmsg); - int read(CAN_message_t& rxmsg); + uint32_t write(CAN_message_t &txmsg); + int read(CAN_message_t &rxmsg); osThreadId thread_id_; volatile bool thread_id_valid_ = false; @@ -45,16 +47,14 @@ class ODriveCAN { return make_protocol_member_list( make_protocol_object("config", make_protocol_ro_property("node_id", &config_.node_id), - make_protocol_ro_property("baud_rate", &config_.baud) - ), + make_protocol_ro_property("baud_rate", &config_.baud)), make_protocol_function("set_node_id", *this, &ODriveCAN::set_node_id, "nodeID"), - make_protocol_function("set_baud_rate", *this, &ODriveCAN::set_baud_rate, "baudRate") - ); + make_protocol_function("set_baud_rate", *this, &ODriveCAN::set_baud_rate, "baudRate")); } private: CAN_HandleTypeDef *handle_ = nullptr; - CANConfig_t &config_; + ODriveCAN::Config_t &config_; void set_node_id(uint8_t nodeID); void set_baud_rate(uint32_t baudRate); From 071c0fc802bf79aadf19237564c4ab8ea94d1f65 Mon Sep 17 00:00:00 2001 From: Unknown Date: Sat, 29 Sep 2018 18:17:54 -0400 Subject: [PATCH 06/72] Tweak CAN messaging, get it working with PSoC --- Firmware/communication/interface_can.cpp | 39 ++++++++++++++---------- Firmware/communication/interface_can.hpp | 2 +- 2 files changed, 24 insertions(+), 17 deletions(-) diff --git a/Firmware/communication/interface_can.cpp b/Firmware/communication/interface_can.cpp index f9a9ff6f..5ebaf3c0 100644 --- a/Firmware/communication/interface_can.cpp +++ b/Firmware/communication/interface_can.cpp @@ -39,7 +39,6 @@ #include #include -static uint32_t counter = 0; // Constructor is called by communication.cpp and the handle is assigned appropriately ODriveCAN::ODriveCAN(CAN_HandleTypeDef *handle, ODriveCAN::Config_t &config) : handle_{handle}, @@ -47,6 +46,7 @@ ODriveCAN::ODriveCAN(CAN_HandleTypeDef *handle, ODriveCAN::Config_t &config) } void ODriveCAN::can_server_thread() { + static uint32_t counter = 0; for (;;) { CAN_message_t txmsg; txmsg.id = 0x100; @@ -58,8 +58,8 @@ void ODriveCAN::can_server_thread() { txmsg.buf[2] = counter >> 8; txmsg.buf[3] = counter; - write(txmsg); // Transmit message w/ counter at ID = 0x100 - + counter++; + write(txmsg); osDelay(10); } } @@ -103,28 +103,33 @@ bool ODriveCAN::start_can_server() { void ODriveCAN::set_baud_rate(uint32_t baudRate) { switch (baudRate) { case CAN_BAUD_125K: - handle_->Init.Prescaler = 21; // 16 TQ's - handle_->Init.TimeSeg1 = CAN_BS1_12TQ; - handle_->Init.TimeSeg2 = CAN_BS2_3TQ; + handle_->Init.Prescaler = 16; // 21 TQ's + handle_->Init.TimeSeg1 = CAN_BS1_16TQ; + handle_->Init.TimeSeg2 = CAN_BS2_4TQ; config_.baud = baudRate; break; + case CAN_BAUD_250K: - handle_->Init.Prescaler = 8; // 21 TQ's + handle_->Init.Prescaler = 8; // 21 TQ's handle_->Init.TimeSeg1 = CAN_BS1_16TQ; handle_->Init.TimeSeg2 = CAN_BS2_4TQ; config_.baud = baudRate; break; + case CAN_BAUD_500K: - handle_->Init.Prescaler = 4; // 21 TQ's - handle_->Init.TimeSeg1 = CAN_BS1_16TQ; - handle_->Init.TimeSeg2 = CAN_BS2_4TQ; - config_.baud = baudRate; - case CAN_BAUD_1000K: - handle_->Init.Prescaler = 2; // 21 TQ's + handle_->Init.Prescaler = 4; // 21 TQ's handle_->Init.TimeSeg1 = CAN_BS1_16TQ; handle_->Init.TimeSeg2 = CAN_BS2_4TQ; config_.baud = baudRate; break; + + case CAN_BAUD_1000K: + handle_->Init.Prescaler = 2; // 21 TQ's + handle_->Init.TimeSeg1 = CAN_BS1_16TQ; + handle_->Init.TimeSeg2 = CAN_BS2_4TQ; + config_.baud = baudRate; + break; + default: break; // baudRate is invalid, so do nothing } @@ -135,7 +140,8 @@ void ODriveCAN::set_node_id(uint8_t nodeID) { config_.node_id = nodeID; } -uint32_t ODriveCAN::write(CAN_message_t& txmsg) { +// Send a CAN message on the bus +uint32_t ODriveCAN::write(CAN_message_t &txmsg) { CAN_TxHeaderTypeDef header; header.StdId = txmsg.id; header.ExtId = txmsg.id; @@ -145,7 +151,8 @@ uint32_t ODriveCAN::write(CAN_message_t& txmsg) { header.TransmitGlobalTime = FunctionalState::DISABLE; uint32_t retTxMailbox; - HAL_CAN_AddTxMessage(handle_, &header, txmsg.buf, &retTxMailbox); + if(HAL_CAN_GetTxMailboxesFreeLevel(handle_) > 0) + HAL_CAN_AddTxMessage(handle_, &header, txmsg.buf, &retTxMailbox); return retTxMailbox; -} +} \ No newline at end of file diff --git a/Firmware/communication/interface_can.hpp b/Firmware/communication/interface_can.hpp index dceb8120..6187440a 100644 --- a/Firmware/communication/interface_can.hpp +++ b/Firmware/communication/interface_can.hpp @@ -36,7 +36,7 @@ class ODriveCAN { bool start_can_server(); void can_server_thread(); - + uint32_t write(CAN_message_t &txmsg); int read(CAN_message_t &rxmsg); From 41998b67a6bcf58811b623998c761df1e9faf019 Mon Sep 17 00:00:00 2001 From: Unknown Date: Sun, 30 Sep 2018 01:49:34 -0400 Subject: [PATCH 07/72] Let the hardware handle re-transmission and reinit from busoff --- Firmware/Board/v3/Src/can.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Firmware/Board/v3/Src/can.c b/Firmware/Board/v3/Src/can.c index d4cff30a..011150ff 100644 --- a/Firmware/Board/v3/Src/can.c +++ b/Firmware/Board/v3/Src/can.c @@ -69,9 +69,9 @@ void MX_CAN1_Init(void) hcan1.Init.TimeSeg1 = CAN_BS1_16TQ; hcan1.Init.TimeSeg2 = CAN_BS2_4TQ; hcan1.Init.TimeTriggeredMode = DISABLE; - hcan1.Init.AutoBusOff = DISABLE; + hcan1.Init.AutoBusOff = ENABLE; hcan1.Init.AutoWakeUp = ENABLE; - hcan1.Init.AutoRetransmission = DISABLE; + hcan1.Init.AutoRetransmission = ENABLE; hcan1.Init.ReceiveFifoLocked = DISABLE; hcan1.Init.TransmitFifoPriority = DISABLE; if (HAL_CAN_Init(&hcan1) != HAL_OK) From 72fc50db6f50d67c205d7abb0d36e765248dfab0 Mon Sep 17 00:00:00 2001 From: Unknown Date: Sun, 30 Sep 2018 01:50:30 -0400 Subject: [PATCH 08/72] Setup semaphore for can --- Firmware/Board/v3/Inc/freertos_vars.h | 1 + Firmware/Board/v3/Src/freertos.c | 5 +++++ Firmware/communication/interface_can.cpp | 3 ++- 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/Firmware/Board/v3/Inc/freertos_vars.h b/Firmware/Board/v3/Inc/freertos_vars.h index 6982ee28..6e4c0696 100644 --- a/Firmware/Board/v3/Inc/freertos_vars.h +++ b/Firmware/Board/v3/Inc/freertos_vars.h @@ -7,6 +7,7 @@ extern osSemaphoreId sem_usb_irq; extern osSemaphoreId sem_uart_dma; extern osSemaphoreId sem_usb_rx; extern osSemaphoreId sem_usb_tx; +extern osSemaphoreId sem_can; extern osThreadId defaultTaskHandle; extern osThreadId usb_irq_thread; diff --git a/Firmware/Board/v3/Src/freertos.c b/Firmware/Board/v3/Src/freertos.c index 524cd6cb..5a078f79 100644 --- a/Firmware/Board/v3/Src/freertos.c +++ b/Firmware/Board/v3/Src/freertos.c @@ -67,6 +67,7 @@ osSemaphoreId sem_usb_irq; osSemaphoreId sem_uart_dma; osSemaphoreId sem_usb_rx; osSemaphoreId sem_usb_tx; +osSemaphoreId sem_can; osThreadId usb_irq_thread; @@ -165,6 +166,10 @@ void MX_FREERTOS_Init(void) { osSemaphoreDef(sem_usb_tx); sem_usb_tx = osSemaphoreCreate(osSemaphore(sem_usb_tx), 1); + osSemaphoreDef(sem_can); + sem_can = osSemaphoreCreate(osSemaphore(sem_can), 1); + osSemaphoreWait(sem_can, 0); + init_deferred_interrupts(); /* USER CODE END RTOS_SEMAPHORES */ diff --git a/Firmware/communication/interface_can.cpp b/Firmware/communication/interface_can.cpp index 5ebaf3c0..29a03a24 100644 --- a/Firmware/communication/interface_can.cpp +++ b/Firmware/communication/interface_can.cpp @@ -33,6 +33,7 @@ #include "interface_can.hpp" #include "fibre/crc.hpp" +#include "freertos_vars.h" #include "utils.h" #include @@ -50,7 +51,7 @@ void ODriveCAN::can_server_thread() { for (;;) { CAN_message_t txmsg; txmsg.id = 0x100; - txmsg.len = 4; + osSemaphoreWait(sem_can, 10); txmsg.isExt = false; txmsg.buf[0] = counter >> 24; From 3a460385b4002447b31adcb73f8489128f44001a Mon Sep 17 00:00:00 2001 From: Unknown Date: Sun, 30 Sep 2018 01:51:09 -0400 Subject: [PATCH 09/72] Messages should have clean default parameters --- Firmware/communication/interface_can.hpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Firmware/communication/interface_can.hpp b/Firmware/communication/interface_can.hpp index 6187440a..a309658b 100644 --- a/Firmware/communication/interface_can.hpp +++ b/Firmware/communication/interface_can.hpp @@ -9,10 +9,10 @@ #define CAN_CLK_MHZ (42) typedef struct { - uint32_t id; - bool isExt; - uint8_t len; - uint8_t buf[8]; + uint32_t id = 0x000; // 11-bit max is 0x7ff, 29-bit max is 0x1FFFFFFF + bool isExt = false; + uint8_t len = 8; + uint8_t buf[8] = {0, 0, 0, 0, 0, 0, 0, 0}; } CAN_message_t; // Anonymous enum for defining the most common CAN baud rates From d38f1c8464eff65879cf5232156279f18bd3a9e6 Mon Sep 17 00:00:00 2001 From: Unknown Date: Sun, 30 Sep 2018 01:51:36 -0400 Subject: [PATCH 10/72] Use an STM32F4 SVD for debugging so we can see registers --- Firmware/.vscode/launch.json | 1 + Firmware/Board/v3/STM32F40x.svd | 54146 ++++++++++++++++++++++++++++++ 2 files changed, 54147 insertions(+) create mode 100644 Firmware/Board/v3/STM32F40x.svd diff --git a/Firmware/.vscode/launch.json b/Firmware/.vscode/launch.json index 71e7db4c..48fecec2 100644 --- a/Firmware/.vscode/launch.json +++ b/Firmware/.vscode/launch.json @@ -15,6 +15,7 @@ "interface/stlink-v2.cfg", "target/stm32f4x_stlink.cfg", ], + "svdFile": "${workspaceRoot}/Board/v3/STM32F40x.svd", "cwd": "${workspaceRoot}" }, { diff --git a/Firmware/Board/v3/STM32F40x.svd b/Firmware/Board/v3/STM32F40x.svd new file mode 100644 index 00000000..3ead4727 --- /dev/null +++ b/Firmware/Board/v3/STM32F40x.svd @@ -0,0 +1,54146 @@ + + + STM32F40x + 1.5 + STM32F40x + + + 8 + + 32 + + 0x20 + 0x0 + 0xFFFFFFFF + + + RNG + Random number generator + RNG + 0x50060800 + + 0x0 + 0x400 + registers + + +FPU +FPU interrupt +81 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + IE + Interrupt enable + 3 + 1 + + + RNGEN + Random number generator + enable + 2 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + 0x00000000 + + + SEIS + Seed error interrupt + status + 6 + 1 + read-write + + + CEIS + Clock error interrupt + status + 5 + 1 + read-write + + + SECS + Seed error current status + 2 + 1 + read-only + + + CECS + Clock error current status + 1 + 1 + read-only + + + DRDY + Data ready + 0 + 1 + read-only + + + + + DR + DR + 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complete interrupt + flag (x=7..4) + 21 + 1 + + + HTIF6 + Stream x half transfer interrupt flag + (x=7..4) + 20 + 1 + + + TEIF6 + Stream x transfer error interrupt flag + (x=7..4) + 19 + 1 + + + DMEIF6 + Stream x direct mode error interrupt + flag (x=7..4) + 18 + 1 + + + FEIF6 + Stream x FIFO error interrupt flag + (x=7..4) + 16 + 1 + + + TCIF5 + Stream x transfer complete interrupt + flag (x=7..4) + 11 + 1 + + + HTIF5 + Stream x half transfer interrupt flag + (x=7..4) + 10 + 1 + + + TEIF5 + Stream x transfer error interrupt flag + (x=7..4) + 9 + 1 + + + DMEIF5 + Stream x direct mode error interrupt + flag (x=7..4) + 8 + 1 + + + FEIF5 + Stream x FIFO error interrupt flag + (x=7..4) + 6 + 1 + + + TCIF4 + Stream x transfer complete interrupt + flag (x=7..4) + 5 + 1 + + + HTIF4 + Stream x half transfer interrupt flag + (x=7..4) + 4 + 1 + + + TEIF4 + Stream x transfer error interrupt flag + (x=7..4) + 3 + 1 + + + DMEIF4 + Stream x direct mode error interrupt + flag (x=7..4) + 2 + 1 + + + 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Peripheral address + 0 + 32 + + + + + S4M0AR + S4M0AR + stream x memory 0 address + register + 0x7C + 0x20 + read-write + 0x00000000 + + + M0A + Memory 0 address + 0 + 32 + + + + + S4M1AR + S4M1AR + stream x memory 1 address + register + 0x80 + 0x20 + read-write + 0x00000000 + + + M1A + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S4FCR + S4FCR + stream x FIFO control register + 0x84 + 0x20 + 0x00000021 + + + FEIE + FIFO error interrupt + enable + 7 + 1 + read-write + + + FS + FIFO status + 3 + 3 + read-only + + + DMDIS + Direct mode disable + 2 + 1 + read-write + + + FTH + FIFO threshold selection + 0 + 2 + read-write + + + + + S5CR + S5CR + stream x configuration + register + 0x88 + 0x20 + read-write + 0x00000000 + + + CHSEL + Channel selection + 25 + 3 + + + MBURST + Memory burst transfer + configuration + 23 + 2 + + + PBURST + Peripheral burst transfer + configuration + 21 + 2 + + + ACK + ACK + 20 + 1 + + + CT + Current target (only in double buffer + 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(only in double buffer + mode) + 19 + 1 + + + DBM + Double buffer mode + 18 + 1 + + + PL + Priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MSIZE + Memory data size + 13 + 2 + + + PSIZE + Peripheral data size + 11 + 2 + + + MINC + Memory increment mode + 10 + 1 + + + PINC + Peripheral increment mode + 9 + 1 + + + CIRC + Circular mode + 8 + 1 + + + DIR + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + TCIE + Transfer complete interrupt + enable + 4 + 1 + + + HTIE + Half transfer interrupt + enable + 3 + 1 + + + TEIE + Transfer error interrupt + enable + 2 + 1 + + + DMEIE + Direct mode error interrupt + enable + 1 + 1 + + + EN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S6NDTR + S6NDTR + stream x number of data + register + 0xA4 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to + transfer + 0 + 16 + + + + + S6PAR + S6PAR + stream x peripheral address + register + 0xA8 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + S6M0AR + S6M0AR + stream x memory 0 address + register + 0xAC + 0x20 + read-write + 0x00000000 + + + M0A + Memory 0 address + 0 + 32 + + + + + S6M1AR + S6M1AR + stream x memory 1 address + register + 0xB0 + 0x20 + read-write + 0x00000000 + + + M1A + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S6FCR + S6FCR + stream x FIFO control register + 0xB4 + 0x20 + 0x00000021 + + + FEIE + FIFO error interrupt + enable + 7 + 1 + read-write + + + FS + FIFO status + 3 + 3 + read-only + + + DMDIS + Direct mode disable + 2 + 1 + read-write + + + FTH + FIFO threshold selection + 0 + 2 + read-write + + + + + S7CR + S7CR + stream x configuration + register + 0xB8 + 0x20 + read-write + 0x00000000 + + + CHSEL + Channel selection + 25 + 3 + + + MBURST + Memory burst transfer + configuration + 23 + 2 + + + PBURST + Peripheral burst transfer + configuration + 21 + 2 + + + ACK + ACK + 20 + 1 + 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peripheral address + register + 0xC0 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + S7M0AR + S7M0AR + stream x memory 0 address + register + 0xC4 + 0x20 + read-write + 0x00000000 + + + M0A + Memory 0 address + 0 + 32 + + + + + S7M1AR + S7M1AR + stream x memory 1 address + register + 0xC8 + 0x20 + read-write + 0x00000000 + + + M1A + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S7FCR + S7FCR + stream x FIFO control register + 0xCC + 0x20 + 0x00000021 + + + FEIE + FIFO error interrupt + enable + 7 + 1 + read-write + + + FS + FIFO status + 3 + 3 + read-only + + + DMDIS + Direct mode disable + 2 + 1 + read-write + + + FTH + FIFO threshold selection + 0 + 2 + read-write + + + + + + + DMA1 + 0x40026000 + + DMA1_Stream0 + DMA1 Stream0 global interrupt + 11 + + + DMA1_Stream1 + DMA1 Stream1 global interrupt + 12 + + + DMA1_Stream2 + DMA1 Stream2 global interrupt + 13 + + + DMA1_Stream3 + DMA1 Stream3 global interrupt + 14 + + + DMA1_Stream4 + DMA1 Stream4 global interrupt + 15 + + + DMA1_Stream5 + DMA1 Stream5 global interrupt + 16 + + + DMA1_Stream6 + DMA1 Stream6 global interrupt + 17 + + + DMA1_Stream7 + DMA1 Stream7 global interrupt + 47 + + + + RCC + Reset and clock control + RCC + 0x40023800 + + 0x0 + 0x400 + registers + + + RCC + RCC global interrupt + 5 + + + + CR + CR + clock control register + 0x0 + 0x20 + 0x00000083 + + + PLLI2SRDY + PLLI2S clock ready flag + 27 + 1 + read-only + + + PLLI2SON + PLLI2S enable + 26 + 1 + read-write + + + PLLRDY + Main PLL (PLL) clock ready + flag + 25 + 1 + read-only + + + PLLON + Main PLL (PLL) enable + 24 + 1 + read-write + + + CSSON + Clock security system + enable + 19 + 1 + read-write + + + HSEBYP + HSE clock bypass + 18 + 1 + read-write + + + HSERDY + HSE clock ready flag + 17 + 1 + read-only + + + HSEON + HSE clock enable + 16 + 1 + read-write + + + HSICAL + Internal high-speed clock + calibration + 8 + 8 + read-only + + + HSITRIM + Internal high-speed clock + trimming + 3 + 5 + read-write + + + HSIRDY + Internal high-speed clock ready + flag + 1 + 1 + read-only + + + HSION + Internal high-speed clock + enable + 0 + 1 + read-write + + + + + PLLCFGR + PLLCFGR + PLL configuration register + 0x4 + 0x20 + read-write + 0x24003010 + + + PLLQ3 + Main PLL (PLL) division factor for USB + OTG FS, SDIO and random number generator + clocks + 27 + 1 + + + PLLQ2 + Main PLL (PLL) division factor for USB + OTG FS, SDIO and random number generator + clocks + 26 + 1 + + + PLLQ1 + Main PLL (PLL) division factor for USB + OTG FS, SDIO and random number generator + clocks + 25 + 1 + + + PLLQ0 + Main PLL (PLL) division factor for USB + OTG FS, SDIO and random number generator + clocks + 24 + 1 + + + PLLSRC + Main PLL(PLL) and audio PLL (PLLI2S) + entry clock source + 22 + 1 + + + PLLP1 + Main PLL (PLL) division factor for main + system clock + 17 + 1 + + + PLLP0 + Main PLL (PLL) division factor for main + system clock + 16 + 1 + + + PLLN8 + Main PLL (PLL) multiplication factor for + VCO + 14 + 1 + + + PLLN7 + Main PLL (PLL) multiplication factor for + VCO + 13 + 1 + + + PLLN6 + Main PLL (PLL) multiplication factor for + VCO + 12 + 1 + + + PLLN5 + Main PLL (PLL) multiplication factor for + VCO + 11 + 1 + + + PLLN4 + Main PLL (PLL) multiplication factor for + VCO + 10 + 1 + + + PLLN3 + Main PLL (PLL) multiplication factor for + VCO + 9 + 1 + + + PLLN2 + Main PLL (PLL) multiplication factor for + VCO + 8 + 1 + + + PLLN1 + Main PLL (PLL) multiplication factor for + VCO + 7 + 1 + + + PLLN0 + Main PLL (PLL) multiplication factor for + VCO + 6 + 1 + + + PLLM5 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 5 + 1 + + + PLLM4 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 4 + 1 + + + PLLM3 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 3 + 1 + + + PLLM2 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 2 + 1 + + + PLLM1 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 1 + 1 + + + PLLM0 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 0 + 1 + + + + + CFGR + CFGR + clock configuration register + 0x8 + 0x20 + 0x00000000 + + + MCO2 + Microcontroller clock output + 2 + 30 + 2 + read-write + + + MCO2PRE + MCO2 prescaler + 27 + 3 + read-write + + + MCO1PRE + MCO1 prescaler + 24 + 3 + read-write + + + I2SSRC + I2S clock selection + 23 + 1 + read-write + + + MCO1 + Microcontroller clock output + 1 + 21 + 2 + read-write + + + RTCPRE + HSE division factor for RTC + clock + 16 + 5 + read-write + + + PPRE2 + APB high-speed prescaler + (APB2) + 13 + 3 + read-write + + + PPRE1 + APB Low speed prescaler + (APB1) + 10 + 3 + read-write + + + HPRE + AHB prescaler + 4 + 4 + read-write + + + SWS1 + System clock switch status + 3 + 1 + read-only + + + SWS0 + System clock switch status + 2 + 1 + read-only + + + SW1 + System clock switch + 1 + 1 + read-write + + + SW0 + System clock switch + 0 + 1 + read-write + + + + + CIR + CIR + clock interrupt register + 0xC + 0x20 + 0x00000000 + + + CSSC + Clock security system interrupt + clear + 23 + 1 + write-only + + + PLLI2SRDYC + PLLI2S ready interrupt + clear + 21 + 1 + write-only + + + PLLRDYC + Main PLL(PLL) ready interrupt + clear + 20 + 1 + write-only + + + HSERDYC + HSE ready interrupt clear + 19 + 1 + write-only + + + HSIRDYC + HSI ready interrupt clear + 18 + 1 + write-only + + + LSERDYC + LSE ready interrupt clear + 17 + 1 + write-only + + + LSIRDYC + LSI ready interrupt clear + 16 + 1 + write-only + + + PLLI2SRDYIE + PLLI2S ready interrupt + enable + 13 + 1 + read-write + + + PLLRDYIE + Main PLL (PLL) ready interrupt + enable + 12 + 1 + read-write + + + HSERDYIE + HSE ready interrupt enable + 11 + 1 + read-write + + + HSIRDYIE + HSI ready interrupt enable + 10 + 1 + read-write + + + LSERDYIE + LSE ready interrupt enable + 9 + 1 + read-write + + + LSIRDYIE + LSI ready interrupt enable + 8 + 1 + read-write + + + CSSF + Clock security system interrupt + flag + 7 + 1 + read-only + + + PLLI2SRDYF + PLLI2S ready interrupt + flag + 5 + 1 + read-only + + + PLLRDYF + Main PLL (PLL) ready interrupt + flag + 4 + 1 + read-only + + + HSERDYF + HSE ready interrupt flag + 3 + 1 + read-only + + + HSIRDYF + HSI ready interrupt flag + 2 + 1 + read-only + + + LSERDYF + LSE ready interrupt flag + 1 + 1 + read-only + + + LSIRDYF + LSI ready interrupt flag + 0 + 1 + read-only + + + + + AHB1RSTR + AHB1RSTR + AHB1 peripheral reset register + 0x10 + 0x20 + read-write + 0x00000000 + + + OTGHSRST + USB OTG HS module reset + 29 + 1 + + + ETHMACRST + Ethernet MAC reset + 25 + 1 + + + DMA2RST + DMA2 reset + 22 + 1 + + + DMA1RST + DMA2 reset + 21 + 1 + + + CRCRST + CRC reset + 12 + 1 + + + GPIOIRST + IO port I reset + 8 + 1 + + + GPIOHRST + IO port H reset + 7 + 1 + + + GPIOGRST + IO port G reset + 6 + 1 + + + GPIOFRST + IO port F reset + 5 + 1 + + + GPIOERST + IO port E reset + 4 + 1 + + + GPIODRST + IO port D reset + 3 + 1 + + + GPIOCRST + IO port C reset + 2 + 1 + + + GPIOBRST + IO port B reset + 1 + 1 + + + GPIOARST + IO port A reset + 0 + 1 + + + + + AHB2RSTR + AHB2RSTR + AHB2 peripheral reset register + 0x14 + 0x20 + read-write + 0x00000000 + + + OTGFSRST + USB OTG FS module reset + 7 + 1 + + + RNGRST + Random number generator module + reset + 6 + 1 + + + DCMIRST + Camera interface reset + 0 + 1 + + + + + AHB3RSTR + AHB3RSTR + AHB3 peripheral reset register + 0x18 + 0x20 + read-write + 0x00000000 + + + FSMCRST + Flexible static memory controller module + reset + 0 + 1 + + + + + APB1RSTR + APB1RSTR + APB1 peripheral reset register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACRST + DAC reset + 29 + 1 + + + PWRRST + Power interface reset + 28 + 1 + + + CAN2RST + CAN2 reset + 26 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + I2C3RST + I2C3 reset + 23 + 1 + + + I2C2RST + I2C 2 reset + 22 + 1 + + + I2C1RST + I2C 1 reset + 21 + 1 + + + UART5RST + USART 5 reset + 20 + 1 + + + UART4RST + USART 4 reset + 19 + 1 + + + UART3RST + USART 3 reset + 18 + 1 + + + UART2RST + USART 2 reset + 17 + 1 + + + SPI3RST + SPI 3 reset + 15 + 1 + + + SPI2RST + SPI 2 reset + 14 + 1 + + + WWDGRST + Window watchdog reset + 11 + 1 + + + TIM14RST + TIM14 reset + 8 + 1 + + + TIM13RST + TIM13 reset + 7 + 1 + + + TIM12RST + TIM12 reset + 6 + 1 + + + TIM7RST + TIM7 reset + 5 + 1 + + + TIM6RST + TIM6 reset + 4 + 1 + + + TIM5RST + TIM5 reset + 3 + 1 + + + TIM4RST + TIM4 reset + 2 + 1 + + + TIM3RST + TIM3 reset + 1 + 1 + + + TIM2RST + TIM2 reset + 0 + 1 + + + + + APB2RSTR + APB2RSTR + APB2 peripheral reset register + 0x24 + 0x20 + read-write + 0x00000000 + + + TIM11RST + TIM11 reset + 18 + 1 + + + TIM10RST + TIM10 reset + 17 + 1 + + + TIM9RST + TIM9 reset + 16 + 1 + + + SYSCFGRST + System configuration controller + reset + 14 + 1 + + + SPI1RST + SPI 1 reset + 12 + 1 + + + SDIORST + SDIO reset + 11 + 1 + + + ADCRST + ADC interface reset (common to all + ADCs) + 8 + 1 + + + USART6RST + USART6 reset + 5 + 1 + + + USART1RST + USART1 reset + 4 + 1 + + + TIM8RST + TIM8 reset + 1 + 1 + + + TIM1RST + TIM1 reset + 0 + 1 + + + + + AHB1ENR + AHB1ENR + AHB1 peripheral clock register + 0x30 + 0x20 + read-write + 0x00100000 + + + OTGHSULPIEN + USB OTG HSULPI clock + enable + 30 + 1 + + + OTGHSEN + USB OTG HS clock enable + 29 + 1 + + + ETHMACPTPEN + Ethernet PTP clock enable + 28 + 1 + + + ETHMACRXEN + Ethernet Reception clock + enable + 27 + 1 + + + ETHMACTXEN + Ethernet Transmission clock + enable + 26 + 1 + + + ETHMACEN + Ethernet MAC clock enable + 25 + 1 + + + DMA2EN + DMA2 clock enable + 22 + 1 + + + DMA1EN + DMA1 clock enable + 21 + 1 + + + BKPSRAMEN + Backup SRAM interface clock + enable + 18 + 1 + + + CRCEN + CRC clock enable + 12 + 1 + + + GPIOIEN + IO port I clock enable + 8 + 1 + + + GPIOHEN + IO port H clock enable + 7 + 1 + + + GPIOGEN + IO port G clock enable + 6 + 1 + + + GPIOFEN + IO port F clock enable + 5 + 1 + + + GPIOEEN + IO port E clock enable + 4 + 1 + + + GPIODEN + IO port D clock enable + 3 + 1 + + + GPIOCEN + IO port C clock enable + 2 + 1 + + + GPIOBEN + IO port B clock enable + 1 + 1 + + + GPIOAEN + IO port A clock enable + 0 + 1 + + + + + AHB2ENR + AHB2ENR + AHB2 peripheral clock enable + register + 0x34 + 0x20 + read-write + 0x00000000 + + + OTGFSEN + USB OTG FS clock enable + 7 + 1 + + + RNGEN + Random number generator clock + enable + 6 + 1 + + + DCMIEN + Camera interface enable + 0 + 1 + + + + + AHB3ENR + AHB3ENR + AHB3 peripheral clock enable + register + 0x38 + 0x20 + read-write + 0x00000000 + + + FSMCEN + Flexible static memory controller module + clock enable + 0 + 1 + + + + + APB1ENR + APB1ENR + APB1 peripheral clock enable + register + 0x40 + 0x20 + read-write + 0x00000000 + + + DACEN + DAC interface clock enable + 29 + 1 + + + PWREN + Power interface clock + enable + 28 + 1 + + + CAN2EN + CAN 2 clock enable + 26 + 1 + + + CAN1EN + CAN 1 clock enable + 25 + 1 + + + I2C3EN + I2C3 clock enable + 23 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + UART5EN + UART5 clock enable + 20 + 1 + + + UART4EN + UART4 clock enable + 19 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + USART2EN + USART 2 clock enable + 17 + 1 + + + SPI3EN + SPI3 clock enable + 15 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + WWDGEN + Window watchdog clock + enable + 11 + 1 + + + TIM14EN + TIM14 clock enable + 8 + 1 + + + TIM13EN + TIM13 clock enable + 7 + 1 + + + TIM12EN + TIM12 clock enable + 6 + 1 + + + TIM7EN + TIM7 clock enable + 5 + 1 + + + TIM6EN + TIM6 clock enable + 4 + 1 + + + TIM5EN + TIM5 clock enable + 3 + 1 + + + TIM4EN + TIM4 clock enable + 2 + 1 + + + TIM3EN + TIM3 clock enable + 1 + 1 + + + TIM2EN + TIM2 clock enable + 0 + 1 + + + + + APB2ENR + APB2ENR + APB2 peripheral clock enable + register + 0x44 + 0x20 + read-write + 0x00000000 + + + TIM11EN + TIM11 clock enable + 18 + 1 + + + TIM10EN + TIM10 clock enable + 17 + 1 + + + TIM9EN + TIM9 clock enable + 16 + 1 + + + SYSCFGEN + System configuration controller clock + enable + 14 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + SDIOEN + SDIO clock enable + 11 + 1 + + + ADC3EN + ADC3 clock enable + 10 + 1 + + + ADC2EN + ADC2 clock enable + 9 + 1 + + + ADC1EN + ADC1 clock enable + 8 + 1 + + + USART6EN + USART6 clock enable + 5 + 1 + + + USART1EN + USART1 clock enable + 4 + 1 + + + TIM8EN + TIM8 clock enable + 1 + 1 + + + TIM1EN + TIM1 clock enable + 0 + 1 + + + + + AHB1LPENR + AHB1LPENR + AHB1 peripheral clock enable in low power + mode register + 0x50 + 0x20 + read-write + 0x7E6791FF + + + OTGHSULPILPEN + USB OTG HS ULPI clock enable during + Sleep mode + 30 + 1 + + + OTGHSLPEN + USB OTG HS clock enable during Sleep + mode + 29 + 1 + + + ETHMACPTPLPEN + Ethernet PTP clock enable during Sleep + mode + 28 + 1 + + + ETHMACRXLPEN + Ethernet reception clock enable during + Sleep mode + 27 + 1 + + + ETHMACTXLPEN + Ethernet transmission clock enable + during Sleep mode + 26 + 1 + + + ETHMACLPEN + Ethernet MAC clock enable during Sleep + mode + 25 + 1 + + + DMA2LPEN + DMA2 clock enable during Sleep + mode + 22 + 1 + + + DMA1LPEN + DMA1 clock enable during Sleep + mode + 21 + 1 + + + BKPSRAMLPEN + Backup SRAM interface clock enable + during Sleep mode + 18 + 1 + + + SRAM2LPEN + SRAM 2 interface clock enable during + Sleep mode + 17 + 1 + + + SRAM1LPEN + SRAM 1interface clock enable during + Sleep mode + 16 + 1 + + + FLITFLPEN + Flash interface clock enable during + Sleep mode + 15 + 1 + + + CRCLPEN + CRC clock enable during Sleep + mode + 12 + 1 + + + GPIOILPEN + IO port I clock enable during Sleep + mode + 8 + 1 + + + GPIOHLPEN + IO port H clock enable during Sleep + mode + 7 + 1 + + + GPIOGLPEN + IO port G clock enable during Sleep + mode + 6 + 1 + + + GPIOFLPEN + IO port F clock enable during Sleep + mode + 5 + 1 + + + GPIOELPEN + IO port E clock enable during Sleep + mode + 4 + 1 + + + GPIODLPEN + IO port D clock enable during Sleep + mode + 3 + 1 + + + GPIOCLPEN + IO port C clock enable during Sleep + mode + 2 + 1 + + + GPIOBLPEN + IO port B clock enable during Sleep + mode + 1 + 1 + + + GPIOALPEN + IO port A clock enable during sleep + mode + 0 + 1 + + + + + AHB2LPENR + AHB2LPENR + AHB2 peripheral clock enable in low power + mode register + 0x54 + 0x20 + read-write + 0x000000F1 + + + OTGFSLPEN + USB OTG FS clock enable during Sleep + mode + 7 + 1 + + + RNGLPEN + Random number generator clock enable + during Sleep mode + 6 + 1 + + + DCMILPEN + Camera interface enable during Sleep + mode + 0 + 1 + + + + + AHB3LPENR + AHB3LPENR + AHB3 peripheral clock enable in low power + mode register + 0x58 + 0x20 + read-write + 0x00000001 + + + FSMCLPEN + Flexible static memory controller module + clock enable during Sleep mode + 0 + 1 + + + + + APB1LPENR + APB1LPENR + APB1 peripheral clock enable in low power + mode register + 0x60 + 0x20 + read-write + 0x36FEC9FF + + + DACLPEN + DAC interface clock enable during Sleep + mode + 29 + 1 + + + PWRLPEN + Power interface clock enable during + Sleep mode + 28 + 1 + + + CAN2LPEN + CAN 2 clock enable during Sleep + mode + 26 + 1 + + + CAN1LPEN + CAN 1 clock enable during Sleep + mode + 25 + 1 + + + I2C3LPEN + I2C3 clock enable during Sleep + mode + 23 + 1 + + + I2C2LPEN + I2C2 clock enable during Sleep + mode + 22 + 1 + + + I2C1LPEN + I2C1 clock enable during Sleep + mode + 21 + 1 + + + UART5LPEN + UART5 clock enable during Sleep + mode + 20 + 1 + + + UART4LPEN + UART4 clock enable during Sleep + mode + 19 + 1 + + + USART3LPEN + USART3 clock enable during Sleep + mode + 18 + 1 + + + USART2LPEN + USART2 clock enable during Sleep + mode + 17 + 1 + + + SPI3LPEN + SPI3 clock enable during Sleep + mode + 15 + 1 + + + SPI2LPEN + SPI2 clock enable during Sleep + mode + 14 + 1 + + + WWDGLPEN + Window watchdog clock enable during + Sleep mode + 11 + 1 + + + TIM14LPEN + TIM14 clock enable during Sleep + mode + 8 + 1 + + + TIM13LPEN + TIM13 clock enable during Sleep + mode + 7 + 1 + + + TIM12LPEN + TIM12 clock enable during Sleep + mode + 6 + 1 + + + TIM7LPEN + TIM7 clock enable during Sleep + mode + 5 + 1 + + + TIM6LPEN + TIM6 clock enable during Sleep + mode + 4 + 1 + + + TIM5LPEN + TIM5 clock enable during Sleep + mode + 3 + 1 + + + TIM4LPEN + TIM4 clock enable during Sleep + mode + 2 + 1 + + + TIM3LPEN + TIM3 clock enable during Sleep + mode + 1 + 1 + + + TIM2LPEN + TIM2 clock enable during Sleep + mode + 0 + 1 + + + + + APB2LPENR + APB2LPENR + APB2 peripheral clock enabled in low power + mode register + 0x64 + 0x20 + read-write + 0x00075F33 + + + TIM11LPEN + TIM11 clock enable during Sleep + mode + 18 + 1 + + + TIM10LPEN + TIM10 clock enable during Sleep + mode + 17 + 1 + + + TIM9LPEN + TIM9 clock enable during sleep + mode + 16 + 1 + + + SYSCFGLPEN + System configuration controller clock + enable during Sleep mode + 14 + 1 + + + SPI1LPEN + SPI 1 clock enable during Sleep + mode + 12 + 1 + + + SDIOLPEN + SDIO clock enable during Sleep + mode + 11 + 1 + + + ADC3LPEN + ADC 3 clock enable during Sleep + mode + 10 + 1 + + + ADC2LPEN + ADC2 clock enable during Sleep + mode + 9 + 1 + + + ADC1LPEN + ADC1 clock enable during Sleep + mode + 8 + 1 + + + USART6LPEN + USART6 clock enable during Sleep + mode + 5 + 1 + + + USART1LPEN + USART1 clock enable during Sleep + mode + 4 + 1 + + + TIM8LPEN + TIM8 clock enable during Sleep + mode + 1 + 1 + + + TIM1LPEN + TIM1 clock enable during Sleep + mode + 0 + 1 + + + + + BDCR + BDCR + Backup domain control register + 0x70 + 0x20 + 0x00000000 + + + BDRST + Backup domain software + reset + 16 + 1 + read-write + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + RTCSEL1 + RTC clock source selection + 9 + 1 + read-write + + + RTCSEL0 + RTC clock source selection + 8 + 1 + read-write + + + LSEBYP + External low-speed oscillator + bypass + 2 + 1 + read-write + + + LSERDY + External low-speed oscillator + ready + 1 + 1 + read-only + + + LSEON + External low-speed oscillator + enable + 0 + 1 + read-write + + + + + CSR + CSR + clock control & status + register + 0x74 + 0x20 + 0x0E000000 + + + LPWRRSTF + Low-power reset flag + 31 + 1 + read-write + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + read-write + + + WDGRSTF + Independent watchdog reset + flag + 29 + 1 + read-write + + + SFTRSTF + Software reset flag + 28 + 1 + read-write + + + PORRSTF + POR/PDR reset flag + 27 + 1 + read-write + + + PADRSTF + PIN reset flag + 26 + 1 + read-write + + + BORRSTF + BOR reset flag + 25 + 1 + read-write + + + RMVF + Remove reset flag + 24 + 1 + read-write + + + LSIRDY + Internal low-speed oscillator + ready + 1 + 1 + read-only + + + LSION + Internal low-speed oscillator + enable + 0 + 1 + read-write + + + + + SSCGR + SSCGR + spread spectrum clock generation + register + 0x80 + 0x20 + read-write + 0x00000000 + + + SSCGEN + Spread spectrum modulation + enable + 31 + 1 + + + SPREADSEL + Spread Select + 30 + 1 + + + INCSTEP + Incrementation step + 13 + 15 + + + MODPER + Modulation period + 0 + 13 + + + + + PLLI2SCFGR + PLLI2SCFGR + PLLI2S configuration register + 0x84 + 0x20 + read-write + 0x20003000 + + + PLLI2SRx + PLLI2S division factor for I2S + clocks + 28 + 3 + + + PLLI2SNx + PLLI2S multiplication factor for + VCO + 6 + 9 + + + + + + + GPIOI + General-purpose I/Os + GPIO + 0x40022000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0x00000000 + + + MODER15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = + 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = + 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = + 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = + 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = + 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = + 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = + 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = + 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = + 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = + 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = + 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = + 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = + 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = + 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = + 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = + 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = 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+ 1 + + + LCK5 + Port x lock bit y (y= + 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= + 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= + 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= + 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= + 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= + 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x + bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x + bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x + bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x + bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x + bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x + bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x + bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x + bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x + bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x + bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x + bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x + bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x + bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x + bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x + bit y (y = 8..15) + 0 + 4 + + + + + + + GPIOA + General-purpose I/Os + GPIO + 0x40020000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xA8000000 + + + MODER15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = + 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = + 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = + 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = + 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = + 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = + 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = + 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = + 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = + 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = + 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = + 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = + 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = + 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = + 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = + 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = + 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x64000000 + + + PUPDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = + 0..15) + 15 + 1 + + + IDR14 + Port input data (y = + 0..15) + 14 + 1 + + + IDR13 + Port input data (y = + 0..15) + 13 + 1 + + + IDR12 + Port input data (y = + 0..15) + 12 + 1 + + + IDR11 + Port input data (y = + 0..15) + 11 + 1 + + + IDR10 + Port input data (y = + 0..15) + 10 + 1 + + + IDR9 + Port input data (y = + 0..15) + 9 + 1 + + + IDR8 + Port input data (y = + 0..15) + 8 + 1 + + + IDR7 + Port input data (y = + 0..15) + 7 + 1 + + + IDR6 + Port input data (y = + 0..15) + 6 + 1 + + + IDR5 + Port input data (y = + 0..15) + 5 + 1 + + + IDR4 + Port input data (y = + 0..15) + 4 + 1 + + + IDR3 + Port input data (y = + 0..15) + 3 + 1 + + + IDR2 + Port input data (y = + 0..15) + 2 + 1 + + + IDR1 + Port input data (y = + 0..15) + 1 + 1 + + + IDR0 + Port input data (y = + 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = + 0..15) + 15 + 1 + + + ODR14 + Port output data (y = + 0..15) + 14 + 1 + + + ODR13 + Port output data (y = + 0..15) + 13 + 1 + + + ODR12 + Port output data (y = + 0..15) + 12 + 1 + + + ODR11 + Port output data (y = + 0..15) + 11 + 1 + + + ODR10 + Port output data (y = + 0..15) + 10 + 1 + + + ODR9 + Port output data (y = + 0..15) + 9 + 1 + + + ODR8 + Port output data (y = + 0..15) + 8 + 1 + + + ODR7 + Port output data (y = + 0..15) + 7 + 1 + + + ODR6 + Port output data (y = + 0..15) + 6 + 1 + + + ODR5 + Port output data (y = + 0..15) + 5 + 1 + + + ODR4 + Port output data (y = + 0..15) + 4 + 1 + + + ODR3 + Port output data (y = + 0..15) + 3 + 1 + + + ODR2 + Port output data (y = + 0..15) + 2 + 1 + + + ODR1 + Port output data (y = + 0..15) + 1 + 1 + + + ODR0 + Port output data (y = + 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = + 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = + 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = + 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = + 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = + 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = + 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = + 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = + 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = + 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = + 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = + 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = + 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = + 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = + 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = + 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= + 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= + 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= + 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= + 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= + 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= + 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= + 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= + 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= + 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= + 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= + 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= + 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= + 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= + 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= + 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= + 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= + 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= + 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= + 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= + 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= + 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= + 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= + 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= + 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= + 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x + bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x + bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x + bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x + bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x + bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x + bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x + bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x + bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x + bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x + bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x + bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x + bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x + bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x + bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x + bit y (y = 8..15) + 0 + 4 + + + + + + + SYSCFG + System configuration controller + SYSCFG + 0x40013800 + + 0x0 + 0x400 + registers + + + + MEMRM + MEMRM + memory remap register + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MODE + MEM_MODE + 0 + 2 + + + + + PMC + PMC + peripheral mode configuration + register + 0x4 + 0x20 + read-write + 0x00000000 + + + MII_RMII_SEL + Ethernet PHY interface + selection + 23 + 1 + + + + + EXTICR1 + EXTICR1 + external interrupt configuration register + 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXTI3 + EXTI x configuration (x = 0 to + 3) + 12 + 4 + + + EXTI2 + EXTI x configuration (x = 0 to + 3) + 8 + 4 + + + EXTI1 + EXTI x configuration (x = 0 to + 3) + 4 + 4 + + + EXTI0 + EXTI x configuration (x = 0 to + 3) + 0 + 4 + + + + + EXTICR2 + EXTICR2 + external interrupt configuration register + 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXTI7 + EXTI x configuration (x = 4 to + 7) + 12 + 4 + + + EXTI6 + EXTI x configuration (x = 4 to + 7) + 8 + 4 + + + EXTI5 + EXTI x configuration (x = 4 to + 7) + 4 + 4 + + + EXTI4 + EXTI x configuration (x = 4 to + 7) + 0 + 4 + + + + + EXTICR3 + EXTICR3 + external interrupt configuration register + 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXTI11 + EXTI x configuration (x = 8 to + 11) + 12 + 4 + + + EXTI10 + EXTI10 + 8 + 4 + + + EXTI9 + EXTI x configuration (x = 8 to + 11) + 4 + 4 + + + EXTI8 + EXTI x configuration (x = 8 to + 11) + 0 + 4 + + + + + EXTICR4 + EXTICR4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXTI15 + EXTI x configuration (x = 12 to + 15) + 12 + 4 + + + EXTI14 + EXTI x configuration (x = 12 to + 15) + 8 + 4 + + + EXTI13 + EXTI x configuration (x = 12 to + 15) + 4 + 4 + + + EXTI12 + EXTI x configuration (x = 12 to + 15) + 0 + 4 + + + + + CMPCR + CMPCR + Compensation cell control + register + 0x20 + 0x20 + read-only + 0x00000000 + + + READY + READY + 8 + 1 + + + CMP_PD + Compensation cell + power-down + 0 + 1 + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + BIDIMODE + Bidirectional data mode + enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional + mode + 14 + 1 + + + CRCEN + Hardware CRC calculation + enable + 13 + 1 + + + CRCNEXT + CRC transfer next + 12 + 1 + + + DFF + Data frame format + 11 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave select + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TXEIE + Tx buffer empty interrupt + enable + 7 + 1 + + + RXNEIE + RX buffer not empty interrupt + enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + FRF + Frame format + 4 + 1 + + + SSOE + SS output enable + 2 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + 0x0002 + + + TIFRFE + TI frame format error + 8 + 1 + read-only + + + BSY + Busy flag + 7 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + MODF + Mode fault + 5 + 1 + read-only + + + CRCERR + CRC error flag + 4 + 1 + read-write + + + UDR + Underrun flag + 3 + 1 + read-only + + + CHSIDE + Channel side + 2 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x0000 + + + DR + Data register + 0 + 16 + + + + + CRCPR + CRCPR + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + + + RXCRCR + RXCRCR + RX CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RxCRC + Rx CRC register + 0 + 16 + + + + + TXCRCR + TXCRCR + TX CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TxCRC + Tx CRC register + 0 + 16 + + + + + I2SCFGR + I2SCFGR + I2S configuration register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMOD + I2S mode selection + 11 + 1 + + + I2SE + I2S Enable + 10 + 1 + + + I2SCFG + I2S configuration mode + 8 + 2 + + + PCMSYNC + PCM frame synchronization + 7 + 1 + + + I2SSTD + I2S standard selection + 4 + 2 + + + CKPOL + Steady state clock + polarity + 3 + 1 + + + DATLEN + Data length to be + transferred + 1 + 2 + + + CHLEN + Channel length (number of bits per audio + channel) + 0 + 1 + + + + + I2SPR + I2SPR + I2S prescaler register + 0x20 + 0x20 + read-write + 00000010 + + + MCKOE + Master clock output enable + 9 + 1 + + + ODD + Odd factor for the + prescaler + 8 + 1 + + + I2SDIV + I2S Linear prescaler + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 51 + + + + I2S2ext + 0x40003400 + + + I2S3ext + 0x40004000 + + + SDIO + Secure digital input/output + interface + SDIO + 0x40012C00 + + 0x0 + 0x400 + registers + + + SDIO + SDIO global interrupt + 49 + + + + POWER + POWER + power control register + 0x0 + 0x20 + read-write + 0x00000000 + + + PWRCTRL + PWRCTRL + 0 + 2 + + + + + CLKCR + CLKCR + SDI clock control register + 0x4 + 0x20 + read-write + 0x00000000 + + + HWFC_EN + HW Flow Control enable + 14 + 1 + + + NEGEDGE + SDIO_CK dephasing selection + bit + 13 + 1 + + + WIDBUS + Wide bus mode enable bit + 11 + 2 + + + BYPASS + Clock divider bypass enable + bit + 10 + 1 + + + PWRSAV + Power saving configuration + bit + 9 + 1 + + + CLKEN + Clock enable bit + 8 + 1 + + + CLKDIV + Clock divide factor + 0 + 8 + + + + + ARG + ARG + argument register + 0x8 + 0x20 + read-write + 0x00000000 + + + CMDARG + Command argument + 0 + 32 + + + + + CMD + CMD + command register + 0xC + 0x20 + read-write + 0x00000000 + + + CE_ATACMD + CE-ATA command + 14 + 1 + + + nIEN + not Interrupt Enable + 13 + 1 + + + ENCMDcompl + Enable CMD completion + 12 + 1 + + + SDIOSuspend + SD I/O suspend command + 11 + 1 + + + CPSMEN + Command path state machine (CPSM) Enable + bit + 10 + 1 + + + WAITPEND + CPSM Waits for ends of data transfer + (CmdPend internal signal). + 9 + 1 + + + WAITINT + CPSM waits for interrupt + request + 8 + 1 + + + WAITRESP + Wait for response bits + 6 + 2 + + + CMDINDEX + Command index + 0 + 6 + + + + + RESPCMD + RESPCMD + command response register + 0x10 + 0x20 + read-only + 0x00000000 + + + RESPCMD + Response command index + 0 + 6 + + + + + RESP1 + RESP1 + response 1..4 register + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS1 + see Table 132. + 0 + 32 + + + + + RESP2 + RESP2 + response 1..4 register + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS2 + see Table 132. + 0 + 32 + + + + + RESP3 + RESP3 + response 1..4 register + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTATUS3 + see Table 132. + 0 + 32 + + + + + RESP4 + RESP4 + response 1..4 register + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS4 + see Table 132. + 0 + 32 + + + + + DTIMER + DTIMER + data timer register + 0x24 + 0x20 + read-write + 0x00000000 + + + DATATIME + Data timeout period + 0 + 32 + + + + + DLEN + DLEN + data length register + 0x28 + 0x20 + read-write + 0x00000000 + + + DATALENGTH + Data length value + 0 + 25 + + + + + DCTRL + DCTRL + data control register + 0x2C + 0x20 + read-write + 0x00000000 + + + SDIOEN + SD I/O enable functions + 11 + 1 + + + RWMOD + Read wait mode + 10 + 1 + + + RWSTOP + Read wait stop + 9 + 1 + + + RWSTART + Read wait start + 8 + 1 + + + DBLOCKSIZE + Data block size + 4 + 4 + + + DMAEN + DMA enable bit + 3 + 1 + + + DTMODE + Data transfer mode selection 1: Stream + or SDIO multibyte data transfer. + 2 + 1 + + + DTDIR + Data transfer direction + selection + 1 + 1 + + + DTEN + DTEN + 0 + 1 + + + + + DCOUNT + DCOUNT + data counter register + 0x30 + 0x20 + read-only + 0x00000000 + + + DATACOUNT + Data count value + 0 + 25 + + + + + STA + STA + status register + 0x34 + 0x20 + read-only + 0x00000000 + + + CEATAEND + CE-ATA command completion signal + received for CMD61 + 23 + 1 + + + SDIOIT + SDIO interrupt received + 22 + 1 + + + RXDAVL + Data available in receive + FIFO + 21 + 1 + + + TXDAVL + Data available in transmit + FIFO + 20 + 1 + + + RXFIFOE + Receive FIFO empty + 19 + 1 + + + TXFIFOE + Transmit FIFO empty + 18 + 1 + + + RXFIFOF + Receive FIFO full + 17 + 1 + + + TXFIFOF + Transmit FIFO full + 16 + 1 + + + RXFIFOHF + Receive FIFO half full: there are at + least 8 words in the FIFO + 15 + 1 + + + TXFIFOHE + Transmit FIFO half empty: at least 8 + words can be written into the FIFO + 14 + 1 + + + RXACT + Data receive in progress + 13 + 1 + + + TXACT + Data transmit in progress + 12 + 1 + + + CMDACT + Command transfer in + progress + 11 + 1 + + + DBCKEND + Data block sent/received (CRC check + passed) + 10 + 1 + + + STBITERR + Start bit not detected on all data + signals in wide bus mode + 9 + 1 + + + DATAEND + Data end (data counter, SDIDCOUNT, is + zero) + 8 + 1 + + + CMDSENT + Command sent (no response + required) + 7 + 1 + + + CMDREND + Command response received (CRC check + passed) + 6 + 1 + + + RXOVERR + Received FIFO overrun + error + 5 + 1 + + + TXUNDERR + Transmit FIFO underrun + error + 4 + 1 + + + DTIMEOUT + Data timeout + 3 + 1 + + + CTIMEOUT + Command response timeout + 2 + 1 + + + DCRCFAIL + Data block sent/received (CRC check + failed) + 1 + 1 + + + CCRCFAIL + Command response received (CRC check + failed) + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x38 + 0x20 + read-write + 0x00000000 + + + CEATAENDC + CEATAEND flag clear bit + 23 + 1 + + + SDIOITC + SDIOIT flag clear bit + 22 + 1 + + + DBCKENDC + DBCKEND flag clear bit + 10 + 1 + + + STBITERRC + STBITERR flag clear bit + 9 + 1 + + + DATAENDC + DATAEND flag clear bit + 8 + 1 + + + CMDSENTC + CMDSENT flag clear bit + 7 + 1 + + + CMDRENDC + CMDREND flag clear bit + 6 + 1 + + + RXOVERRC + RXOVERR flag clear bit + 5 + 1 + + + TXUNDERRC + TXUNDERR flag clear bit + 4 + 1 + + + DTIMEOUTC + DTIMEOUT flag clear bit + 3 + 1 + + + CTIMEOUTC + CTIMEOUT flag clear bit + 2 + 1 + + + DCRCFAILC + DCRCFAIL flag clear bit + 1 + 1 + + + CCRCFAILC + CCRCFAIL flag clear bit + 0 + 1 + + + + + MASK + MASK + mask register + 0x3C + 0x20 + read-write + 0x00000000 + + + CEATAENDIE + CE-ATA command completion signal + received interrupt enable + 23 + 1 + + + SDIOITIE + SDIO mode interrupt received interrupt + enable + 22 + 1 + + + RXDAVLIE + Data available in Rx FIFO interrupt + enable + 21 + 1 + + + TXDAVLIE + Data available in Tx FIFO interrupt + enable + 20 + 1 + + + RXFIFOEIE + Rx FIFO empty interrupt + enable + 19 + 1 + + + TXFIFOEIE + Tx FIFO empty interrupt + enable + 18 + 1 + + + RXFIFOFIE + Rx FIFO full interrupt + enable + 17 + 1 + + + TXFIFOFIE + Tx FIFO full interrupt + enable + 16 + 1 + + + RXFIFOHFIE + Rx FIFO half full interrupt + enable + 15 + 1 + + + TXFIFOHEIE + Tx FIFO half empty interrupt + enable + 14 + 1 + + + RXACTIE + Data receive acting interrupt + enable + 13 + 1 + + + TXACTIE + Data transmit acting interrupt + enable + 12 + 1 + + + CMDACTIE + Command acting interrupt + enable + 11 + 1 + + + DBCKENDIE + Data block end interrupt + enable + 10 + 1 + + + STBITERRIE + Start bit error interrupt + enable + 9 + 1 + + + DATAENDIE + Data end interrupt enable + 8 + 1 + + + CMDSENTIE + Command sent interrupt + enable + 7 + 1 + + + CMDRENDIE + Command response received interrupt + enable + 6 + 1 + + + RXOVERRIE + Rx FIFO overrun error interrupt + enable + 5 + 1 + + + TXUNDERRIE + Tx FIFO underrun error interrupt + enable + 4 + 1 + + + DTIMEOUTIE + Data timeout interrupt + enable + 3 + 1 + + + CTIMEOUTIE + Command timeout interrupt + enable + 2 + 1 + + + DCRCFAILIE + Data CRC fail interrupt + enable + 1 + 1 + + + CCRCFAILIE + Command CRC fail interrupt + enable + 0 + 1 + + + + + FIFOCNT + FIFOCNT + FIFO counter register + 0x48 + 0x20 + read-only + 0x00000000 + + + FIFOCOUNT + Remaining number of words to be written + to or read from the FIFO. + 0 + 24 + + + + + FIFO + FIFO + data FIFO register + 0x80 + 0x20 + read-write + 0x00000000 + + + FIFOData + Receive and transmit FIFO + data + 0 + 32 + + + + + + + ADC1 + Analog-to-digital converter + ADC + 0x40012000 + + 0x0 + 0x400 + registers + + + ADC + ADC1 global interrupt + 18 + + + + SR + SR + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OVR + Overrun + 5 + 1 + + + STRT + Regular channel start flag + 4 + 1 + + + JSTRT + Injected channel start + flag + 3 + 1 + + + JEOC + Injected channel end of + conversion + 2 + 1 + + + EOC + Regular channel end of + conversion + 1 + 1 + + + AWD + Analog watchdog flag + 0 + 1 + + + + + CR1 + CR1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OVRIE + Overrun interrupt enable + 26 + 1 + + + RES + Resolution + 24 + 2 + + + AWDEN + Analog watchdog enable on regular + channels + 23 + 1 + + + JAWDEN + Analog watchdog enable on injected + channels + 22 + 1 + + + DISCNUM + Discontinuous mode channel + count + 13 + 3 + + + JDISCEN + Discontinuous mode on injected + channels + 12 + 1 + + + DISCEN + Discontinuous mode on regular + channels + 11 + 1 + + + JAUTO + Automatic injected group + conversion + 10 + 1 + + + AWDSGL + Enable the watchdog on a single channel + in scan mode + 9 + 1 + + + SCAN + Scan mode + 8 + 1 + + + JEOCIE + Interrupt enable for injected + channels + 7 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 6 + 1 + + + EOCIE + Interrupt enable for EOC + 5 + 1 + + + AWDCH + Analog watchdog channel select + bits + 0 + 5 + + + + + CR2 + CR2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + SWSTART + Start conversion of regular + channels + 30 + 1 + + + EXTEN + External trigger enable for regular + channels + 28 + 2 + + + EXTSEL + External event select for regular + group + 24 + 4 + + + JSWSTART + Start conversion of injected + channels + 22 + 1 + + + JEXTEN + External trigger enable for injected + channels + 20 + 2 + + + JEXTSEL + External event select for injected + group + 16 + 4 + + + ALIGN + Data alignment + 11 + 1 + + + EOCS + End of conversion + selection + 10 + 1 + + + DDS + DMA disable selection (for single ADC + mode) + 9 + 1 + + + DMA + Direct memory access mode (for single + ADC mode) + 8 + 1 + + + CONT + Continuous conversion + 1 + 1 + + + ADON + A/D Converter ON / OFF + 0 + 1 + + + + + SMPR1 + SMPR1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + SMPx_x + Sample time bits + 0 + 32 + + + + + SMPR2 + SMPR2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + SMPx_x + Sample time bits + 0 + 32 + + + + + JOFR1 + JOFR1 + injected channel data offset register + x + 0x14 + 0x20 + read-write + 0x00000000 + + + JOFFSET1 + Data offset for injected channel + x + 0 + 12 + + + + + JOFR2 + JOFR2 + injected channel data offset register + x + 0x18 + 0x20 + read-write + 0x00000000 + + + JOFFSET2 + Data offset for injected channel + x + 0 + 12 + + + + + JOFR3 + JOFR3 + injected channel data offset register + x + 0x1C + 0x20 + read-write + 0x00000000 + + + JOFFSET3 + Data offset for injected channel + x + 0 + 12 + + + + + JOFR4 + JOFR4 + injected channel data offset register + x + 0x20 + 0x20 + read-write + 0x00000000 + + + JOFFSET4 + Data offset for injected channel + x + 0 + 12 + + + + + HTR + HTR + watchdog higher threshold + register + 0x24 + 0x20 + read-write + 0x00000FFF + + + HT + Analog watchdog higher + threshold + 0 + 12 + + + + + LTR + LTR + watchdog lower threshold + register + 0x28 + 0x20 + read-write + 0x00000000 + + + LT + Analog watchdog lower + threshold + 0 + 12 + + + + + SQR1 + SQR1 + regular sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + L + Regular channel sequence + length + 20 + 4 + + + SQ16 + 16th conversion in regular + sequence + 15 + 5 + + + SQ15 + 15th conversion in regular + sequence + 10 + 5 + + + SQ14 + 14th conversion in regular + sequence + 5 + 5 + + + SQ13 + 13th conversion in regular + sequence + 0 + 5 + + + + + SQR2 + SQR2 + regular sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ12 + 12th conversion in regular + sequence + 25 + 5 + + + SQ11 + 11th conversion in regular + sequence + 20 + 5 + + + SQ10 + 10th conversion in regular + sequence + 15 + 5 + + + SQ9 + 9th conversion in regular + sequence + 10 + 5 + + + SQ8 + 8th conversion in regular + sequence + 5 + 5 + + + SQ7 + 7th conversion in regular + sequence + 0 + 5 + + + + + SQR3 + SQR3 + regular sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ6 + 6th conversion in regular + sequence + 25 + 5 + + + SQ5 + 5th conversion in regular + sequence + 20 + 5 + + + SQ4 + 4th conversion in regular + sequence + 15 + 5 + + + SQ3 + 3rd conversion in regular + sequence + 10 + 5 + + + SQ2 + 2nd conversion in regular + sequence + 5 + 5 + + + SQ1 + 1st conversion in regular + sequence + 0 + 5 + + + + + JSQR + JSQR + injected sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + JL + Injected sequence length + 20 + 2 + + + JSQ4 + 4th conversion in injected + sequence + 15 + 5 + + + JSQ3 + 3rd conversion in injected + sequence + 10 + 5 + + + JSQ2 + 2nd conversion in injected + sequence + 5 + 5 + + + JSQ1 + 1st conversion in injected + sequence + 0 + 5 + + + + + JDR1 + JDR1 + injected data register x + 0x3C + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + JDR2 + JDR2 + injected data register x + 0x40 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + JDR3 + JDR3 + injected data register x + 0x44 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + JDR4 + JDR4 + injected data register x + 0x48 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + DR + DR + regular data register + 0x4C + 0x20 + read-only + 0x00000000 + + + DATA + Regular data + 0 + 16 + + + + + + + ADC2 + 0x40012100 + + ADC + ADC2 global interrupts + 18 + + + + ADC3 + 0x40012200 + + ADC + ADC3 global interrupts + 18 + + + + USART6 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40011400 + + 0x0 + 0x400 + registers + + + USART6 + USART6 global interrupt + 71 + + + + SR + SR + Status register + 0x0 + 0x20 + 0x00C00000 + + + CTS + CTS flag + 9 + 1 + read-write + + + LBD + LIN break detection flag + 8 + 1 + read-write + + + TXE + Transmit data register + empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RXNE + Read data register not + empty + 5 + 1 + read-write + + + IDLE + IDLE line detected + 4 + 1 + read-only + + + ORE + Overrun error + 3 + 1 + read-only + + + NF + Noise detected flag + 2 + 1 + read-only + + + FE + Framing error + 1 + 1 + read-only + + + PE + Parity error + 0 + 1 + read-only + + + + + DR + DR + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DR + Data value + 0 + 9 + + + + + BRR + BRR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV_Mantissa + mantissa of USARTDIV + 4 + 12 + + + DIV_Fraction + fraction of USARTDIV + 0 + 4 + + + + + CR1 + CR1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + OVER8 + Oversampling mode + 15 + 1 + + + UE + USART enable + 13 + 1 + + + M + Word length + 12 + 1 + + + WAKE + Wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + TXE interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + RWU + Receiver wakeup + 1 + 1 + + + SBK + Send break + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBDL + lin break detection length + 5 + 1 + + + ADD + Address of the USART node + 0 + 4 + + + + + CR3 + CR3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + ONEBIT + One sample bit method + enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + IrDA low-power + 2 + 1 + + + IREN + IrDA mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + GTPR + GTPR + Guard time and prescaler + register + 0x18 + 0x20 + read-write + 0x0000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + + + USART1 + 0x40011000 + + USART1 + USART1 global interrupt + 37 + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + DAC + Digital-to-analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + TIM6_DAC + TIM6 global interrupt, DAC1 and DAC2 underrun + error interrupt + 54 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAUDRIE2 + DAC channel2 DMA underrun interrupt + enable + 29 + 1 + + + DMAEN2 + DAC channel2 DMA enable + 28 + 1 + + + MAMP2 + DAC channel2 mask/amplitude + selector + 24 + 4 + + + WAVE2 + DAC channel2 noise/triangle wave + generation enable + 22 + 2 + + + TSEL2 + DAC channel2 trigger + selection + 19 + 3 + + + TEN2 + DAC channel2 trigger + enable + 18 + 1 + + + BOFF2 + DAC channel2 output buffer + disable + 17 + 1 + + + EN2 + DAC channel2 enable + 16 + 1 + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt + enable + 13 + 1 + + + DMAEN1 + DAC channel1 DMA enable + 12 + 1 + + + MAMP1 + DAC channel1 mask/amplitude + selector + 8 + 4 + + + WAVE1 + DAC channel1 noise/triangle wave + generation enable + 6 + 2 + + + TSEL1 + DAC channel1 trigger + selection + 3 + 3 + + + TEN1 + DAC channel1 trigger + enable + 2 + 1 + + + BOFF1 + DAC channel1 output buffer + disable + 1 + 1 + + + EN1 + DAC channel1 enable + 0 + 1 + + + + + SWTRIGR + SWTRIGR + software trigger register + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG2 + DAC channel2 software + trigger + 1 + 1 + + + SWTRIG1 + DAC channel1 software + trigger + 0 + 1 + + + + + DHR12R1 + DHR12R1 + channel1 12-bit right-aligned data holding + register + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + + + DHR12L1 + DHR12L1 + channel1 12-bit left aligned data holding + register + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + + + DHR8R1 + DHR8R1 + channel1 8-bit right aligned data holding + register + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + + + DHR12R2 + DHR12R2 + channel2 12-bit right aligned data holding + register + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 0 + 12 + + + + + DHR12L2 + DHR12L2 + channel2 12-bit left aligned data holding + register + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 4 + 12 + + + + + DHR8R2 + DHR8R2 + channel2 8-bit right-aligned data holding + register + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 0 + 8 + + + + + DHR12RD + DHR12RD + Dual DAC 12-bit right-aligned data holding + register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 16 + 12 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + + + DHR12LD + DHR12LD + DUAL DAC 12-bit left aligned data holding + register + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 20 + 12 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + + + DHR8RD + DHR8RD + DUAL DAC 8-bit right aligned data holding + register + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 8 + 8 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + + + DOR1 + DOR1 + channel1 data output register + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output + 0 + 12 + + + + + DOR2 + DOR2 + channel2 data output register + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output + 0 + 12 + + + + + SR + SR + status register + 0x34 + 0x20 + read-write + 0x00000000 + + + DMAUDR2 + DAC channel2 DMA underrun + flag + 29 + 1 + + + DMAUDR1 + DAC channel1 DMA underrun + flag + 13 + 1 + + + + + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + PVD + PVD through EXTI line detection + interrupt + 1 + + + + CR + CR + power control register + 0x0 + 0x20 + read-write + 0x00000000 + + + FPDS + Flash power down in Stop + mode + 9 + 1 + + + DBP + Disable backup domain write + protection + 8 + 1 + + + PLS + PVD level selection + 5 + 3 + + + PVDE + Power voltage detector + enable + 4 + 1 + + + CSBF + Clear standby flag + 3 + 1 + + + CWUF + Clear wakeup flag + 2 + 1 + + + PDDS + Power down deepsleep + 1 + 1 + + + LPDS + Low-power deep sleep + 0 + 1 + + + + + CSR + CSR + power control/status register + 0x4 + 0x20 + 0x00000000 + + + WUF + Wakeup flag + 0 + 1 + read-only + + + SBF + Standby flag + 1 + 1 + read-only + + + PVDO + PVD output + 2 + 1 + read-only + + + BRR + Backup regulator ready + 3 + 1 + read-only + + + EWUP + Enable WKUP pin + 8 + 1 + read-write + + + BRE + Backup regulator enable + 9 + 1 + read-write + + + VOSRDY + Regulator voltage scaling output + selection ready bit + 14 + 1 + read-write + + + + + + + I2C3 + Inter-integrated circuit + I2C + 0x40005C00 + + 0x0 + 0x400 + registers + + + I2C3_EV + I2C3 event interrupt + 72 + + + I2C3_ER + I2C3 error interrupt + 73 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SWRST + Software reset + 15 + 1 + + + ALERT + SMBus alert + 13 + 1 + + + PEC + Packet error checking + 12 + 1 + + + POS + Acknowledge/PEC Position (for data + reception) + 11 + 1 + + + ACK + Acknowledge enable + 10 + 1 + + + STOP + Stop generation + 9 + 1 + + + START + Start generation + 8 + 1 + + + NOSTRETCH + Clock stretching disable (Slave + mode) + 7 + 1 + + + ENGC + General call enable + 6 + 1 + + + ENPEC + PEC enable + 5 + 1 + + + ENARP + ARP enable + 4 + 1 + + + SMBTYPE + SMBus type + 3 + 1 + + + SMBUS + SMBus mode + 1 + 1 + + + PE + Peripheral enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + LAST + DMA last transfer + 12 + 1 + + + DMAEN + DMA requests enable + 11 + 1 + + + ITBUFEN + Buffer interrupt enable + 10 + 1 + + + ITEVTEN + Event interrupt enable + 9 + 1 + + + ITERREN + Error interrupt enable + 8 + 1 + + + FREQ + Peripheral clock frequency + 0 + 6 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + ADDMODE + Addressing mode (slave + mode) + 15 + 1 + + + ADD10 + Interface address + 8 + 2 + + + ADD7 + Interface address + 1 + 7 + + + ADD0 + Interface address + 0 + 1 + + + + + OAR2 + OAR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x0000 + + + ADD2 + Interface address + 1 + 7 + + + ENDUAL + Dual addressing mode + enable + 0 + 1 + + + + + DR + DR + Data register + 0x10 + 0x20 + read-write + 0x0000 + + + DR + 8-bit data register + 0 + 8 + + + + + SR1 + SR1 + Status register 1 + 0x14 + 0x20 + 0x0000 + + + SMBALERT + SMBus alert + 15 + 1 + read-write + + + TIMEOUT + Timeout or Tlow error + 14 + 1 + read-write + + + PECERR + PEC Error in reception + 12 + 1 + read-write + + + OVR + Overrun/Underrun + 11 + 1 + read-write + + + AF + Acknowledge failure + 10 + 1 + read-write + + + ARLO + Arbitration lost (master + mode) + 9 + 1 + read-write + + + BERR + Bus error + 8 + 1 + read-write + + + TxE + Data register empty + (transmitters) + 7 + 1 + read-only + + + RxNE + Data register not empty + (receivers) + 6 + 1 + read-only + + + STOPF + Stop detection (slave + mode) + 4 + 1 + read-only + + + ADD10 + 10-bit header sent (Master + mode) + 3 + 1 + read-only + + + BTF + Byte transfer finished + 2 + 1 + read-only + + + ADDR + Address sent (master mode)/matched + (slave mode) + 1 + 1 + read-only + + + SB + Start bit (Master mode) + 0 + 1 + read-only + + + + + SR2 + SR2 + Status register 2 + 0x18 + 0x20 + read-only + 0x0000 + + + PEC + acket error checking + register + 8 + 8 + + + DUALF + Dual flag (Slave mode) + 7 + 1 + + + SMBHOST + SMBus host header (Slave + mode) + 6 + 1 + + + SMBDEFAULT + SMBus device default address (Slave + mode) + 5 + 1 + + + GENCALL + General call address (Slave + mode) + 4 + 1 + + + TRA + Transmitter/receiver + 2 + 1 + + + BUSY + Bus busy + 1 + 1 + + + MSL + Master/slave + 0 + 1 + + + + + CCR + CCR + Clock control register + 0x1C + 0x20 + read-write + 0x0000 + + + F_S + I2C master mode selection + 15 + 1 + + + DUTY + Fast mode duty cycle + 14 + 1 + + + CCR + Clock control register in Fast/Standard + mode (Master mode) + 0 + 12 + + + + + TRISE + TRISE + TRISE register + 0x20 + 0x20 + read-write + 0x0002 + + + TRISE + Maximum rise time in Fast/Standard mode + (Master mode) + 0 + 6 + + + + + + + I2C2 + 0x40005800 + + I2C2_EV + I2C2 event interrupt + 33 + + + I2C2_ER + I2C2 error interrupt + 34 + + + + I2C1 + 0x40005400 + + I2C1_EV + I2C1 event interrupt + 31 + + + I2C1_ER + I2C1 error interrupt + 32 + + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value (write only, read + 0000h) + 0 + 16 + + + + + PR + PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + + + + RLR + RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload + value + 0 + 12 + + + + + SR + SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + RVU + Watchdog counter reload value + update + 1 + 1 + + + PVU + Watchdog prescaler value + update + 0 + 1 + + + + + + + WWDG + Window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG + Window Watchdog interrupt + 0 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x7F + + + WDGA + Activation bit + 7 + 1 + + + T + 7-bit counter (MSB to LSB) + 0 + 7 + + + + + CFR + CFR + Configuration register + 0x4 + 0x20 + read-write + 0x7F + + + EWI + Early wakeup interrupt + 9 + 1 + + + WDGTB1 + Timer base + 8 + 1 + + + WDGTB0 + Timer base + 7 + 1 + + + W + 7-bit window value + 0 + 7 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-write + 0x00 + + + EWIF + Early wakeup interrupt + flag + 0 + 1 + + + + + + + RTC + Real-time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC_WKUP + RTC Wakeup interrupt through the EXTI + line + 3 + + + RTC_Alarm + RTC Alarms (A and B) through EXTI line + interrupt + 41 + + + + TR + TR + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + DR + DR + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens in BCD format + 20 + 4 + + + YU + Year units in BCD format + 16 + 4 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + CR + CR + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + COE + Calibration output enable + 23 + 1 + + + OSEL + Output selection + 21 + 2 + + + POL + Output polarity + 20 + 1 + + + BKP + Backup + 18 + 1 + + + SUB1H + Subtract 1 hour (winter time + change) + 17 + 1 + + + ADD1H + Add 1 hour (summer time + change) + 16 + 1 + + + TSIE + Time-stamp interrupt + enable + 15 + 1 + + + WUTIE + Wakeup timer interrupt + enable + 14 + 1 + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + + + TSE + Time stamp enable + 11 + 1 + + + WUTE + Wakeup timer enable + 10 + 1 + + + ALRBE + Alarm B enable + 9 + 1 + + + ALRAE + Alarm A enable + 8 + 1 + + + DCE + Coarse digital calibration + enable + 7 + 1 + + + FMT + Hour format + 6 + 1 + + + REFCKON + Reference clock detection enable (50 or + 60 Hz) + 4 + 1 + + + TSEDGE + Time-stamp event active + edge + 3 + 1 + + + WCKSEL + Wakeup clock selection + 0 + 3 + + + + + ISR + ISR + initialization and status + register + 0xC + 0x20 + 0x00000007 + + + ALRAWF + Alarm A write flag + 0 + 1 + read-only + + + ALRBWF + Alarm B write flag + 1 + 1 + read-only + + + WUTWF + Wakeup timer write flag + 2 + 1 + read-only + + + SHPF + Shift operation pending + 3 + 1 + read-write + + + INITS + Initialization status flag + 4 + 1 + read-only + + + RSF + Registers synchronization + flag + 5 + 1 + read-write + + + INITF + Initialization flag + 6 + 1 + read-only + + + INIT + Initialization mode + 7 + 1 + read-write + + + ALRAF + Alarm A flag + 8 + 1 + read-write + + + ALRBF + Alarm B flag + 9 + 1 + read-write + + + WUTF + Wakeup timer flag + 10 + 1 + read-write + + + TSF + Time-stamp flag + 11 + 1 + read-write + + + TSOVF + Time-stamp overflow flag + 12 + 1 + read-write + + + TAMP1F + Tamper detection flag + 13 + 1 + read-write + + + TAMP2F + TAMPER2 detection flag + 14 + 1 + read-write + + + RECALPF + Recalibration pending Flag + 16 + 1 + read-only + + + + + PRER + PRER + prescaler register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_A + Asynchronous prescaler + factor + 16 + 7 + + + PREDIV_S + Synchronous prescaler + factor + 0 + 15 + + + + + WUTR + WUTR + wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value + bits + 0 + 16 + + + + + CALIBR + CALIBR + calibration register + 0x18 + 0x20 + read-write + 0x00000000 + + + DCS + Digital calibration sign + 7 + 1 + + + DC + Digital calibration + 0 + 5 + + + + + ALRMAR + ALRMAR + alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm A date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD + format + 24 + 4 + + + MSK3 + Alarm A hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm A minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm A seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + ALRMBR + ALRMBR + alarm B register + 0x20 + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm B date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD + format + 24 + 4 + + + MSK3 + Alarm B hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm B minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm B seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + WPR + WPR + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + Write protection key + 0 + 8 + + + + + SSR + SSR + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + SHIFTR + SHIFTR + shift control register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add one second + 31 + 1 + + + SUBFS + Subtract a fraction of a + second + 0 + 15 + + + + + TSTR + TSTR + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + ALARMOUTTYPE + AFO_ALARM output type + 18 + 1 + + + TSINSEL + TIMESTAMP mapping + 17 + 1 + + + TAMP1INSEL + TAMPER1 mapping + 16 + 1 + + + TAMPIE + Tamper interrupt enable + 2 + 1 + + + TAMP1TRG + Active level for tamper 1 + 1 + 1 + + + TAMP1E + Tamper 1 detection enable + 0 + 1 + + + + + TSDR + TSDR + time stamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + TSSSR + TSSSR + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + CALR + CALR + calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + CALP + Increase frequency of RTC by 488.5 + ppm + 15 + 1 + + + CALW8 + Use an 8-second calibration cycle + period + 14 + 1 + + + CALW16 + Use a 16-second calibration cycle + period + 13 + 1 + + + CALM + Calibration minus + 0 + 9 + + + + + TAFCR + TAFCR + tamper and alternate function configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + ALARMOUTTYPE + AFO_ALARM output type + 18 + 1 + + + TSINSEL + TIMESTAMP mapping + 17 + 1 + + + TAMP1INSEL + TAMPER1 mapping + 16 + 1 + + + TAMPPUDIS + TAMPER pull-up disable + 15 + 1 + + + TAMPPRCH + Tamper precharge duration + 13 + 2 + + + TAMPFLT + Tamper filter count + 11 + 2 + + + TAMPFREQ + Tamper sampling frequency + 8 + 3 + + + TAMPTS + Activate timestamp on tamper detection + event + 7 + 1 + + + TAMP2TRG + Active level for tamper 2 + 4 + 1 + + + TAMP2E + Tamper 2 detection enable + 3 + 1 + + + TAMPIE + Tamper interrupt enable + 2 + 1 + + + TAMP1TRG + Active level for tamper 1 + 1 + 1 + + + TAMP1E + Tamper 1 detection enable + 0 + 1 + + + + + ALRMASSR + ALRMASSR + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting + at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + ALRMBSSR + ALRMBSSR + alarm B sub second register + 0x48 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting + at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + BKP0R + BKP0R + backup register + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP1R + BKP1R + backup register + 0x54 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP2R + BKP2R + backup register + 0x58 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP3R + BKP3R + backup register + 0x5C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP4R + BKP4R + backup register + 0x60 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP5R + BKP5R + backup register + 0x64 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP6R + BKP6R + backup register + 0x68 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP7R + BKP7R + backup register + 0x6C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP8R + BKP8R + backup register + 0x70 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP9R + BKP9R + backup register + 0x74 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP10R + BKP10R + backup register + 0x78 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP11R + BKP11R + backup register + 0x7C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP12R + BKP12R + backup register + 0x80 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP13R + BKP13R + backup register + 0x84 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP14R + BKP14R + backup register + 0x88 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP15R + BKP15R + backup register + 0x8C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP16R + BKP16R + backup register + 0x90 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP17R + BKP17R + backup register + 0x94 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP18R + BKP18R + backup register + 0x98 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP19R + BKP19R + backup register + 0x9C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + + + UART4 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40004C00 + + 0x0 + 0x400 + registers + + + UART4 + UART4 global interrupt + 52 + + + + SR + SR + Status register + 0x0 + 0x20 + 0x00C00000 + + + LBD + LIN break detection flag + 8 + 1 + read-write + + + TXE + Transmit data register + empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RXNE + Read data register not + empty + 5 + 1 + read-write + + + IDLE + IDLE line detected + 4 + 1 + read-only + + + ORE + Overrun error + 3 + 1 + read-only + + + NF + Noise detected flag + 2 + 1 + read-only + + + FE + Framing error + 1 + 1 + read-only + + + PE + Parity error + 0 + 1 + read-only + + + + + DR + DR + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DR + Data value + 0 + 9 + + + + + BRR + BRR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV_Mantissa + mantissa of USARTDIV + 4 + 12 + + + DIV_Fraction + fraction of USARTDIV + 0 + 4 + + + + + CR1 + CR1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + OVER8 + Oversampling mode + 15 + 1 + + + UE + USART enable + 13 + 1 + + + M + Word length + 12 + 1 + + + WAKE + Wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + TXE interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + RWU + Receiver wakeup + 1 + 1 + + + SBK + Send break + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBDL + lin break detection length + 5 + 1 + + + ADD + Address of the USART node + 0 + 4 + + + + + CR3 + CR3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + ONEBIT + One sample bit method + enable + 11 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + IrDA low-power + 2 + 1 + + + IREN + IrDA mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + + + UART5 + 0x40005000 + + UART5 + UART5 global interrupt + 53 + + + + C_ADC + Common ADC registers + ADC + 0x40012300 + + 0x0 + 0x400 + registers + + + + CSR + CSR + ADC Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + OVR3 + Overrun flag of ADC3 + 21 + 1 + + + STRT3 + Regular channel Start flag of ADC + 3 + 20 + 1 + + + JSTRT3 + Injected channel Start flag of ADC + 3 + 19 + 1 + + + JEOC3 + Injected channel end of conversion of + ADC 3 + 18 + 1 + + + EOC3 + End of conversion of ADC 3 + 17 + 1 + + + AWD3 + Analog watchdog flag of ADC + 3 + 16 + 1 + + + OVR2 + Overrun flag of ADC 2 + 13 + 1 + + + STRT2 + Regular channel Start flag of ADC + 2 + 12 + 1 + + + JSTRT2 + Injected channel Start flag of ADC + 2 + 11 + 1 + + + JEOC2 + Injected channel end of conversion of + ADC 2 + 10 + 1 + + + EOC2 + End of conversion of ADC 2 + 9 + 1 + + + AWD2 + Analog watchdog flag of ADC + 2 + 8 + 1 + + + OVR1 + Overrun flag of ADC 1 + 5 + 1 + + + STRT1 + Regular channel Start flag of ADC + 1 + 4 + 1 + + + JSTRT1 + Injected channel Start flag of ADC + 1 + 3 + 1 + + + JEOC1 + Injected channel end of conversion of + ADC 1 + 2 + 1 + + + EOC1 + End of conversion of ADC 1 + 1 + 1 + + + AWD1 + Analog watchdog flag of ADC + 1 + 0 + 1 + + + + + CCR + CCR + ADC common control register + 0x4 + 0x20 + read-write + 0x00000000 + + + TSVREFE + Temperature sensor and VREFINT + enable + 23 + 1 + + + VBATE + VBAT enable + 22 + 1 + + + ADCPRE + ADC prescaler + 16 + 2 + + + DMA + Direct memory access mode for multi ADC + mode + 14 + 2 + + + DDS + DMA disable selection for multi-ADC + mode + 13 + 1 + + + DELAY + Delay between 2 sampling + phases + 8 + 4 + + + MULT + Multi ADC mode selection + 0 + 5 + + + + + CDR + CDR + ADC common regular data register for dual + and triple modes + 0x8 + 0x20 + read-only + 0x00000000 + + + DATA2 + 2nd data item of a pair of regular + conversions + 16 + 16 + + + DATA1 + 1st data item of a pair of regular + conversions + 0 + 16 + + + + + + + TIM1 + Advanced-timers + TIM + 0x40010000 + + 0x0 + 0x400 + registers + + + TIM1_BRK_TIM9 + TIM1 Break interrupt and TIM9 global + interrupt + 24 + + + TIM1_UP_TIM10 + TIM1 Update interrupt and TIM10 global + interrupt + 25 + + + TIM1_TRG_COM_TIM11 + TIM1 Trigger and Commutation interrupts and + TIM11 global interrupt + 26 + + + TIM1_CC + TIM1 Capture Compare interrupt + 27 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + Output Compare 2 clear + enable + 15 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1CE + Output Compare 1 clear + enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PCS + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + Output compare 4 clear + enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + CC4S + 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description available + 3 + 1 + + + MCP + no description available + 4 + 1 + + + MCFHP + no description available + 5 + 1 + + + + + MMCRIR + MMCRIR + Ethernet MMC receive interrupt + register + 0x4 + 0x20 + read-write + 0x00000000 + + + RFCES + no description available + 5 + 1 + + + RFAES + no description available + 6 + 1 + + + RGUFS + no description available + 17 + 1 + + + + + MMCTIR + MMCTIR + Ethernet MMC transmit interrupt + register + 0x8 + 0x20 + read-only + 0x00000000 + + + TGFSCS + no description available + 14 + 1 + + + TGFMSCS + no description available + 15 + 1 + + + TGFS + no description available + 21 + 1 + + + + + MMCRIMR + MMCRIMR + Ethernet MMC receive interrupt mask + register + 0xC + 0x20 + read-write + 0x00000000 + + + RFCEM + no description available + 5 + 1 + + + RFAEM + no description available + 6 + 1 + + + RGUFM + no description available + 17 + 1 + + + + + MMCTIMR + MMCTIMR + Ethernet MMC transmit interrupt mask + register + 0x10 + 0x20 + read-write + 0x00000000 + + + TGFSCM + no description available + 14 + 1 + + + TGFMSCM + no description available + 15 + 1 + + + TGFM + no description available + 16 + 1 + + + + + MMCTGFSCCR + MMCTGFSCCR + Ethernet MMC transmitted good frames after a + single collision counter + 0x4C + 0x20 + read-only + 0x00000000 + + + TGFSCC + no description available + 0 + 32 + + + + + MMCTGFMSCCR + MMCTGFMSCCR + Ethernet MMC transmitted good frames after + more than a single collision + 0x50 + 0x20 + read-only + 0x00000000 + + + TGFMSCC + no description available + 0 + 32 + + + + + MMCTGFCR + MMCTGFCR + Ethernet MMC transmitted good frames counter + register + 0x68 + 0x20 + read-only + 0x00000000 + + + TGFC + HTL + 0 + 32 + + + + + MMCRFCECR + MMCRFCECR + Ethernet MMC received frames with CRC error + counter register + 0x94 + 0x20 + read-only + 0x00000000 + + + RFCFC + no description available + 0 + 32 + + + + + MMCRFAECR + MMCRFAECR + Ethernet MMC received frames with alignment + error counter register + 0x98 + 0x20 + read-only + 0x00000000 + + + RFAEC + no description available + 0 + 32 + + + + + MMCRGUFCR + MMCRGUFCR + MMC received good unicast frames counter + register + 0xC4 + 0x20 + read-only + 0x00000000 + + + RGUFC + no description available + 0 + 32 + + + + + + + Ethernet_PTP + Ethernet: Precision time protocol + Ethernet + 0x40028700 + + 0x0 + 0x400 + registers + + + + PTPTSCR + PTPTSCR + Ethernet PTP time stamp control + register + 0x0 + 0x20 + read-write + 0x00002000 + + + TSE + no description available + 0 + 1 + + + TSFCU + no description available + 1 + 1 + + + TSPTPPSV2E + no description available + 10 + 1 + + + TSSPTPOEFE + no description available + 11 + 1 + + + TSSIPV6FE + no description available + 12 + 1 + + + TSSIPV4FE + no description available + 13 + 1 + + + TSSEME + no description available + 14 + 1 + + + TSSMRME + no description available + 15 + 1 + + + TSCNT + no description available + 16 + 2 + + + TSPFFMAE + no description available + 18 + 1 + + + TSSTI + no description available + 2 + 1 + + + TSSTU + no description available + 3 + 1 + + + TSITE + no description available + 4 + 1 + + + TTSARU + no description available + 5 + 1 + + + TSSARFE + no description available + 8 + 1 + + + TSSSR + no description available + 9 + 1 + + + + + PTPSSIR + PTPSSIR + Ethernet PTP subsecond increment + register + 0x4 + 0x20 + read-write + 0x00000000 + + + STSSI + no description available + 0 + 8 + + + + + PTPTSHR + PTPTSHR + Ethernet PTP time stamp high + register + 0x8 + 0x20 + read-only + 0x00000000 + + + STS + no description available + 0 + 32 + + + + + PTPTSLR + PTPTSLR + Ethernet PTP time stamp low + register + 0xC + 0x20 + read-only + 0x00000000 + + + STSS + no description available + 0 + 31 + + + STPNS + no description available + 31 + 1 + + + + + PTPTSHUR + PTPTSHUR + Ethernet PTP time stamp high update + register + 0x10 + 0x20 + read-write + 0x00000000 + + + TSUS + no description available + 0 + 32 + + + + + PTPTSLUR + PTPTSLUR + Ethernet PTP time stamp low update + register + 0x14 + 0x20 + read-write + 0x00000000 + + + TSUSS + no description available + 0 + 31 + + + TSUPNS + no description available + 31 + 1 + + + + + PTPTSAR + PTPTSAR + Ethernet PTP time stamp addend + register + 0x18 + 0x20 + read-write + 0x00000000 + + + TSA + no description available + 0 + 32 + + + + + PTPTTHR + PTPTTHR + Ethernet PTP target time high + register + 0x1C + 0x20 + read-write + 0x00000000 + + + TTSH + 0 + 0 + 32 + + + + + PTPTTLR + PTPTTLR + Ethernet PTP target time low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + TTSL + no description available + 0 + 32 + + + + + PTPTSSR + PTPTSSR + Ethernet PTP time stamp status + register + 0x28 + 0x20 + read-only + 0x00000000 + + + TSSO + no description available + 0 + 1 + + + TSTTR + no description available + 1 + 1 + + + + + PTPPPSCR + PTPPPSCR + Ethernet PTP PPS control + register + 0x2C + 0x20 + read-only + 0x00000000 + + + TSSO + TSSO + 0 + 1 + + + TSTTR + TSTTR + 1 + 1 + + + + + + + Ethernet_DMA + Ethernet: DMA controller operation + Ethernet + 0x40029000 + + 0x0 + 0x400 + registers + + + + DMABMR + DMABMR + Ethernet DMA bus mode register + 0x0 + 0x20 + read-write + 0x00002101 + + + SR + no description available + 0 + 1 + + + DA + no description available + 1 + 1 + + + DSL + no description available + 2 + 5 + + + EDFE + no description available + 7 + 1 + + + PBL + no description available + 8 + 6 + + + RTPR + no description available + 14 + 2 + + + FB + no description available + 16 + 1 + + + RDP + no description available + 17 + 6 + + + USP + no description available + 23 + 1 + + + FPM + no description available + 24 + 1 + + + AAB + no description available + 25 + 1 + + + MB + no description available + 26 + 1 + + + + + DMATPDR + DMATPDR + Ethernet DMA transmit poll demand + register + 0x4 + 0x20 + read-write + 0x00000000 + + + TPD + no description available + 0 + 32 + + + + + DMARPDR + DMARPDR + EHERNET DMA receive poll demand + register + 0x8 + 0x20 + read-write + 0x00000000 + + + RPD + RPD + 0 + 32 + + + + + DMARDLAR + DMARDLAR + Ethernet DMA receive descriptor list address + register + 0xC + 0x20 + read-write + 0x00000000 + + + SRL + no description available + 0 + 32 + + + + + DMATDLAR + DMATDLAR + Ethernet DMA transmit descriptor list + address register + 0x10 + 0x20 + read-write + 0x00000000 + + + STL + no description available + 0 + 32 + + + + + DMASR + DMASR + Ethernet DMA status register + 0x14 + 0x20 + 0x00000000 + + + TS + no description available + 0 + 1 + read-write + + + TPSS + no description available + 1 + 1 + read-write + + + TBUS + no description available + 2 + 1 + read-write + + + TJTS + no description available + 3 + 1 + read-write + + + ROS + no description available + 4 + 1 + read-write + + + TUS + no description available + 5 + 1 + read-write + + + RS + no description available + 6 + 1 + read-write + + + RBUS + no description available + 7 + 1 + read-write + + + RPSS + no description available + 8 + 1 + read-write + + + PWTS + no description available + 9 + 1 + read-write + + + ETS + no description available + 10 + 1 + read-write + + + FBES + no description available + 13 + 1 + read-write + + + ERS + no description available + 14 + 1 + read-write + + + AIS + no description available + 15 + 1 + read-write + + + NIS + no description available + 16 + 1 + read-write + + + RPS + no description available + 17 + 3 + read-only + + + TPS + no description available + 20 + 3 + read-only + + + EBS + no description available + 23 + 3 + read-only + + + MMCS + no description available + 27 + 1 + read-only + + + PMTS + no description available + 28 + 1 + read-only + + + TSTS + no description available + 29 + 1 + read-only + + + + + DMAOMR + DMAOMR + Ethernet DMA operation mode + register + 0x18 + 0x20 + read-write + 0x00000000 + + + SR + SR + 1 + 1 + + + OSF + OSF + 2 + 1 + + + RTC + RTC + 3 + 2 + + + FUGF + FUGF + 6 + 1 + + + FEF + FEF + 7 + 1 + + + ST + ST + 13 + 1 + + + TTC + TTC + 14 + 3 + + + FTF + FTF + 20 + 1 + + + TSF + TSF + 21 + 1 + + + DFRF + DFRF + 24 + 1 + + + RSF + RSF + 25 + 1 + + + DTCEFD + DTCEFD + 26 + 1 + + + + + DMAIER + DMAIER + Ethernet DMA interrupt enable + register + 0x1C + 0x20 + read-write + 0x00000000 + + + TIE + no description available + 0 + 1 + + + TPSIE + no description available + 1 + 1 + + + TBUIE + no description available + 2 + 1 + + + TJTIE + no description available + 3 + 1 + + + ROIE + no description available + 4 + 1 + + + TUIE + no description available + 5 + 1 + + + RIE + no description available + 6 + 1 + + + RBUIE + no description available + 7 + 1 + + + RPSIE + no description available + 8 + 1 + + + RWTIE + no description available + 9 + 1 + + + ETIE + no description available + 10 + 1 + + + FBEIE + no description available + 13 + 1 + + + ERIE + no description available + 14 + 1 + + + AISE + no description available + 15 + 1 + + + NISE + no description available + 16 + 1 + + + + + DMAMFBOCR + DMAMFBOCR + Ethernet DMA missed frame and buffer + overflow counter register + 0x20 + 0x20 + read-write + 0x00000000 + + + MFC + no description available + 0 + 16 + + + OMFC + no description available + 16 + 1 + + + MFA + no description available + 17 + 11 + + + OFOC + no description available + 28 + 1 + + + + + DMARSWTR + DMARSWTR + Ethernet DMA receive status watchdog timer + register + 0x24 + 0x20 + read-write + 0x00000000 + + + RSWTC + RSWTC + 0 + 8 + + + + + DMACHTDR + DMACHTDR + Ethernet DMA current host transmit + descriptor register + 0x48 + 0x20 + read-only + 0x00000000 + + + HTDAP + HTDAP + 0 + 32 + + + + + DMACHRDR + DMACHRDR + Ethernet DMA current host receive descriptor + register + 0x4C + 0x20 + read-only + 0x00000000 + + + HRDAP + HRDAP + 0 + 32 + + + + + DMACHTBAR + DMACHTBAR + Ethernet DMA current host transmit buffer + address register + 0x50 + 0x20 + read-only + 0x00000000 + + + HTBAP + no description available + 0 + 32 + + + + + DMACHRBAR + DMACHRBAR + Ethernet DMA current host receive buffer + address register + 0x54 + 0x20 + read-only + 0x00000000 + + + HRBAP + no description available + 0 + 32 + + + + + + + CRC + Cryptographic processor + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data Register + 0 + 32 + + + + + IDR + IDR + Independent Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + Independent Data register + 0 + 8 + + + + + CR + CR + Control register + 0x8 + 0x20 + write-only + 0x00000000 + + + CR + Control regidter + 0 + 1 + + + + + + + OTG_FS_GLOBAL + USB on the go full speed + USB_OTG_FS + 0x50000000 + + 0x0 + 0x400 + registers + + + OTG_FS_WKUP + USB On-The-Go FS Wakeup through EXTI line + interrupt + 42 + + + OTG_FS + USB On The Go FS global + interrupt + 67 + + + + FS_GOTGCTL + FS_GOTGCTL + OTG_FS control and status register + (OTG_FS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + SRQSCS + Session request success + 0 + 1 + read-only + + + SRQ + Session request + 1 + 1 + read-write + + + HNGSCS + Host negotiation success + 8 + 1 + read-only + + + HNPRQ + HNP request + 9 + 1 + read-write + + + HSHNPEN + Host set HNP enable + 10 + 1 + read-write + + + DHNPEN + Device HNP enabled + 11 + 1 + read-write + + + CIDSTS + Connector ID status + 16 + 1 + read-only + + + DBCT + Long/short debounce time + 17 + 1 + read-only + + + ASVLD + A-session valid + 18 + 1 + read-only + + + BSVLD + B-session valid + 19 + 1 + read-only + + + + + FS_GOTGINT + FS_GOTGINT + OTG_FS interrupt register + (OTG_FS_GOTGINT) + 0x4 + 0x20 + read-write + 0x00000000 + + + SEDET + Session end detected + 2 + 1 + + + SRSSCHG + Session request success status + change + 8 + 1 + + + HNSSCHG + Host negotiation success status + change + 9 + 1 + + + HNGDET + Host negotiation detected + 17 + 1 + + + ADTOCHG + A-device timeout change + 18 + 1 + + + DBCDNE + Debounce done + 19 + 1 + + + + + FS_GAHBCFG + FS_GAHBCFG + OTG_FS AHB configuration register + (OTG_FS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GINT + Global interrupt mask + 0 + 1 + + + TXFELVL + TxFIFO empty level + 7 + 1 + + + PTXFELVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + FS_GUSBCFG + FS_GUSBCFG + OTG_FS USB configuration register + (OTG_FS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOCAL + FS timeout calibration + 0 + 3 + read-write + + + PHYSEL + Full Speed serial transceiver + select + 6 + 1 + write-only + + + SRPCAP + SRP-capable + 8 + 1 + read-write + + + HNPCAP + HNP-capable + 9 + 1 + read-write + + + TRDT + USB turnaround time + 10 + 4 + read-write + + + FHMOD + Force host mode + 29 + 1 + read-write + + + FDMOD + Force device mode + 30 + 1 + read-write + + + CTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + FS_GRSTCTL + FS_GRSTCTL + OTG_FS reset register + (OTG_FS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSRST + Core soft reset + 0 + 1 + read-write + + + HSRST + HCLK soft reset + 1 + 1 + read-write + + + FCRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDL + AHB master idle + 31 + 1 + read-only + + + + + FS_GINTSTS + FS_GINTSTS + OTG_FS core interrupt register + (OTG_FS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CMOD + Current mode of operation + 0 + 1 + read-only + + + MMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFE + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ESUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDNE + Enumeration done + 13 + 1 + read-write + + + ISOODRP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPINT + OUT endpoint interrupt + 19 + 1 + read-only + + + IISOIXFR + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + IPXFR_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + HPRTINT + Host port interrupt + 24 + 1 + read-only + + + HCINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFE + Periodic TxFIFO empty + 26 + 1 + read-only + + + CIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + SRQINT + Session request/new session detected + interrupt + 30 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + FS_GINTMSK + FS_GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MMISM + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINT + OTG interrupt mask + 2 + 1 + read-write + + + SOFM + Start of frame mask + 3 + 1 + read-write + + + RXFLVLM + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEM + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINAKEFFM + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GONAKEFFM + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ESUSPM + Early suspend mask + 10 + 1 + read-write + + + USBSUSPM + USB suspend mask + 11 + 1 + read-write + + + USBRST + USB reset mask + 12 + 1 + read-write + + + ENUMDNEM + Enumeration done mask + 13 + 1 + read-write + + + ISOODRPM + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFM + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + EPMISM + Endpoint mismatch interrupt + mask + 17 + 1 + read-write + + + IEPINT + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPINT + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + IISOIXFRM + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + IPXFRM_IISOOXFRM + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTIM + Host port interrupt mask + 24 + 1 + read-only + + + HCIM + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEM + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CIDSCHGM + Connector ID status change + mask + 28 + 1 + read-write + + + DISCINT + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + SRQIM + Session request/new session detected + interrupt mask + 30 + 1 + read-write + + + WUIM + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + FS_GRXSTSR_Device + FS_GRXSTSR_Device + OTG_FS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + FS_GRXSTSR_Host + FS_GRXSTSR_Host + OTG_FS Receive status debug read(Host + mode) + FS_GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + FS_GRXFSIZ + FS_GRXFSIZ + OTG_FS Receive FIFO size register + (OTG_FS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFD + RxFIFO depth + 0 + 16 + + + + + FS_GNPTXFSIZ_Device + FS_GNPTXFSIZ_Device + OTG_FS non-periodic transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + TX0FSA + Endpoint 0 transmit RAM start + address + 0 + 16 + + + TX0FD + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + FS_GNPTXFSIZ_Host + FS_GNPTXFSIZ_Host + OTG_FS non-periodic transmit FIFO size + register (Host mode) + FS_GNPTXFSIZ_Device + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSA + Non-periodic transmit RAM start + address + 0 + 16 + + + NPTXFD + Non-periodic TxFIFO depth + 16 + 16 + + + + + FS_GNPTXSTS + FS_GNPTXSTS + OTG_FS non-periodic transmit FIFO/queue + status register (OTG_FS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSAV + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTQXSAV + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + FS_GCCFG + FS_GCCFG + OTG_FS general core configuration register + (OTG_FS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDWN + Power down + 16 + 1 + + + VBUSASEN + Enable the VBUS sensing + device + 18 + 1 + + + VBUSBSEN + Enable the VBUS sensing + device + 19 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + + + FS_CID + FS_CID + core ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + PRODUCT_ID + Product ID field + 0 + 32 + + + + + FS_HPTXFSIZ + FS_HPTXFSIZ + OTG_FS Host periodic transmit FIFO size + register (OTG_FS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXSA + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZ + Host periodic TxFIFO depth + 16 + 16 + + + + + FS_DIEPTXF1 + FS_DIEPTXF1 + OTG_FS device IN endpoint transmit FIFO size + register (OTG_FS_DIEPTXF2) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + FS_DIEPTXF2 + FS_DIEPTXF2 + OTG_FS device IN endpoint transmit FIFO size + register (OTG_FS_DIEPTXF3) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + FS_DIEPTXF3 + FS_DIEPTXF3 + OTG_FS device IN endpoint transmit FIFO size + register (OTG_FS_DIEPTXF4) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + OTG_FS_HOST + USB on the go full speed + USB_OTG_FS + 0x50000400 + + 0x0 + 0x400 + registers + + + + FS_HCFG + FS_HCFG + OTG_FS host configuration register + (OTG_FS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCS + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSS + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTG_FS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRIVL + Frame interval + 0 + 16 + + + + + FS_HFNUM + FS_HFNUM + OTG_FS host frame number/frame time + remaining register (OTG_FS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + FS_HPTXSTS + FS_HPTXSTS + OTG_FS_Host periodic transmit FIFO/queue + status register (OTG_FS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSAVL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSAV + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTG_FS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTG_FS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTM + Channel interrupt mask + 0 + 16 + + + + + FS_HPRT + FS_HPRT + OTG_FS host port control and status register + (OTG_FS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PCSTS + Port connect status + 0 + 1 + read-only + + + PCDET + Port connect detected + 1 + 1 + read-write + + + PENA + Port enable + 2 + 1 + read-write + + + PENCHNG + Port enable/disable change + 3 + 1 + read-write + + + POCA + Port overcurrent active + 4 + 1 + read-only + + + POCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRES + Port resume + 6 + 1 + read-write + + + PSUSP + Port suspend + 7 + 1 + read-write + + + PRST + Port reset + 8 + 1 + read-write + + + PLSTS + Port line status + 10 + 2 + read-only + + + PPWR + Port power + 12 + 1 + read-write + + + PTCTL + Port test control + 13 + 4 + read-write + + + PSPD + Port speed + 17 + 2 + read-only + + + + + FS_HCCHAR0 + FS_HCCHAR0 + OTG_FS host channel-0 characteristics + register (OTG_FS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR1 + FS_HCCHAR1 + OTG_FS host channel-1 characteristics + register (OTG_FS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR2 + FS_HCCHAR2 + OTG_FS host channel-2 characteristics + register (OTG_FS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR3 + FS_HCCHAR3 + OTG_FS host channel-3 characteristics + register (OTG_FS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR4 + FS_HCCHAR4 + OTG_FS host channel-4 characteristics + register (OTG_FS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR5 + FS_HCCHAR5 + OTG_FS host channel-5 characteristics + register (OTG_FS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR6 + FS_HCCHAR6 + OTG_FS host channel-6 characteristics + register (OTG_FS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR7 + FS_HCCHAR7 + OTG_FS host channel-7 characteristics + register (OTG_FS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCINT0 + FS_HCINT0 + OTG_FS host channel-0 interrupt register + (OTG_FS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT1 + FS_HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT2 + FS_HCINT2 + OTG_FS host channel-2 interrupt register + (OTG_FS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT3 + FS_HCINT3 + OTG_FS host channel-3 interrupt register + (OTG_FS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT4 + FS_HCINT4 + OTG_FS host channel-4 interrupt register + (OTG_FS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT5 + FS_HCINT5 + OTG_FS host channel-5 interrupt register + (OTG_FS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT6 + FS_HCINT6 + OTG_FS host channel-6 interrupt register + (OTG_FS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT7 + FS_HCINT7 + OTG_FS host channel-7 interrupt register + (OTG_FS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINTMSK0 + FS_HCINTMSK0 + OTG_FS host channel-0 mask register + (OTG_FS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK1 + FS_HCINTMSK1 + OTG_FS host channel-1 mask register + (OTG_FS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK2 + FS_HCINTMSK2 + OTG_FS host channel-2 mask register + (OTG_FS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK3 + FS_HCINTMSK3 + OTG_FS host channel-3 mask register + (OTG_FS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK4 + FS_HCINTMSK4 + OTG_FS host channel-4 mask register + (OTG_FS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK5 + FS_HCINTMSK5 + OTG_FS host channel-5 mask register + (OTG_FS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK6 + FS_HCINTMSK6 + OTG_FS host channel-6 mask register + (OTG_FS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK7 + FS_HCINTMSK7 + OTG_FS host channel-7 mask register + (OTG_FS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCTSIZ0 + FS_HCTSIZ0 + OTG_FS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ1 + FS_HCTSIZ1 + OTG_FS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ2 + FS_HCTSIZ2 + OTG_FS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ3 + FS_HCTSIZ3 + OTG_FS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ4 + FS_HCTSIZ4 + OTG_FS host channel-x transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ5 + FS_HCTSIZ5 + OTG_FS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ6 + FS_HCTSIZ6 + OTG_FS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ7 + FS_HCTSIZ7 + OTG_FS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + + + OTG_FS_DEVICE + USB on the go full speed + USB_OTG_FS + 0x50000800 + + 0x0 + 0x400 + registers + + + + FS_DCFG + FS_DCFG + OTG_FS device configuration register + (OTG_FS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DSPD + Device speed + 0 + 2 + + + NZLSOHSK + Non-zero-length status OUT + handshake + 2 + 1 + + + DAD + Device address + 4 + 7 + + + PFIVL + Periodic frame interval + 11 + 2 + + + + + FS_DCTL + FS_DCTL + OTG_FS device control register + (OTG_FS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWUSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SDIS + Soft disconnect + 1 + 1 + read-write + + + GINSTS + Global IN NAK status + 2 + 1 + read-only + + + GONSTS + Global OUT NAK status + 3 + 1 + read-only + + + TCTL + Test control + 4 + 3 + read-write + + + SGINAK + Set global IN NAK + 7 + 1 + read-write + + + CGINAK + Clear global IN NAK + 8 + 1 + read-write + + + SGONAK + Set global OUT NAK + 9 + 1 + read-write + + + CGONAK + Clear global OUT NAK + 10 + 1 + read-write + + + POPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + FS_DSTS + FS_DSTS + OTG_FS device status register + (OTG_FS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + EERR + Erratic error + 3 + 1 + + + FNSOF + Frame number of the received + SOF + 8 + 14 + + + + + FS_DIEPMSK + FS_DIEPMSK + OTG_FS device IN endpoint common interrupt + mask register (OTG_FS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + + + FS_DOEPMSK + FS_DOEPMSK + OTG_FS device OUT endpoint common interrupt + mask register (OTG_FS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + STUPM + SETUP phase done mask + 3 + 1 + + + OTEPDM + OUT token received when endpoint + disabled mask + 4 + 1 + + + + + FS_DAINT + FS_DAINT + OTG_FS device all endpoints interrupt + register (OTG_FS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + IEPINT + IN endpoint interrupt bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + FS_DAINTMSK + FS_DAINTMSK + OTG_FS all endpoints interrupt mask register + (OTG_FS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + IEPM + IN EP interrupt mask bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DVBUSDIS + DVBUSDIS + OTG_FS device VBUS discharge time + register + 0x28 + 0x20 + read-write + 0x000017D7 + + + VBUSDT + Device VBUS discharge time + 0 + 16 + + + + + DVBUSPULSE + DVBUSPULSE + OTG_FS device VBUS pulsing time + register + 0x2C + 0x20 + read-write + 0x000005B8 + + + DVBUSP + Device VBUS pulsing time + 0 + 12 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTG_FS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEM + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + FS_DIEPCTL0 + FS_DIEPCTL0 + OTG_FS device control IN endpoint 0 control + register (OTG_FS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 2 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-only + + + EPENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTG device endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM_SD1PID + SODDFRM/SD1PID + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + Stall + Stall + 21 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTG device endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + Stall + Stall + 21 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTG device endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + Stall + Stall + 21 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DOEPCTL0 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+ 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + Stall + Stall + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DIEPINT0 + DIEPINT0 + device endpoint-x interrupt + register + 0x108 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DIEPINT1 + DIEPINT1 + device endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DIEPINT2 + DIEPINT2 + device endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DIEPINT3 + DIEPINT3 + device endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DOEPINT0 + DOEPINT0 + device endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DOEPINT1 + DOEPINT1 + device endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DOEPINT2 + DOEPINT2 + device endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DOEPINT3 + DOEPINT3 + device endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + device endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + PKTCNT + Packet count + 19 + 2 + + + XFRSIZ + Transfer size + 0 + 7 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + STUPCNT + SETUP packet count + 29 + 2 + + + PKTCNT + Packet count + 19 + 1 + + + XFRSIZ + Transfer size + 0 + 7 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + device endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + MCNT + Multi count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + device endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + MCNT + Multi count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + device endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + MCNT + Multi count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DTXFSTS0 + DTXFSTS0 + OTG_FS device IN endpoint transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTG_FS device IN endpoint transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTG_FS device IN endpoint transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTG_FS device IN endpoint transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + + + OTG_FS_PWRCLK + USB on the go full speed + USB_OTG_FS + 0x50000E00 + + 0x0 + 0x400 + registers + + + + FS_PCGCCTL + FS_PCGCCTL + OTG_FS power and clock gating control + register + 0x0 + 0x20 + read-write + 0x00000000 + + + STPPCLK + Stop PHY clock + 0 + 1 + + + GATEHCLK + Gate HCLK + 1 + 1 + + + PHYSUSP + PHY Suspended + 4 + 1 + + + + + + + CAN1 + Controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN1_TX + CAN1 TX interrupts + 19 + + + CAN1_RX0 + CAN1 RX0 interrupts + 20 + + + CAN1_RX1 + CAN1 RX1 interrupts + 21 + + + CAN1_SCE + CAN1 SCE interrupt + 22 + + + + MCR + MCR + master control register + 0x0 + 0x20 + read-write + 0x00010002 + + + DBF + DBF + 16 + 1 + + + RESET + RESET + 15 + 1 + + + TTCM + TTCM + 7 + 1 + + + ABOM + ABOM + 6 + 1 + + + AWUM + AWUM + 5 + 1 + + + NART + NART + 4 + 1 + + + RFLM + RFLM + 3 + 1 + + + TXFP + TXFP + 2 + 1 + + + SLEEP + SLEEP + 1 + 1 + + + INRQ + INRQ + 0 + 1 + + + + + MSR + MSR + master status register + 0x4 + 0x20 + 0x00000C02 + + + RX + RX + 11 + 1 + read-only + + + SAMP + SAMP + 10 + 1 + read-only + + + RXM + RXM + 9 + 1 + read-only + + + TXM + TXM + 8 + 1 + read-only + + + SLAKI + SLAKI + 4 + 1 + read-write + + + WKUI + WKUI + 3 + 1 + read-write + + + ERRI + ERRI + 2 + 1 + read-write + + + SLAK + SLAK + 1 + 1 + read-only + + + INAK + INAK + 0 + 1 + read-only + + + + + TSR + TSR + transmit status register + 0x8 + 0x20 + 0x1C000000 + + + LOW2 + Lowest priority flag for mailbox + 2 + 31 + 1 + read-only + + + LOW1 + Lowest priority flag for mailbox + 1 + 30 + 1 + read-only + + + LOW0 + Lowest priority flag for mailbox + 0 + 29 + 1 + read-only + + + TME2 + Lowest priority flag for mailbox + 2 + 28 + 1 + read-only + + + TME1 + Lowest priority flag for mailbox + 1 + 27 + 1 + read-only + + + TME0 + Lowest priority flag for mailbox + 0 + 26 + 1 + read-only + + + CODE + CODE + 24 + 2 + read-only + + + ABRQ2 + ABRQ2 + 23 + 1 + read-write + + + TERR2 + TERR2 + 19 + 1 + read-write + + + ALST2 + ALST2 + 18 + 1 + read-write + + + TXOK2 + TXOK2 + 17 + 1 + read-write + + + RQCP2 + RQCP2 + 16 + 1 + read-write + + + ABRQ1 + ABRQ1 + 15 + 1 + read-write + + + TERR1 + TERR1 + 11 + 1 + read-write + + + ALST1 + ALST1 + 10 + 1 + read-write + + + TXOK1 + TXOK1 + 9 + 1 + read-write + + + RQCP1 + RQCP1 + 8 + 1 + read-write + + + ABRQ0 + ABRQ0 + 7 + 1 + read-write + + + TERR0 + TERR0 + 3 + 1 + read-write + + + ALST0 + ALST0 + 2 + 1 + read-write + + + TXOK0 + TXOK0 + 1 + 1 + read-write + + + RQCP0 + RQCP0 + 0 + 1 + read-write + + + + + RF0R + RF0R + receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RFOM0 + RFOM0 + 5 + 1 + read-write + + + FOVR0 + FOVR0 + 4 + 1 + read-write + + + FULL0 + FULL0 + 3 + 1 + read-write + + + FMP0 + FMP0 + 0 + 2 + read-only + + + + + RF1R + RF1R + receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RFOM1 + RFOM1 + 5 + 1 + read-write + + + FOVR1 + FOVR1 + 4 + 1 + read-write + + + FULL1 + FULL1 + 3 + 1 + read-write + + + FMP1 + FMP1 + 0 + 2 + read-only + + + + + IER + IER + interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + SLKIE + SLKIE + 17 + 1 + + + WKUIE + WKUIE + 16 + 1 + + + ERRIE + ERRIE + 15 + 1 + + + LECIE + LECIE + 11 + 1 + + + BOFIE + BOFIE + 10 + 1 + + + EPVIE + EPVIE + 9 + 1 + + + EWGIE + EWGIE + 8 + 1 + + + FOVIE1 + FOVIE1 + 6 + 1 + + + FFIE1 + FFIE1 + 5 + 1 + + + FMPIE1 + FMPIE1 + 4 + 1 + + + FOVIE0 + FOVIE0 + 3 + 1 + + + FFIE0 + FFIE0 + 2 + 1 + + + FMPIE0 + FMPIE0 + 1 + 1 + + + TMEIE + TMEIE + 0 + 1 + + + + + ESR + ESR + interrupt enable register + 0x18 + 0x20 + 0x00000000 + + + REC + REC + 24 + 8 + read-only + + + TEC + TEC + 16 + 8 + read-only + + + LEC + LEC + 4 + 3 + read-write + + + BOFF + BOFF + 2 + 1 + read-only + + + EPVF + EPVF + 1 + 1 + read-only + + + EWGF + EWGF + 0 + 1 + read-only + + + + + BTR + BTR + bit timing register + 0x1C + 0x20 + read-write + 0x00000000 + + + SILM + SILM + 31 + 1 + + + LBKM + LBKM + 30 + 1 + + + SJW + SJW + 24 + 2 + + + TS2 + TS2 + 20 + 3 + + + TS1 + TS1 + 16 + 4 + + + BRP + BRP + 0 + 10 + + + + + TI0R + TI0R + TX mailbox identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + STID + STID + 21 + 11 + + + EXID + EXID + 3 + 18 + + + IDE + IDE + 2 + 1 + + + RTR + RTR + 1 + 1 + + + TXRQ + TXRQ + 0 + 1 + + + + + TDT0R + TDT0R + mailbox data length control and time stamp + register + 0x184 + 0x20 + read-write + 0x00000000 + + + TIME + TIME + 16 + 16 + + + TGT + TGT + 8 + 1 + + + DLC + DLC + 0 + 4 + + + + + TDL0R + TDL0R + mailbox data low register + 0x188 + 0x20 + read-write + 0x00000000 + + + DATA3 + DATA3 + 24 + 8 + + + DATA2 + DATA2 + 16 + 8 + + + DATA1 + DATA1 + 8 + 8 + + + DATA0 + DATA0 + 0 + 8 + + + + + TDH0R + TDH0R + mailbox data high register + 0x18C + 0x20 + read-write + 0x00000000 + + + DATA7 + DATA7 + 24 + 8 + + + DATA6 + DATA6 + 16 + 8 + + + DATA5 + DATA5 + 8 + 8 + + + DATA4 + DATA4 + 0 + 8 + + + + + TI1R + TI1R + mailbox identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + STID + STID + 21 + 11 + + + EXID + EXID + 3 + 18 + + + IDE + IDE + 2 + 1 + + + RTR + RTR + 1 + 1 + + + TXRQ + TXRQ + 0 + 1 + + + + + TDT1R + TDT1R + mailbox data length control and time stamp + register + 0x194 + 0x20 + read-write + 0x00000000 + + + TIME + TIME + 16 + 16 + + + TGT + TGT + 8 + 1 + + + DLC + DLC + 0 + 4 + + + + + TDL1R + TDL1R + mailbox data low register + 0x198 + 0x20 + read-write + 0x00000000 + + + DATA3 + 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Interrupt on line + 2 + 2 + 1 + + + SWIER3 + Software Interrupt on line + 3 + 3 + 1 + + + SWIER4 + Software Interrupt on line + 4 + 4 + 1 + + + SWIER5 + Software Interrupt on line + 5 + 5 + 1 + + + SWIER6 + Software Interrupt on line + 6 + 6 + 1 + + + SWIER7 + Software Interrupt on line + 7 + 7 + 1 + + + SWIER8 + Software Interrupt on line + 8 + 8 + 1 + + + SWIER9 + Software Interrupt on line + 9 + 9 + 1 + + + SWIER10 + Software Interrupt on line + 10 + 10 + 1 + + + SWIER11 + Software Interrupt on line + 11 + 11 + 1 + + + SWIER12 + Software Interrupt on line + 12 + 12 + 1 + + + SWIER13 + Software Interrupt on line + 13 + 13 + 1 + + + SWIER14 + Software Interrupt on line + 14 + 14 + 1 + + + SWIER15 + Software Interrupt on line + 15 + 15 + 1 + + + SWIER16 + Software Interrupt on line + 16 + 16 + 1 + + + SWIER17 + Software Interrupt on line + 17 + 17 + 1 + + + SWIER18 + Software Interrupt on line + 18 + 18 + 1 + + + SWIER19 + Software Interrupt on line + 19 + 19 + 1 + + + SWIER20 + Software Interrupt on line + 20 + 20 + 1 + + + SWIER21 + Software Interrupt on line + 21 + 21 + 1 + + + SWIER22 + Software Interrupt on line + 22 + 22 + 1 + + + + + PR + PR + Pending register (EXTI_PR) + 0x14 + 0x20 + read-write + 0x00000000 + + + PR0 + Pending bit 0 + 0 + 1 + + + PR1 + Pending bit 1 + 1 + 1 + + + PR2 + Pending bit 2 + 2 + 1 + + + PR3 + Pending bit 3 + 3 + 1 + + + PR4 + Pending bit 4 + 4 + 1 + + + PR5 + Pending bit 5 + 5 + 1 + + + PR6 + Pending bit 6 + 6 + 1 + + + PR7 + Pending bit 7 + 7 + 1 + + + PR8 + Pending bit 8 + 8 + 1 + + + PR9 + Pending bit 9 + 9 + 1 + + + PR10 + Pending bit 10 + 10 + 1 + + + PR11 + Pending bit 11 + 11 + 1 + + + PR12 + Pending bit 12 + 12 + 1 + + + PR13 + Pending bit 13 + 13 + 1 + + + PR14 + Pending bit 14 + 14 + 1 + + + PR15 + Pending bit 15 + 15 + 1 + + + PR16 + Pending bit 16 + 16 + 1 + + + PR17 + Pending bit 17 + 17 + 1 + + + PR18 + Pending bit 18 + 18 + 1 + + + PR19 + Pending bit 19 + 19 + 1 + + + PR20 + Pending bit 20 + 20 + 1 + + + PR21 + Pending bit 21 + 21 + 1 + + + PR22 + Pending bit 22 + 22 + 1 + + + + + + + OTG_HS_GLOBAL + USB on the go high speed + USB_OTG_HS + 0x40040000 + + 0x0 + 0xFFFC0400 + registers + + + 0xFFFC0400 + 0x40000 + reserved + + + OTG_HS_EP1_OUT + USB On The Go HS End Point 1 Out global + interrupt + 74 + + + OTG_HS_EP1_IN + USB On The Go HS End Point 1 In global + interrupt + 75 + + + OTG_HS_WKUP + USB On The Go HS Wakeup through EXTI + interrupt + 76 + + + OTG_HS + USB On The Go HS global + interrupt + 77 + + + + OTG_HS_GOTGCTL + OTG_HS_GOTGCTL + OTG_HS control and status + register + 0x0 + 32 + 0x00000800 + + + SRQSCS + Session request success + 0 + 1 + read-only + + + SRQ + Session request + 1 + 1 + read-write + + + HNGSCS + Host negotiation success + 8 + 1 + read-only + + + HNPRQ + HNP request + 9 + 1 + read-write + + + HSHNPEN + Host set HNP enable + 10 + 1 + read-write + + + DHNPEN + Device HNP enabled + 11 + 1 + read-write + + + CIDSTS + Connector ID status + 16 + 1 + read-only + + + DBCT + Long/short debounce time + 17 + 1 + read-only + + + ASVLD + A-session valid + 18 + 1 + read-only + + + BSVLD + B-session valid + 19 + 1 + read-only + + + + + OTG_HS_GOTGINT + OTG_HS_GOTGINT + OTG_HS interrupt register + 0x4 + 32 + read-write + 0x0 + + + SEDET + Session end detected + 2 + 1 + + + SRSSCHG + Session request success status + change + 8 + 1 + + + HNSSCHG + Host negotiation success status + change + 9 + 1 + + + HNGDET + Host negotiation detected + 17 + 1 + + + ADTOCHG + A-device timeout change + 18 + 1 + + + DBCDNE + Debounce done + 19 + 1 + + + + + OTG_HS_GAHBCFG + OTG_HS_GAHBCFG + OTG_HS AHB configuration + register + 0x8 + 32 + read-write + 0x0 + + + GINT + Global interrupt mask + 0 + 1 + + + HBSTLEN + Burst length/type + 1 + 4 + + + DMAEN + DMA enable + 5 + 1 + + + TXFELVL + TxFIFO empty level + 7 + 1 + + + PTXFELVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + OTG_HS_GUSBCFG + OTG_HS_GUSBCFG + OTG_HS USB configuration + register + 0xC + 32 + 0x00000A00 + + + TOCAL + FS timeout calibration + 0 + 3 + read-write + + + PHYSEL + USB 2.0 high-speed ULPI PHY or USB 1.1 + full-speed serial transceiver select + 6 + 1 + write-only + + + SRPCAP + SRP-capable + 8 + 1 + read-write + + + HNPCAP + HNP-capable + 9 + 1 + read-write + + + TRDT + USB turnaround time + 10 + 4 + read-write + + + PHYLPCS + PHY Low-power clock select + 15 + 1 + read-write + + + ULPIFSLS + ULPI FS/LS select + 17 + 1 + read-write + + + ULPIAR + ULPI Auto-resume + 18 + 1 + read-write + + + ULPICSM + ULPI Clock SuspendM + 19 + 1 + read-write + + + ULPIEVBUSD + ULPI External VBUS Drive + 20 + 1 + read-write + + + ULPIEVBUSI + ULPI external VBUS + indicator + 21 + 1 + read-write + + + TSDPS + TermSel DLine pulsing + selection + 22 + 1 + read-write + + + PCCI + Indicator complement + 23 + 1 + read-write + + + PTCI + Indicator pass through + 24 + 1 + read-write + + + ULPIIPD + ULPI interface protect + disable + 25 + 1 + read-write + + + FHMOD + Forced host mode + 29 + 1 + read-write + + + FDMOD + Forced peripheral mode + 30 + 1 + read-write + + + CTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + OTG_HS_GRSTCTL + OTG_HS_GRSTCTL + OTG_HS reset register + 0x10 + 32 + 0x20000000 + + + CSRST + Core soft reset + 0 + 1 + read-write + + + HSRST + HCLK soft reset + 1 + 1 + read-write + + + FCRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + DMAREQ + DMA request signal + 30 + 1 + read-only + + + AHBIDL + AHB master idle + 31 + 1 + read-only + + + + + OTG_HS_GINTSTS + OTG_HS_GINTSTS + OTG_HS core interrupt register + 0x14 + 32 + 0x04000020 + + + CMOD + Current mode of operation + 0 + 1 + read-only + + + MMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO nonempty + 4 + 1 + read-only + + + NPTXFE + Nonperiodic TxFIFO empty + 5 + 1 + read-only + + + GINAKEFF + Global IN nonperiodic NAK + effective + 6 + 1 + read-only + + + BOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ESUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDNE + Enumeration done + 13 + 1 + read-write + + + ISOODRP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPINT + OUT endpoint interrupt + 19 + 1 + read-only + + + IISOIXFR + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + PXFR_INCOMPISOOUT + Incomplete periodic + transfer + 21 + 1 + read-write + + + DATAFSUSP + Data fetch suspended + 22 + 1 + read-write + + + HPRTINT + Host port interrupt + 24 + 1 + read-only + + + HCINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFE + Periodic TxFIFO empty + 26 + 1 + read-only + + + CIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + SRQINT + Session request/new session detected + interrupt + 30 + 1 + read-write + + + WKUINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + OTG_HS_GINTMSK + OTG_HS_GINTMSK + OTG_HS interrupt mask register + 0x18 + 32 + 0x0 + + + MMISM + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINT + OTG interrupt mask + 2 + 1 + read-write + + + SOFM + Start of frame mask + 3 + 1 + read-write + + + RXFLVLM + Receive FIFO nonempty mask + 4 + 1 + read-write + + + NPTXFEM + Nonperiodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINAKEFFM + Global nonperiodic IN NAK effective + mask + 6 + 1 + read-write + + + GONAKEFFM + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ESUSPM + Early suspend mask + 10 + 1 + read-write + + + USBSUSPM + USB suspend mask + 11 + 1 + read-write + + + USBRST + USB reset mask + 12 + 1 + read-write + + + ENUMDNEM + Enumeration done mask + 13 + 1 + read-write + + + ISOODRPM + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFM + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + EPMISM + Endpoint mismatch interrupt + mask + 17 + 1 + read-write + + + IEPINT + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPINT + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + IISOIXFRM + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + PXFRM_IISOOXFRM + Incomplete periodic transfer + mask + 21 + 1 + read-write + + + FSUSPM + Data fetch suspended mask + 22 + 1 + read-write + + + PRTIM + Host port interrupt mask + 24 + 1 + read-only + + + HCIM + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEM + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CIDSCHGM + Connector ID status change + mask + 28 + 1 + read-write + + + DISCINT + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + SRQIM + Session request/new session detected + interrupt mask + 30 + 1 + read-write + + + WUIM + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + OTG_HS_GRXSTSR_Host + OTG_HS_GRXSTSR_Host + OTG_HS Receive status debug read register + (host mode) + 0x1C + 32 + read-only + 0x0 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + OTG_HS_GRXSTSP_Host + OTG_HS_GRXSTSP_Host + OTG_HS status read and pop register (host + mode) + 0x20 + 32 + read-only + 0x0 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + OTG_HS_GRXFSIZ + OTG_HS_GRXFSIZ + OTG_HS Receive FIFO size + register + 0x24 + 32 + read-write + 0x00000200 + + + RXFD + RxFIFO depth + 0 + 16 + + + + + OTG_HS_GNPTXFSIZ_Host + OTG_HS_GNPTXFSIZ_Host + OTG_HS nonperiodic transmit FIFO size + register (host mode) + 0x28 + 32 + read-write + 0x00000200 + + + NPTXFSA + Nonperiodic transmit RAM start + address + 0 + 16 + + + NPTXFD + Nonperiodic TxFIFO depth + 16 + 16 + + + + + OTG_HS_TX0FSIZ_Peripheral + OTG_HS_TX0FSIZ_Peripheral + Endpoint 0 transmit FIFO size (peripheral + mode) + OTG_HS_GNPTXFSIZ_Host + 0x28 + 32 + read-write + 0x00000200 + + + TX0FSA + Endpoint 0 transmit RAM start + address + 0 + 16 + + + TX0FD + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + OTG_HS_GNPTXSTS + OTG_HS_GNPTXSTS + OTG_HS nonperiodic transmit FIFO/queue + status register + 0x2C + 32 + read-only + 0x00080200 + + + NPTXFSAV + Nonperiodic TxFIFO space + available + 0 + 16 + + + NPTQXSAV + Nonperiodic transmit request queue space + available + 16 + 8 + + + NPTXQTOP + Top of the nonperiodic transmit request + queue + 24 + 7 + + + + + OTG_HS_GCCFG + OTG_HS_GCCFG + OTG_HS general core configuration + register + 0x38 + 32 + read-write + 0x0 + + + PWRDWN + Power down + 16 + 1 + + + I2CPADEN + Enable I2C bus connection for the + external I2C PHY interface + 17 + 1 + + + VBUSASEN + Enable the VBUS sensing + device + 18 + 1 + + + VBUSBSEN + Enable the VBUS sensing device + 19 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + NOVBUSSENS + VBUS sensing disable + option + 21 + 1 + + + + + OTG_HS_CID + OTG_HS_CID + OTG_HS core ID register + 0x3C + 32 + read-write + 0x00001200 + + + PRODUCT_ID + Product ID field + 0 + 32 + + + + + OTG_HS_HPTXFSIZ + OTG_HS_HPTXFSIZ + OTG_HS Host periodic transmit FIFO size + register + 0x100 + 32 + read-write + 0x02000600 + + + PTXSA + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFD + Host periodic TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF1 + OTG_HS_DIEPTXF1 + OTG_HS device IN endpoint transmit FIFO size + register + 0x104 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF2 + OTG_HS_DIEPTXF2 + OTG_HS device IN endpoint transmit FIFO size + register + 0x108 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF3 + OTG_HS_DIEPTXF3 + OTG_HS device IN endpoint transmit FIFO size + register + 0x11C + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF4 + OTG_HS_DIEPTXF4 + OTG_HS device IN endpoint transmit FIFO size + register + 0x120 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF5 + OTG_HS_DIEPTXF5 + OTG_HS device IN endpoint transmit FIFO size + register + 0x124 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF6 + OTG_HS_DIEPTXF6 + OTG_HS device IN endpoint transmit FIFO size + register + 0x128 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF7 + OTG_HS_DIEPTXF7 + OTG_HS device IN endpoint transmit FIFO size + register + 0x12C + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_GRXSTSR_Peripheral + OTG_HS_GRXSTSR_Peripheral + OTG_HS Receive status debug read register + (peripheral mode mode) + OTG_HS_GRXSTSR_Host + 0x1C + 32 + read-only + 0x0 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + OTG_HS_GRXSTSP_Peripheral + OTG_HS_GRXSTSP_Peripheral + OTG_HS status read and pop register + (peripheral mode) + OTG_HS_GRXSTSP_Host + 0x20 + 32 + read-only + 0x0 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + + + OTG_HS_HOST + USB on the go high speed + USB_OTG_HS + 0x40040400 + + 0x0 + 0x400 + registers + + + + OTG_HS_HCFG + OTG_HS_HCFG + OTG_HS host configuration + register + 0x0 + 32 + 0x0 + + + FSLSPCS + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSS + FS- and LS-only support + 2 + 1 + read-only + + + + + OTG_HS_HFIR + OTG_HS_HFIR + OTG_HS Host frame interval + register + 0x4 + 32 + read-write + 0x0000EA60 + + + FRIVL + Frame interval + 0 + 16 + + + + + OTG_HS_HFNUM + OTG_HS_HFNUM + OTG_HS host frame number/frame time + remaining register + 0x8 + 32 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + OTG_HS_HPTXSTS + OTG_HS_HPTXSTS + OTG_HS_Host periodic transmit FIFO/queue + status register + 0x10 + 32 + 0x00080100 + + + PTXFSAVL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSAV + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + OTG_HS_HAINT + OTG_HS_HAINT + OTG_HS Host all channels interrupt + register + 0x14 + 32 + read-only + 0x0 + + + HAINT + Channel interrupts + 0 + 16 + + + + + OTG_HS_HAINTMSK + OTG_HS_HAINTMSK + OTG_HS host all channels interrupt mask + register + 0x18 + 32 + read-write + 0x0 + + + HAINTM + Channel interrupt mask + 0 + 16 + + + + + OTG_HS_HPRT + OTG_HS_HPRT + OTG_HS host port control and status + register + 0x40 + 32 + 0x0 + + + PCSTS + Port connect status + 0 + 1 + read-only + + + PCDET + Port connect detected + 1 + 1 + read-write + + + PENA + Port enable + 2 + 1 + read-write + + + PENCHNG + Port enable/disable change + 3 + 1 + read-write + + + POCA + Port overcurrent active + 4 + 1 + read-only + + + POCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRES + Port resume + 6 + 1 + read-write + + + PSUSP + Port suspend + 7 + 1 + read-write + + + PRST + Port reset + 8 + 1 + read-write + + + PLSTS + Port line status + 10 + 2 + read-only + + + PPWR + Port power + 12 + 1 + read-write + + + PTCTL + Port test control + 13 + 4 + read-write + + + PSPD + Port speed + 17 + 2 + read-only + + + + + OTG_HS_HCCHAR0 + OTG_HS_HCCHAR0 + OTG_HS host channel-0 characteristics + register + 0x100 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR1 + OTG_HS_HCCHAR1 + OTG_HS host channel-1 characteristics + register + 0x120 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR2 + OTG_HS_HCCHAR2 + OTG_HS host channel-2 characteristics + register + 0x140 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR3 + OTG_HS_HCCHAR3 + OTG_HS host channel-3 characteristics + register + 0x160 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR4 + OTG_HS_HCCHAR4 + OTG_HS host channel-4 characteristics + register + 0x180 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR5 + OTG_HS_HCCHAR5 + OTG_HS host channel-5 characteristics + register + 0x1A0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR6 + OTG_HS_HCCHAR6 + OTG_HS host channel-6 characteristics + register + 0x1C0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR7 + OTG_HS_HCCHAR7 + OTG_HS host channel-7 characteristics + register + 0x1E0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR8 + OTG_HS_HCCHAR8 + OTG_HS host channel-8 characteristics + register + 0x200 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR9 + OTG_HS_HCCHAR9 + OTG_HS host channel-9 characteristics + register + 0x220 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR10 + OTG_HS_HCCHAR10 + OTG_HS host channel-10 characteristics + register + 0x240 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + 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interrupt mask + register + 0x10C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK1 + OTG_HS_HCINTMSK1 + OTG_HS host channel-1 interrupt mask + register + 0x12C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK 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+ Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK9 + OTG_HS_HCINTMSK9 + OTG_HS host channel-9 interrupt mask + register + 0x22C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK10 + OTG_HS_HCINTMSK10 + OTG_HS host channel-10 interrupt mask + register + 0x24C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK11 + OTG_HS_HCINTMSK11 + OTG_HS host channel-11 interrupt mask + register + 0x26C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCTSIZ0 + OTG_HS_HCTSIZ0 + OTG_HS host channel-11 transfer size + register + 0x110 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ1 + OTG_HS_HCTSIZ1 + OTG_HS host channel-1 transfer size + register + 0x130 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ2 + OTG_HS_HCTSIZ2 + OTG_HS host channel-2 transfer size + register + 0x150 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ3 + OTG_HS_HCTSIZ3 + OTG_HS host channel-3 transfer size + register + 0x170 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ4 + OTG_HS_HCTSIZ4 + OTG_HS host channel-4 transfer size + register + 0x190 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ5 + OTG_HS_HCTSIZ5 + OTG_HS host channel-5 transfer size + register + 0x1B0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ6 + OTG_HS_HCTSIZ6 + OTG_HS host channel-6 transfer size + register + 0x1D0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ7 + OTG_HS_HCTSIZ7 + OTG_HS host channel-7 transfer size + register + 0x1F0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ8 + OTG_HS_HCTSIZ8 + OTG_HS host channel-8 transfer size + register + 0x210 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ9 + OTG_HS_HCTSIZ9 + OTG_HS host channel-9 transfer size + register + 0x230 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ10 + OTG_HS_HCTSIZ10 + OTG_HS host channel-10 transfer size + register + 0x250 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ11 + OTG_HS_HCTSIZ11 + OTG_HS host channel-11 transfer size + register + 0x270 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCDMA0 + OTG_HS_HCDMA0 + OTG_HS host channel-0 DMA address + register + 0x114 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA1 + OTG_HS_HCDMA1 + OTG_HS host channel-1 DMA address + register + 0x134 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA2 + OTG_HS_HCDMA2 + OTG_HS host channel-2 DMA address + register + 0x154 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA3 + OTG_HS_HCDMA3 + OTG_HS host channel-3 DMA address + register + 0x174 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA4 + OTG_HS_HCDMA4 + OTG_HS host channel-4 DMA address + register + 0x194 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA5 + OTG_HS_HCDMA5 + OTG_HS host channel-5 DMA address + register + 0x1B4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA6 + OTG_HS_HCDMA6 + OTG_HS host channel-6 DMA address + register + 0x1D4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA7 + OTG_HS_HCDMA7 + OTG_HS host channel-7 DMA address + register + 0x1F4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA8 + OTG_HS_HCDMA8 + OTG_HS host channel-8 DMA address + register + 0x214 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA9 + OTG_HS_HCDMA9 + OTG_HS host channel-9 DMA address + register + 0x234 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA10 + OTG_HS_HCDMA10 + OTG_HS host channel-10 DMA address + register + 0x254 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA11 + OTG_HS_HCDMA11 + OTG_HS host channel-11 DMA address + register + 0x274 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + + + OTG_HS_DEVICE + USB on the go high speed + USB_OTG_HS + 0x40040800 + + 0x0 + 0x400 + registers + + + + OTG_HS_DCFG + OTG_HS_DCFG + OTG_HS device configuration + register + 0x0 + 32 + read-write + 0x02200000 + + + DSPD + Device speed + 0 + 2 + + + NZLSOHSK + Nonzero-length status OUT + handshake + 2 + 1 + + + DAD + Device address + 4 + 7 + + + PFIVL + Periodic (micro)frame + interval + 11 + 2 + + + PERSCHIVL + Periodic scheduling + interval + 24 + 2 + + + + + OTG_HS_DCTL + OTG_HS_DCTL + OTG_HS device control register + 0x4 + 32 + 0x0 + + + RWUSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SDIS + Soft disconnect + 1 + 1 + read-write + + + GINSTS + Global IN NAK status + 2 + 1 + read-only + + + GONSTS + Global OUT NAK status + 3 + 1 + read-only + + + TCTL + Test control + 4 + 3 + read-write + + + SGINAK + Set global IN NAK + 7 + 1 + write-only + + + CGINAK + Clear global IN NAK + 8 + 1 + write-only + + + SGONAK + Set global OUT NAK + 9 + 1 + write-only + + + CGONAK + Clear global OUT NAK + 10 + 1 + write-only + + + POPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + OTG_HS_DSTS + OTG_HS_DSTS + OTG_HS device status register + 0x8 + 32 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + EERR + Erratic error + 3 + 1 + + + FNSOF + Frame number of the received + SOF + 8 + 14 + + + + + OTG_HS_DIEPMSK + OTG_HS_DIEPMSK + OTG_HS device IN endpoint common interrupt + mask register + 0x10 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask (nonisochronous + endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + TXFURM + FIFO underrun mask + 8 + 1 + + + BIM + BNA interrupt mask + 9 + 1 + + + + + OTG_HS_DOEPMSK + OTG_HS_DOEPMSK + OTG_HS device OUT endpoint common interrupt + mask register + 0x14 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + STUPM + SETUP phase done mask + 3 + 1 + + + OTEPDM + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets received + mask + 6 + 1 + + + OPEM + OUT packet error mask + 8 + 1 + + + BOIM + BNA interrupt mask + 9 + 1 + + + + + OTG_HS_DAINT + OTG_HS_DAINT + OTG_HS device all endpoints interrupt + register + 0x18 + 32 + read-only + 0x0 + + + IEPINT + IN endpoint interrupt bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + OTG_HS_DAINTMSK + OTG_HS_DAINTMSK + OTG_HS all endpoints interrupt mask + register + 0x1C + 32 + read-write + 0x0 + + + IEPM + IN EP interrupt mask bits + 0 + 16 + + + OEPM + OUT EP interrupt mask bits + 16 + 16 + + + + + OTG_HS_DVBUSDIS + OTG_HS_DVBUSDIS + OTG_HS device VBUS discharge time + register + 0x28 + 32 + read-write + 0x000017D7 + + + VBUSDT + Device VBUS discharge time + 0 + 16 + + + + + OTG_HS_DVBUSPULSE + OTG_HS_DVBUSPULSE + OTG_HS device VBUS pulsing time + register + 0x2C + 32 + read-write + 0x000005B8 + + + DVBUSP + Device VBUS pulsing time + 0 + 12 + + + + + OTG_HS_DTHRCTL + OTG_HS_DTHRCTL + OTG_HS Device threshold control + register + 0x30 + 32 + read-write + 0x0 + + + NONISOTHREN + Nonisochronous IN endpoints threshold + enable + 0 + 1 + + + ISOTHREN + ISO IN endpoint threshold + enable + 1 + 1 + + + TXTHRLEN + Transmit threshold length + 2 + 9 + + + RXTHREN + Receive threshold enable + 16 + 1 + + + RXTHRLEN + Receive threshold length + 17 + 9 + + + ARPEN + Arbiter parking enable + 27 + 1 + + + + + OTG_HS_DIEPEMPMSK + OTG_HS_DIEPEMPMSK + OTG_HS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 32 + read-write + 0x0 + + + INEPTXFEM + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + OTG_HS_DEACHINT + OTG_HS_DEACHINT + OTG_HS device each endpoint interrupt + register + 0x38 + 32 + read-write + 0x0 + + + IEP1INT + IN endpoint 1interrupt bit + 1 + 1 + + + OEP1INT + OUT endpoint 1 interrupt + bit + 17 + 1 + + + + + OTG_HS_DEACHINTMSK + OTG_HS_DEACHINTMSK + OTG_HS device each endpoint interrupt + register mask + 0x3C + 32 + read-write + 0x0 + + + IEP1INTM + IN Endpoint 1 interrupt mask + bit + 1 + 1 + + + OEP1INTM + OUT Endpoint 1 interrupt mask + bit + 17 + 1 + + + + + OTG_HS_DIEPEACHMSK1 + OTG_HS_DIEPEACHMSK1 + OTG_HS device each in endpoint-1 interrupt + register + 0x40 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask (nonisochronous + endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + TXFURM + FIFO underrun mask + 8 + 1 + + + BIM + BNA interrupt mask + 9 + 1 + + + NAKM + NAK interrupt mask + 13 + 1 + + + + + OTG_HS_DOEPEACHMSK1 + OTG_HS_DOEPEACHMSK1 + OTG_HS device each OUT endpoint-1 interrupt + register + 0x80 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + TXFURM + OUT packet error mask + 8 + 1 + + + BIM + BNA interrupt mask + 9 + 1 + + + BERRM + Bubble error interrupt + mask + 12 + 1 + + + NAKM + NAK interrupt mask + 13 + 1 + + + NYETM + NYET interrupt mask + 14 + 1 + + + + + OTG_HS_DIEPCTL0 + OTG_HS_DIEPCTL0 + OTG device endpoint-0 control + register + 0x100 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL1 + OTG_HS_DIEPCTL1 + OTG device endpoint-1 control + register + 0x120 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL2 + OTG_HS_DIEPCTL2 + OTG device endpoint-2 control + register + 0x140 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL3 + OTG_HS_DIEPCTL3 + OTG device endpoint-3 control + register + 0x160 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL4 + OTG_HS_DIEPCTL4 + OTG device endpoint-4 control + register + 0x180 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL5 + OTG_HS_DIEPCTL5 + OTG device endpoint-5 control + register + 0x1A0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL6 + OTG_HS_DIEPCTL6 + OTG device endpoint-6 control + register + 0x1C0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL7 + OTG_HS_DIEPCTL7 + OTG device endpoint-7 control + register + 0x1E0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPINT0 + OTG_HS_DIEPINT0 + OTG device endpoint-0 interrupt + register + 0x108 + 32 + 0x00000080 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT1 + OTG_HS_DIEPINT1 + OTG device endpoint-1 interrupt + register + 0x128 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT2 + OTG_HS_DIEPINT2 + OTG device endpoint-2 interrupt + register + 0x148 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT3 + OTG_HS_DIEPINT3 + OTG device endpoint-3 interrupt + register + 0x168 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT4 + OTG_HS_DIEPINT4 + OTG device endpoint-4 interrupt + register + 0x188 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT5 + OTG_HS_DIEPINT5 + OTG device endpoint-5 interrupt + register + 0x1A8 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT6 + OTG_HS_DIEPINT6 + OTG device endpoint-6 interrupt + register + 0x1C8 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT7 + OTG_HS_DIEPINT7 + OTG device endpoint-7 interrupt + register + 0x1E8 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPTSIZ0 + OTG_HS_DIEPTSIZ0 + OTG_HS device IN endpoint 0 transfer size + register + 0x110 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + OTG_HS_DIEPDMA1 + OTG_HS_DIEPDMA1 + OTG_HS device endpoint-1 DMA address + register + 0x114 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA2 + OTG_HS_DIEPDMA2 + OTG_HS device endpoint-2 DMA address + register + 0x134 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA3 + OTG_HS_DIEPDMA3 + OTG_HS device endpoint-3 DMA address + register + 0x154 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA4 + OTG_HS_DIEPDMA4 + OTG_HS device endpoint-4 DMA address + register + 0x174 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA5 + OTG_HS_DIEPDMA5 + OTG_HS device endpoint-5 DMA address + register + 0x194 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DTXFSTS0 + OTG_HS_DTXFSTS0 + OTG_HS device IN endpoint transmit FIFO + status register + 0x118 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS1 + OTG_HS_DTXFSTS1 + OTG_HS device IN endpoint transmit FIFO + status register + 0x138 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS2 + OTG_HS_DTXFSTS2 + OTG_HS device IN endpoint transmit FIFO + status register + 0x158 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS3 + OTG_HS_DTXFSTS3 + OTG_HS device IN endpoint transmit FIFO + status register + 0x178 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS4 + OTG_HS_DTXFSTS4 + OTG_HS device IN endpoint transmit FIFO + status register + 0x198 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS5 + OTG_HS_DTXFSTS5 + OTG_HS device IN endpoint transmit FIFO + status register + 0x1B8 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DIEPTSIZ1 + OTG_HS_DIEPTSIZ1 + OTG_HS device endpoint transfer size + register + 0x130 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ2 + OTG_HS_DIEPTSIZ2 + OTG_HS device endpoint transfer size + register + 0x150 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ3 + OTG_HS_DIEPTSIZ3 + OTG_HS device endpoint transfer size + register + 0x170 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ4 + OTG_HS_DIEPTSIZ4 + OTG_HS device endpoint transfer size + register + 0x190 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ5 + OTG_HS_DIEPTSIZ5 + OTG_HS device endpoint transfer size + register + 0x1B0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DOEPCTL0 + OTG_HS_DOEPCTL0 + OTG_HS device control OUT endpoint 0 control + register + 0x300 + 32 + 0x00008000 + + + MPSIZ + Maximum packet size + 0 + 2 + read-only + + + USBAEP + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-only + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-only + + + EPENA + Endpoint enable + 31 + 1 + write-only + + + + + OTG_HS_DOEPCTL1 + OTG_HS_DOEPCTL1 + OTG device endpoint-1 control + register + 0x320 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL2 + OTG_HS_DOEPCTL2 + OTG device endpoint-2 control + register + 0x340 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL3 + OTG_HS_DOEPCTL3 + OTG device endpoint-3 control + register + 0x360 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPINT0 + OTG_HS_DOEPINT0 + OTG_HS device endpoint-0 interrupt + register + 0x308 + 32 + read-write + 0x00000080 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT1 + OTG_HS_DOEPINT1 + OTG_HS device endpoint-1 interrupt + register + 0x328 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT2 + OTG_HS_DOEPINT2 + OTG_HS device endpoint-2 interrupt + register + 0x348 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT3 + OTG_HS_DOEPINT3 + OTG_HS device endpoint-3 interrupt + register + 0x368 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT4 + OTG_HS_DOEPINT4 + OTG_HS device endpoint-4 interrupt + register + 0x388 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT5 + OTG_HS_DOEPINT5 + OTG_HS device endpoint-5 interrupt + register + 0x3A8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT6 + OTG_HS_DOEPINT6 + OTG_HS device endpoint-6 interrupt + register + 0x3C8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT7 + OTG_HS_DOEPINT7 + OTG_HS device endpoint-7 interrupt + register + 0x3E8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPTSIZ0 + OTG_HS_DOEPTSIZ0 + OTG_HS device endpoint-1 transfer size + register + 0x310 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + STUPCNT + SETUP packet count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ1 + OTG_HS_DOEPTSIZ1 + OTG_HS device endpoint-2 transfer size + register + 0x330 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ2 + OTG_HS_DOEPTSIZ2 + OTG_HS device endpoint-3 transfer size + register + 0x350 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ3 + OTG_HS_DOEPTSIZ3 + OTG_HS device endpoint-4 transfer size + register + 0x370 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ4 + OTG_HS_DOEPTSIZ4 + OTG_HS device endpoint-5 transfer size + register + 0x390 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + + + OTG_HS_PWRCLK + USB on the go high speed + USB_OTG_HS + 0x40040E00 + + 0x0 + 0x3F200 + registers + + + 0x3F200 + 0xFFFC1200 + reserved + + + + OTG_HS_PCGCR + OTG_HS_PCGCR + Power and clock gating control + register + 0x0 + 32 + read-write + 0x0 + + + STPPCLK + Stop PHY clock + 0 + 1 + + + GATEHCLK + Gate HCLK + 1 + 1 + + + PHYSUSP + PHY suspended + 4 + 1 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E000 + + 0x0 + 0x1001 + registers + + + 0x1001 + 0xFFFFF3FF + reserved + + + + ICTR + ICTR + Interrupt Controller Type + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + INTLINESNUM + Total number of interrupt lines in + groups + 0 + 4 + + + + + STIR + STIR + Software Triggered Interrupt + Register + 0xF00 + 0x20 + write-only + 0x00000000 + + + INTID + interrupt to be triggered + 0 + 9 + + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER2 + ISER2 + Interrupt Set-Enable Register + 0x108 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER2 + ICER2 + Interrupt Clear-Enable + Register + 0x188 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x200 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x204 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR2 + ISPR2 + Interrupt Set-Pending Register + 0x208 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x280 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x284 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR2 + ICPR2 + Interrupt Clear-Pending + Register + 0x288 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x300 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x304 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR2 + IABR2 + Interrupt Active Bit Register + 0x308 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR15 + IPR15 + Interrupt Priority Register + 0x43C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR16 + IPR16 + Interrupt Priority Register + 0x440 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR17 + IPR17 + Interrupt Priority Register + 0x444 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR18 + IPR18 + Interrupt Priority Register + 0x448 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR19 + IPR19 + Interrupt Priority Register + 0x44C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + From 04a0a78c3d9cd392f2482375df532284e60ce02d Mon Sep 17 00:00:00 2001 From: Unknown Date: Sun, 30 Sep 2018 01:54:02 -0400 Subject: [PATCH 11/72] Get semaphore-controlled bus reception working --- Firmware/communication/interface_can.cpp | 155 ++++++++++++++++------- Firmware/communication/interface_can.hpp | 12 +- ODrive_Workspace.code-workspace | 9 +- 3 files changed, 127 insertions(+), 49 deletions(-) diff --git a/Firmware/communication/interface_can.cpp b/Firmware/communication/interface_can.cpp index 29a03a24..c570b28e 100644 --- a/Firmware/communication/interface_can.cpp +++ b/Firmware/communication/interface_can.cpp @@ -32,6 +32,7 @@ */ #include "interface_can.hpp" +#include #include "fibre/crc.hpp" #include "freertos_vars.h" #include "utils.h" @@ -40,28 +41,37 @@ #include #include +std::unordered_map ctxMap; + // Constructor is called by communication.cpp and the handle is assigned appropriately ODriveCAN::ODriveCAN(CAN_HandleTypeDef *handle, ODriveCAN::Config_t &config) : handle_{handle}, config_{config} { + ctxMap[handle_] = this; } void ODriveCAN::can_server_thread() { - static uint32_t counter = 0; + CAN_message_t heartbeat; + heartbeat.id = 0x700 + config_.node_id; + uint32_t lastHeartbeatTick = osKernelSysTick(); + for (;;) { - CAN_message_t txmsg; - txmsg.id = 0x100; + CAN_message_t rxmsg; + osSemaphoreWait(sem_can, 10); - txmsg.isExt = false; + while (available()) { + read(rxmsg); + write(rxmsg); + } - txmsg.buf[0] = counter >> 24; - txmsg.buf[1] = counter >> 16; - txmsg.buf[2] = counter >> 8; - txmsg.buf[3] = counter; - - counter++; - write(txmsg); - osDelay(10); + // Handle heartbeat message + uint32_t now = osKernelSysTick(); + if(now - lastHeartbeatTick >= 100){ + write(heartbeat); + lastHeartbeatTick = now; + } + + HAL_CAN_ActivateNotification(handle_, CAN_IT_RX_FIFO0_MSG_PENDING); } } @@ -78,19 +88,35 @@ bool ODriveCAN::start_can_server() { if (status != HAL_OK) return false; + CAN_FilterTypeDef filter; + filter.FilterActivation = ENABLE; + filter.FilterBank = 0; + filter.FilterFIFOAssignment = CAN_RX_FIFO0; + filter.FilterIdHigh = 0x0000; + filter.FilterIdLow = 0x0000; + filter.FilterMaskIdHigh = 0x0000; + filter.FilterMaskIdLow = 0x0000; + filter.FilterMode = CAN_FILTERMODE_IDMASK; + filter.FilterScale = CAN_FILTERSCALE_32BIT; + + status = HAL_CAN_ConfigFilter(handle_, &filter); + if (status != HAL_OK) + return false; + status = HAL_CAN_Start(handle_); if (status != HAL_OK) return false; status = HAL_CAN_ActivateNotification(handle_, - CAN_IT_TX_MAILBOX_EMPTY | - CAN_IT_RX_FIFO0_MSG_PENDING | CAN_IT_RX_FIFO1_MSG_PENDING | /* we probably only want this */ - CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO1_FULL | - CAN_IT_RX_FIFO0_OVERRUN | CAN_IT_RX_FIFO1_OVERRUN | - CAN_IT_WAKEUP | CAN_IT_SLEEP_ACK | - CAN_IT_ERROR_WARNING | CAN_IT_ERROR_PASSIVE | - CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE | - CAN_IT_ERROR); + // CAN_IT_TX_MAILBOX_EMPTY | + CAN_IT_RX_FIFO0_MSG_PENDING | CAN_IT_RX_FIFO1_MSG_PENDING /* we probably only want this */ + // CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO1_FULL + // CAN_IT_RX_FIFO0_OVERRUN | CAN_IT_RX_FIFO1_OVERRUN | + // CAN_IT_WAKEUP | CAN_IT_SLEEP_ACK | + // CAN_IT_ERROR_WARNING | CAN_IT_ERROR_PASSIVE | + // CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE | + // | CAN_IT_ERROR + ); if (status != HAL_OK) return false; @@ -101,33 +127,70 @@ bool ODriveCAN::start_can_server() { return true; } + + +// Send a CAN message on the bus +uint32_t ODriveCAN::write(CAN_message_t &txmsg) { + CAN_TxHeaderTypeDef header; + header.StdId = txmsg.id; + header.ExtId = txmsg.id; + header.IDE = txmsg.isExt ? CAN_ID_EXT : CAN_ID_STD; + header.RTR = CAN_RTR_DATA; + header.DLC = txmsg.len; + header.TransmitGlobalTime = FunctionalState::DISABLE; + + uint32_t retTxMailbox; + if (HAL_CAN_GetTxMailboxesFreeLevel(handle_) > 0) + HAL_CAN_AddTxMessage(handle_, &header, txmsg.buf, &retTxMailbox); + + return retTxMailbox; +} + +uint32_t ODriveCAN::available() { + return (HAL_CAN_GetRxFifoFillLevel(handle_, CAN_RX_FIFO0) + HAL_CAN_GetRxFifoFillLevel(handle_, CAN_RX_FIFO1)); +} + +bool ODriveCAN::read(CAN_message_t &rxmsg) { + CAN_RxHeaderTypeDef header; + bool validRead = false; + if (HAL_CAN_GetRxFifoFillLevel(handle_, CAN_RX_FIFO0) > 0) { + HAL_CAN_GetRxMessage(handle_, CAN_RX_FIFO0, &header, rxmsg.buf); + validRead = true; + } else if (HAL_CAN_GetRxFifoFillLevel(handle_, CAN_RX_FIFO1) > 0) { + HAL_CAN_GetRxMessage(handle_, CAN_RX_FIFO1, &header, rxmsg.buf); + validRead = true; + } + + rxmsg.isExt = header.IDE; + rxmsg.id = rxmsg.isExt ? header.ExtId : header.StdId; // If it's an extended message, pass the extended ID + rxmsg.len = header.DLC; + + return validRead; +} + + +// Set one of only a few common baud rates. CAN doesn't do arbitrary baud rates well due to the time-quanta issue. +// 21 TQ allows for easy sampling at exactly 80% (recommended by Vector Informatik GmbH for high reliability systems) +// Conveniently, the CAN peripheral's 42MHz clock lets us easily create 21TQs for all common baud rates void ODriveCAN::set_baud_rate(uint32_t baudRate) { switch (baudRate) { case CAN_BAUD_125K: handle_->Init.Prescaler = 16; // 21 TQ's - handle_->Init.TimeSeg1 = CAN_BS1_16TQ; - handle_->Init.TimeSeg2 = CAN_BS2_4TQ; config_.baud = baudRate; break; case CAN_BAUD_250K: handle_->Init.Prescaler = 8; // 21 TQ's - handle_->Init.TimeSeg1 = CAN_BS1_16TQ; - handle_->Init.TimeSeg2 = CAN_BS2_4TQ; config_.baud = baudRate; break; case CAN_BAUD_500K: handle_->Init.Prescaler = 4; // 21 TQ's - handle_->Init.TimeSeg1 = CAN_BS1_16TQ; - handle_->Init.TimeSeg2 = CAN_BS2_4TQ; config_.baud = baudRate; break; case CAN_BAUD_1000K: handle_->Init.Prescaler = 2; // 21 TQ's - handle_->Init.TimeSeg1 = CAN_BS1_16TQ; - handle_->Init.TimeSeg2 = CAN_BS2_4TQ; config_.baud = baudRate; break; @@ -141,19 +204,23 @@ void ODriveCAN::set_node_id(uint8_t nodeID) { config_.node_id = nodeID; } -// Send a CAN message on the bus -uint32_t ODriveCAN::write(CAN_message_t &txmsg) { - CAN_TxHeaderTypeDef header; - header.StdId = txmsg.id; - header.ExtId = txmsg.id; - header.IDE = txmsg.isExt ? CAN_ID_EXT : CAN_ID_STD; - header.RTR = CAN_RTR_DATA; - header.DLC = txmsg.len; - header.TransmitGlobalTime = FunctionalState::DISABLE; - - uint32_t retTxMailbox; - if(HAL_CAN_GetTxMailboxesFreeLevel(handle_) > 0) - HAL_CAN_AddTxMessage(handle_, &header, txmsg.buf, &retTxMailbox); - - return retTxMailbox; -} \ No newline at end of file +void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) {} +void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) {} +void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) {} +void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) {} +void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) {} +void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) {} +void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) { + HAL_CAN_DeactivateNotification(hcan, CAN_IT_RX_FIFO0_MSG_PENDING); + osSemaphoreRelease(sem_can); +} +void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) { + // osSemaphoreRelease(sem_can); +} +void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) {} +void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) {} +void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) {} +void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) {} +void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) { + HAL_CAN_ResetError(hcan); +} diff --git a/Firmware/communication/interface_can.hpp b/Firmware/communication/interface_can.hpp index a309658b..546680cb 100644 --- a/Firmware/communication/interface_can.hpp +++ b/Firmware/communication/interface_can.hpp @@ -34,15 +34,18 @@ class ODriveCAN { ODriveCAN(CAN_HandleTypeDef *handle, ODriveCAN::Config_t &config); + // Thread Relevant Data + osThreadId thread_id_; + volatile bool thread_id_valid_ = false; bool start_can_server(); void can_server_thread(); + // I/O Functions + uint32_t available(); uint32_t write(CAN_message_t &txmsg); - int read(CAN_message_t &rxmsg); - - osThreadId thread_id_; - volatile bool thread_id_valid_ = false; + bool read(CAN_message_t &rxmsg); + // Communication Protocol Handling auto make_protocol_definitions() { return make_protocol_member_list( make_protocol_object("config", @@ -58,6 +61,7 @@ class ODriveCAN { void set_node_id(uint8_t nodeID); void set_baud_rate(uint32_t baudRate); + }; #endif // __INTERFACE_CAN_HPP diff --git a/ODrive_Workspace.code-workspace b/ODrive_Workspace.code-workspace index 250eb601..fd56d688 100644 --- a/ODrive_Workspace.code-workspace +++ b/ODrive_Workspace.code-workspace @@ -44,7 +44,14 @@ "algorithm": "cpp", "chrono": "cpp", "condition_variable": "cpp", - "future": "cpp" + "future": "cpp", + "cmath": "cpp", + "cstdarg": "cpp", + "unordered_map": "cpp", + "fstream": "cpp", + "numeric": "cpp", + "optional": "cpp", + "sstream": "cpp" } } } From c48251f3f598a0cd39f40740fc7974d82719d201 Mon Sep 17 00:00:00 2001 From: Unknown Date: Sun, 30 Sep 2018 02:04:37 -0400 Subject: [PATCH 12/72] Report axis errors and current state in heartbeat --- Firmware/communication/interface_can.cpp | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Firmware/communication/interface_can.cpp b/Firmware/communication/interface_can.cpp index c570b28e..80fe84d9 100644 --- a/Firmware/communication/interface_can.cpp +++ b/Firmware/communication/interface_can.cpp @@ -41,6 +41,8 @@ #include #include +#include + std::unordered_map ctxMap; // Constructor is called by communication.cpp and the handle is assigned appropriately @@ -65,6 +67,10 @@ void ODriveCAN::can_server_thread() { } // Handle heartbeat message + heartbeat.buf[0] = axes[0]->error_; + heartbeat.buf[1] = axes[0]->current_state_; + heartbeat.buf[2] = axes[1]->error_; + heartbeat.buf[3] = axes[2]->current_state_; uint32_t now = osKernelSysTick(); if(now - lastHeartbeatTick >= 100){ write(heartbeat); From 0589b12238d591324e3ad1627435a06b46cd21fb Mon Sep 17 00:00:00 2001 From: Unknown Date: Sun, 30 Sep 2018 02:06:19 -0400 Subject: [PATCH 13/72] We don't have an axis 2... --- Firmware/communication/interface_can.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Firmware/communication/interface_can.cpp b/Firmware/communication/interface_can.cpp index 80fe84d9..f53db443 100644 --- a/Firmware/communication/interface_can.cpp +++ b/Firmware/communication/interface_can.cpp @@ -70,7 +70,7 @@ void ODriveCAN::can_server_thread() { heartbeat.buf[0] = axes[0]->error_; heartbeat.buf[1] = axes[0]->current_state_; heartbeat.buf[2] = axes[1]->error_; - heartbeat.buf[3] = axes[2]->current_state_; + heartbeat.buf[3] = axes[1]->current_state_; uint32_t now = osKernelSysTick(); if(now - lastHeartbeatTick >= 100){ write(heartbeat); From 2431fd98c67c9890a6d9b9f687e4cedd9cdc79b8 Mon Sep 17 00:00:00 2001 From: Unknown Date: Thu, 4 Oct 2018 18:50:45 -0400 Subject: [PATCH 14/72] Start with CAN_SIMPLE protocol --- Firmware/Tupfile.lua | 1 + Firmware/communication/can_simple.cpp | 26 ++++++++++++++++++++++++ Firmware/communication/can_simple.hpp | 22 ++++++++++++++++++++ Firmware/communication/interface_can.cpp | 17 +++++++++++----- Firmware/communication/interface_can.hpp | 25 ++++++++++++++--------- 5 files changed, 76 insertions(+), 15 deletions(-) create mode 100644 Firmware/communication/can_simple.cpp create mode 100644 Firmware/communication/can_simple.hpp diff --git a/Firmware/Tupfile.lua b/Firmware/Tupfile.lua index 0b3d43e3..9678a31a 100644 --- a/Firmware/Tupfile.lua +++ b/Firmware/Tupfile.lua @@ -157,6 +157,7 @@ build{ 'MotorControl/sensorless_estimator.cpp', 'MotorControl/trapTraj.cpp', 'MotorControl/main.cpp', + 'communication/can_simple.cpp', 'communication/communication.cpp', 'communication/ascii_protocol.cpp', 'communication/interface_uart.cpp', diff --git a/Firmware/communication/can_simple.cpp b/Firmware/communication/can_simple.cpp new file mode 100644 index 00000000..dc4c8cba --- /dev/null +++ b/Firmware/communication/can_simple.cpp @@ -0,0 +1,26 @@ +#include "can_simple.hpp" +#include "odrive_main.h" + +void CANSimple::handle_can_message(CAN_message_t& msg) { + // This functional way of handling the messages is neat and is much cleaner from + // a data security point of view, but it will require some tweaking to fix the syntax. + // + // auto func = callback_map.find(msg.id); + // if(func != callback_map.end()){ + // func->second(msg); + // } + + // Frame + // nodeID | CMD + // 4 bits | 7 bits + auto nodeID = (msg.id >> 7 & 0x15); + for(int i = 0; i < AXIS_COUNT; i++){ + if(axes[i]->config_.nodeID) + } + switch (msg.id & 0x7F) { + case 0x010: move_to_pos_callback(); break; + } +} + +void move_to_pos_callback(Axis& axis, uint32_t pos){ +} \ No newline at end of file diff --git a/Firmware/communication/can_simple.hpp b/Firmware/communication/can_simple.hpp new file mode 100644 index 00000000..f2ed42ed --- /dev/null +++ b/Firmware/communication/can_simple.hpp @@ -0,0 +1,22 @@ +#ifndef __CAN_SIMPLE_HPP_ +#define __CAN_SIMPLE_HPP_ + +#include "interface_can.hpp" + +class CANSimple { + public: + static void handle_can_message(CAN_message_t& msg); + + private: + // Controller + static void move_to_pos_callback(Axis& axis, uint32_t pos); + + // This functional way of handling the messages is neat and is much cleaner from + // a data security point of view, but it will require some tweaking + // + // const std::map> callback_map = { + // {0x000, std::bind(&CANSimple::heartbeat_callback, this, _1)} + // }; +}; + +#endif \ No newline at end of file diff --git a/Firmware/communication/interface_can.cpp b/Firmware/communication/interface_can.cpp index f53db443..21edf0ca 100644 --- a/Firmware/communication/interface_can.cpp +++ b/Firmware/communication/interface_can.cpp @@ -32,7 +32,7 @@ */ #include "interface_can.hpp" -#include + #include "fibre/crc.hpp" #include "freertos_vars.h" #include "utils.h" @@ -41,15 +41,20 @@ #include #include +// Specific CAN Protocols +#include "can_simple.hpp" + #include -std::unordered_map ctxMap; +// Safer context handling via maps instead of arrays +// #include +// std::unordered_map ctxMap; // Constructor is called by communication.cpp and the handle is assigned appropriately ODriveCAN::ODriveCAN(CAN_HandleTypeDef *handle, ODriveCAN::Config_t &config) : handle_{handle}, config_{config} { - ctxMap[handle_] = this; + // ctxMap[handle_] = this; } void ODriveCAN::can_server_thread() { @@ -60,10 +65,12 @@ void ODriveCAN::can_server_thread() { for (;;) { CAN_message_t rxmsg; - osSemaphoreWait(sem_can, 10); + osSemaphoreWait(sem_can, 10); // Poll every 10ms regardless of sempahore status while (available()) { read(rxmsg); - write(rxmsg); + switch(config_.protocol) { + case CAN_PROTOCOL_SIMPLE: CANSimple::handle_can_message(rxmsg); break; + } } // Handle heartbeat message diff --git a/Firmware/communication/interface_can.hpp b/Firmware/communication/interface_can.hpp index 546680cb..356c6cde 100644 --- a/Firmware/communication/interface_can.hpp +++ b/Firmware/communication/interface_can.hpp @@ -16,20 +16,25 @@ typedef struct { } CAN_message_t; // Anonymous enum for defining the most common CAN baud rates - - enum { - CAN_BAUD_125K = 125000, - CAN_BAUD_250K = 250000, - CAN_BAUD_500K = 500000, - CAN_BAUD_1000K = 1000000, - CAN_BAUD_1M = 1000000 - }; + +enum { + CAN_BAUD_125K = 125000, + CAN_BAUD_250K = 250000, + CAN_BAUD_500K = 500000, + CAN_BAUD_1000K = 1000000, + CAN_BAUD_1M = 1000000 +}; + +enum CAN_Protocol_t { + CAN_PROTOCOL_SIMPLE +}; class ODriveCAN { public: struct Config_t { uint8_t node_id = 0; uint32_t baud = CAN_BAUD_250K; + CAN_Protocol_t protocol = CAN_PROTOCOL_SIMPLE; }; ODriveCAN(CAN_HandleTypeDef *handle, ODriveCAN::Config_t &config); @@ -39,7 +44,7 @@ class ODriveCAN { volatile bool thread_id_valid_ = false; bool start_can_server(); void can_server_thread(); - + // I/O Functions uint32_t available(); uint32_t write(CAN_message_t &txmsg); @@ -51,6 +56,7 @@ class ODriveCAN { make_protocol_object("config", make_protocol_ro_property("node_id", &config_.node_id), make_protocol_ro_property("baud_rate", &config_.baud)), + make_protocol_property("can_protocol", &config_.protocol), make_protocol_function("set_node_id", *this, &ODriveCAN::set_node_id, "nodeID"), make_protocol_function("set_baud_rate", *this, &ODriveCAN::set_baud_rate, "baudRate")); } @@ -61,7 +67,6 @@ class ODriveCAN { void set_node_id(uint8_t nodeID); void set_baud_rate(uint32_t baudRate); - }; #endif // __INTERFACE_CAN_HPP From 538236ab21fc4f6b13ff4402ae40d560bccad458 Mon Sep 17 00:00:00 2001 From: Unknown Date: Thu, 4 Oct 2018 18:50:56 -0400 Subject: [PATCH 15/72] Each axis needs a can nodeID --- Firmware/MotorControl/axis.hpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Firmware/MotorControl/axis.hpp b/Firmware/MotorControl/axis.hpp index 6063ee3a..ec8fa8ef 100644 --- a/Firmware/MotorControl/axis.hpp +++ b/Firmware/MotorControl/axis.hpp @@ -54,6 +54,8 @@ public: float spin_up_current = 10.0f; // [A] float spin_up_acceleration = 400.0f; // [rad/s^2] float spin_up_target_vel = 400.0f; // [rad/s] + + uint8_t can_node_id = 0; // If both axes are 0, only the first one will get commands. }; enum thread_signals { From c88d3f7a012d849f2aac00f2e5137dbb7b8a94eb Mon Sep 17 00:00:00 2001 From: Unknown Date: Thu, 4 Oct 2018 20:39:00 -0400 Subject: [PATCH 16/72] We're using gcc --- Firmware/.vscode/c_cpp_properties.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Firmware/.vscode/c_cpp_properties.json b/Firmware/.vscode/c_cpp_properties.json index 570c0f29..5176fa6c 100644 --- a/Firmware/.vscode/c_cpp_properties.json +++ b/Firmware/.vscode/c_cpp_properties.json @@ -31,7 +31,7 @@ "__packed=\"__attribute__((__packed__))\"", "__GNUC__" ], - "intelliSenseMode": "clang-x64", + "intelliSenseMode": "gcc-x64", "browse": { "path": [ "${workspaceRoot}", From 4fa09d6bbca4a591c54a45036279f2450604cd08 Mon Sep 17 00:00:00 2001 From: Unknown Date: Fri, 5 Oct 2018 22:20:04 -0400 Subject: [PATCH 17/72] Get CAN_SIMPLE to compile --- Firmware/MotorControl/axis.cpp | 43 +++++----- Firmware/MotorControl/axis.hpp | 10 ++- Firmware/communication/can_simple.cpp | 103 +++++++++++++++++++++-- Firmware/communication/can_simple.hpp | 8 +- Firmware/communication/interface_can.cpp | 77 +++++------------ Firmware/communication/interface_can.hpp | 2 + 6 files changed, 156 insertions(+), 87 deletions(-) diff --git a/Firmware/MotorControl/axis.cpp b/Firmware/MotorControl/axis.cpp index 4ff660fd..3aaf5ed4 100644 --- a/Firmware/MotorControl/axis.cpp +++ b/Firmware/MotorControl/axis.cpp @@ -3,8 +3,9 @@ #include #include "gpio.h" -#include "utils.h" #include "odrive_main.h" +#include "utils.h" +#include "communication/interface_can.hpp" Axis::Axis(const AxisHardwareConfig_t& hw_config, Config_t& config, @@ -19,8 +20,7 @@ Axis::Axis(const AxisHardwareConfig_t& hw_config, sensorless_estimator_(sensorless_estimator), controller_(controller), motor_(motor), - trap_(trap) -{ + trap_(trap) { encoder_.axis_ = this; sensorless_estimator_.axis_ = this; controller_.axis_ = this; @@ -46,7 +46,7 @@ static void run_state_machine_loop_wrapper(void* ctx) { // @brief Starts run_state_machine_loop in a new thread void Axis::start_thread() { - osThreadDef(thread_def, run_state_machine_loop_wrapper, hw_config_.thread_priority, 0, 4*512); + osThreadDef(thread_def, run_state_machine_loop_wrapper, hw_config_.thread_priority, 0, 4 * 512); thread_id_ = osThreadCreate(osThread(thread_def), this); thread_id_valid_ = true; } @@ -85,7 +85,7 @@ void Axis::set_step_dir_enabled(bool enable) { // Subscribe to rising edges of the step GPIO GPIO_subscribe(hw_config_.step_port, hw_config_.step_pin, GPIO_PULLDOWN, - step_cb_wrapper, this); + step_cb_wrapper, this); enable_step_dir_ = true; } else { @@ -136,7 +136,9 @@ bool Axis::do_updates() { // Sub-components should use set_error which will propegate to this error_ encoder_.update(); sensorless_estimator_.update(); - return check_for_errors(); + bool ret = check_for_errors(); + odCAN->send_heartbeat(this); + return ret; } float Axis::get_temp() { @@ -148,7 +150,7 @@ float Axis::get_temp() { bool Axis::run_sensorless_spin_up() { // Early Spin-up: spiral up current float x = 0.0f; - run_control_loop([&](){ + run_control_loop([&]() { float phase = wrap_pm_pi(config_.ramp_up_distance * x); float I_mag = config_.spin_up_current * x; x += current_meas_period / config_.ramp_up_time; @@ -158,11 +160,11 @@ bool Axis::run_sensorless_spin_up() { }); if (error_ != ERROR_NONE) return false; - + // Late Spin-up: accelerate float vel = config_.ramp_up_distance / config_.ramp_up_time; float phase = wrap_pm_pi(config_.ramp_up_distance); - run_control_loop([&](){ + run_control_loop([&]() { vel += config_.spin_up_acceleration * current_meas_period; phase = wrap_pm_pi(phase + vel * current_meas_period); float I_mag = config_.spin_up_current; @@ -181,7 +183,7 @@ bool Axis::run_sensorless_spin_up() { // Note run_sensorless_control_loop and run_closed_loop_control_loop are very similar and differ only in where we get the estimate from. bool Axis::run_sensorless_control_loop() { set_step_dir_enabled(config_.enable_step_dir); - run_control_loop([this](){ + run_control_loop([this]() { if (controller_.config_.control_mode >= Controller::CTRL_MODE_POSITION_CONTROL) return error_ |= ERROR_POS_CTRL_DURING_SENSORLESS, false; @@ -190,7 +192,7 @@ bool Axis::run_sensorless_control_loop() { if (!controller_.update(sensorless_estimator_.pll_pos_, sensorless_estimator_.vel_estimate_, ¤t_setpoint)) return error_ |= ERROR_CONTROLLER_FAILED, false; if (!motor_.update(current_setpoint, sensorless_estimator_.phase_)) - return false; // set_error should update axis.error_ + return false; // set_error should update axis.error_ return true; }); set_step_dir_enabled(false); @@ -199,13 +201,13 @@ bool Axis::run_sensorless_control_loop() { bool Axis::run_closed_loop_control_loop() { set_step_dir_enabled(config_.enable_step_dir); - run_control_loop([this](){ + run_control_loop([this]() { // Note that all estimators are updated in the loop prefix in run_control_loop float current_setpoint; if (!controller_.update(encoder_.pos_estimate_, encoder_.vel_estimate_, ¤t_setpoint)) - return error_ |= ERROR_CONTROLLER_FAILED, false; //TODO: Make controller.set_error + return error_ |= ERROR_CONTROLLER_FAILED, false; //TODO: Make controller.set_error if (!motor_.update(current_setpoint, encoder_.phase_)) - return false; // set_error should update axis.error_ + return false; // set_error should update axis.error_ return true; }); set_step_dir_enabled(false); @@ -216,7 +218,7 @@ bool Axis::run_idle_loop() { // run_control_loop ignores missed modulation timing updates // if and only if we're in AXIS_STATE_IDLE safety_critical_disarm_motor_pwm(motor_); - run_control_loop([this](){ + run_control_loop([this]() { return true; }); return check_for_errors(); @@ -224,7 +226,6 @@ bool Axis::run_idle_loop() { // Infinite loop that does calibration and enters main control loop as appropriate void Axis::run_state_machine_loop() { - // Allocate the map for anti-cogging algorithm and initialize all values to 0.0f // TODO: Move this somewhere else // TODO: respect changes of CPR @@ -238,7 +239,7 @@ void Axis::run_state_machine_loop() { // arm! motor_.arm(); - + for (;;) { // Load the task chain if a specific request is pending if (requested_state_ != AXIS_STATE_UNDEFINED) { @@ -265,7 +266,7 @@ void Axis::run_state_machine_loop() { task_chain_[pos++] = requested_state_; task_chain_[pos++] = AXIS_STATE_IDLE; } - task_chain_[pos++] = AXIS_STATE_UNDEFINED; // TODO: bounds checking + task_chain_[pos++] = AXIS_STATE_UNDEFINED; // TODO: bounds checking requested_state_ = AXIS_STATE_UNDEFINED; // Auto-clear any invalid state error error_ &= ~ERROR_INVALID_STATE; @@ -296,7 +297,7 @@ void Axis::run_state_machine_loop() { break; case AXIS_STATE_SENSORLESS_CONTROL: - status = run_sensorless_spin_up(); // TODO: restart if desired + status = run_sensorless_spin_up(); // TODO: restart if desired if (status) status = run_sensorless_control_loop(); break; @@ -307,12 +308,12 @@ void Axis::run_state_machine_loop() { case AXIS_STATE_IDLE: run_idle_loop(); - status = motor_.arm(); // done with idling - try to arm the motor + status = motor_.arm(); // done with idling - try to arm the motor break; default: error_ |= ERROR_INVALID_STATE; - status = false; // this will set the state to idle + status = false; // this will set the state to idle break; } diff --git a/Firmware/MotorControl/axis.hpp b/Firmware/MotorControl/axis.hpp index ec8fa8ef..3b46e347 100644 --- a/Firmware/MotorControl/axis.hpp +++ b/Firmware/MotorControl/axis.hpp @@ -20,6 +20,7 @@ public: ERROR_ENCODER_FAILED = 0x100, ERROR_CONTROLLER_FAILED = 0x200, ERROR_POS_CTRL_DURING_SENSORLESS = 0x400, + ERROR_ESTOP_REQUESTED = 0x800 }; // Warning: Do not reorder these enum values. @@ -55,7 +56,7 @@ public: float spin_up_acceleration = 400.0f; // [rad/s^2] float spin_up_target_vel = 400.0f; // [rad/s] - uint8_t can_node_id = 0; // If both axes are 0, only the first one will get commands. + uint8_t can_node_id = 0; // Both axes will have the same id to start }; enum thread_signals { @@ -113,10 +114,9 @@ public: // Update all estimators // Note: updates run even if checks fail bool updates_ok = do_updates(); - if (!checks_ok || !updates_ok) break; - + // Run main loop function, defer quitting for after wait // TODO: change arming logic to arm after waiting bool main_continue = update_handler(); @@ -165,6 +165,7 @@ public: State_t task_chain_[10] = { AXIS_STATE_UNDEFINED }; State_t& current_state_ = task_chain_[0]; uint32_t loop_counter_ = 0; + uint32_t last_heartbeat_ = 0; // Communication protocol definitions auto make_protocol_definitions() { @@ -186,7 +187,8 @@ public: make_protocol_property("ramp_up_distance", &config_.ramp_up_distance), make_protocol_property("spin_up_current", &config_.spin_up_current), make_protocol_property("spin_up_acceleration", &config_.spin_up_acceleration), - make_protocol_property("spin_up_target_vel", &config_.spin_up_target_vel) + make_protocol_property("spin_up_target_vel", &config_.spin_up_target_vel), + make_protocol_property("can_node_id", &config_.can_node_id) ), make_protocol_function("get_temp", *this, &Axis::get_temp), make_protocol_object("motor", motor_.make_protocol_definitions()), diff --git a/Firmware/communication/can_simple.cpp b/Firmware/communication/can_simple.cpp index dc4c8cba..92acf2a8 100644 --- a/Firmware/communication/can_simple.cpp +++ b/Firmware/communication/can_simple.cpp @@ -1,3 +1,4 @@ + #include "can_simple.hpp" #include "odrive_main.h" @@ -14,13 +15,105 @@ void CANSimple::handle_can_message(CAN_message_t& msg) { // nodeID | CMD // 4 bits | 7 bits auto nodeID = (msg.id >> 7 & 0x15); - for(int i = 0; i < AXIS_COUNT; i++){ - if(axes[i]->config_.nodeID) + Axis* axis = nullptr; + + for (uint8_t i = 0; i < AXIS_COUNT; i++) { + if (axes[i]->config_.can_node_id == nodeID) { + axis = axes[i]; + } } - switch (msg.id & 0x7F) { - case 0x010: move_to_pos_callback(); break; + if (axis != nullptr) { + switch (msg.id & 0x7F) { + case 0x010: + move_to_pos_callback(axis, msg); + break; + case 0x011: + set_pos_setpoint_callback(axis, msg); + break; + case 0x012: + set_vel_setpoint_callback(axis, msg); + break; + case 0x013: + set_current_setpoint_callback(axis, msg); + break; + } } } -void move_to_pos_callback(Axis& axis, uint32_t pos){ +void CANSimple::estop_callback(){ + for(Axis* axis : axes){ + axis->error_ |= Axis::ERROR_ESTOP_REQUESTED; + } +} + +void CANSimple::move_to_pos_callback(Axis* axis, CAN_message_t& msg) { + float pos = msg.buf[0]; + pos += msg.buf[1] << 8; + pos += msg.buf[2] << 16; + pos += msg.buf[3] << 24; + + axis->controller_.move_to_pos(pos); +} + +void CANSimple::set_pos_setpoint_callback(Axis* axis, CAN_message_t& msg) { + float pos = msg.buf[0]; + pos += msg.buf[1] << 8; + pos += msg.buf[2] << 16; + pos += msg.buf[3] << 24; + + float vel = msg.buf[4]; + vel += msg.buf[5] << 8; + vel *= 0.1f; // Factor of 10 + + float current = msg.buf[6]; + current += (msg.buf[7] << 8); + current *= 0.01f; // Factor of 100 + + axis->controller_.set_pos_setpoint(pos, vel, current); +} + +void CANSimple::set_vel_setpoint_callback(Axis* axis, CAN_message_t& msg) { + float vel = msg.buf[0]; + vel += msg.buf[1] << 8; + vel += msg.buf[2] << 16; + vel += msg.buf[3] << 24; + vel *= 0.01f; + + float current = msg.buf[4]; + current += msg.buf[5] << 8; + current += msg.buf[6] << 16; + current += msg.buf[7] << 24; + current *= 0.01f; + + axis->controller_.set_vel_setpoint(vel, current); +} + +void CANSimple::set_current_setpoint_callback(Axis* axis, CAN_message_t& msg) { + float current = msg.buf[0]; + current += msg.buf[1] << 8; + current += msg.buf[2] << 16; + current += msg.buf[3] << 24; + current *= 0.01f; + + axis->controller_.set_current_setpoint(current); +} + +void CANSimple::send_heartbeat(Axis* axis){ + CAN_message_t txmsg; + txmsg.id = axis->config_.can_node_id << 7; + txmsg.id += 0x1; + txmsg.isExt = false; + txmsg.len = 8; + + // Axis errors in 1st 32-bit value + txmsg.buf[0] = axis->error_; + txmsg.buf[1] = axis->error_ >> 8; + txmsg.buf[2] = axis->error_ >> 16; + txmsg.buf[3] = axis->error_ >> 24; + + // Current state of axis in 2nd 32-bit value + txmsg.buf[4] = axis->current_state_; + txmsg.buf[5] = axis->current_state_ >> 8; + txmsg.buf[6] = axis->current_state_ >> 16; + txmsg.buf[7] = axis->current_state_ >> 24; } \ No newline at end of file diff --git a/Firmware/communication/can_simple.hpp b/Firmware/communication/can_simple.hpp index f2ed42ed..7d87f2da 100644 --- a/Firmware/communication/can_simple.hpp +++ b/Firmware/communication/can_simple.hpp @@ -6,10 +6,16 @@ class CANSimple { public: static void handle_can_message(CAN_message_t& msg); + static void send_heartbeat(Axis* axis); private: + static void estop_callback(); + // Controller - static void move_to_pos_callback(Axis& axis, uint32_t pos); + static void move_to_pos_callback(Axis* axis, CAN_message_t& msg); + static void set_pos_setpoint_callback(Axis* axis, CAN_message_t& msg); + static void set_vel_setpoint_callback(Axis* axis, CAN_message_t& msg); + static void set_current_setpoint_callback(Axis* axis, CAN_message_t& msg); // This functional way of handling the messages is neat and is much cleaner from // a data security point of view, but it will require some tweaking diff --git a/Firmware/communication/interface_can.cpp b/Firmware/communication/interface_can.cpp index 21edf0ca..716821d2 100644 --- a/Firmware/communication/interface_can.cpp +++ b/Firmware/communication/interface_can.cpp @@ -1,36 +1,3 @@ -/* -* -* Zero-config node ID negotiation -* ------------------------------- -* -* A heartbeat message is a message with a 8 byte unique serial number as payload. -* A regular message is any message that is not a heartbeat message. -* -* All nodes MUST obey these four rules: -* -* a) At a given point in time, a node MUST consider a node ID taken (by others) -* if any of the following is true: -* - the node received a (not self-emitted) heartbeat message with that node ID -* within the last second -* - the node attempted and failed at sending a heartbeat message with that -* node ID within the last second (failed in the sense of not ACK'd) -* -* b) At a given point in time, a node MUST NOT consider a node ID self-assigned -* if, within the last second, it did not succeed in sending a heartbeat -* message with that node ID. -* -* c) At a given point in time, a node MUST NOT send any heartbeat message with -* a node ID that is taken. -* -* d) At a given point in time, a node MUST NOT send any regular message with -* a node ID that is not self-assigned. -* -* Hardware allocation -* ------------------- -* RX FIFO0: -* - filter bank 0: heartbeat messages -*/ - #include "interface_can.hpp" #include "fibre/crc.hpp" @@ -58,32 +25,18 @@ ODriveCAN::ODriveCAN(CAN_HandleTypeDef *handle, ODriveCAN::Config_t &config) } void ODriveCAN::can_server_thread() { - CAN_message_t heartbeat; - heartbeat.id = 0x700 + config_.node_id; - uint32_t lastHeartbeatTick = osKernelSysTick(); - for (;;) { CAN_message_t rxmsg; - osSemaphoreWait(sem_can, 10); // Poll every 10ms regardless of sempahore status + osSemaphoreWait(sem_can, 10); // Poll every 10ms regardless of sempahore status while (available()) { read(rxmsg); - switch(config_.protocol) { - case CAN_PROTOCOL_SIMPLE: CANSimple::handle_can_message(rxmsg); break; + switch (config_.protocol) { + case CAN_PROTOCOL_SIMPLE: + CANSimple::handle_can_message(rxmsg); + break; } } - - // Handle heartbeat message - heartbeat.buf[0] = axes[0]->error_; - heartbeat.buf[1] = axes[0]->current_state_; - heartbeat.buf[2] = axes[1]->error_; - heartbeat.buf[3] = axes[1]->current_state_; - uint32_t now = osKernelSysTick(); - if(now - lastHeartbeatTick >= 100){ - write(heartbeat); - lastHeartbeatTick = now; - } - HAL_CAN_ActivateNotification(handle_, CAN_IT_RX_FIFO0_MSG_PENDING); } } @@ -140,8 +93,6 @@ bool ODriveCAN::start_can_server() { return true; } - - // Send a CAN message on the bus uint32_t ODriveCAN::write(CAN_message_t &txmsg) { CAN_TxHeaderTypeDef header; @@ -181,8 +132,7 @@ bool ODriveCAN::read(CAN_message_t &rxmsg) { return validRead; } - -// Set one of only a few common baud rates. CAN doesn't do arbitrary baud rates well due to the time-quanta issue. +// Set one of only a few common baud rates. CAN doesn't do arbitrary baud rates well due to the time-quanta issue. // 21 TQ allows for easy sampling at exactly 80% (recommended by Vector Informatik GmbH for high reliability systems) // Conveniently, the CAN peripheral's 42MHz clock lets us easily create 21TQs for all common baud rates void ODriveCAN::set_baud_rate(uint32_t baudRate) { @@ -217,6 +167,21 @@ void ODriveCAN::set_node_id(uint8_t nodeID) { config_.node_id = nodeID; } +// This function is called by each axis. +// It provides an abstraction from the specific CAN protocol in use +void ODriveCAN::send_heartbeat(Axis *axis) { + // Handle heartbeat message + uint32_t now = osKernelSysTick(); + if (now - axis->last_heartbeat_ >= 100) { + switch (config_.protocol) { + case CAN_PROTOCOL_SIMPLE: + CANSimple::send_heartbeat(axis); + break; + } + axis->last_heartbeat_ = now; + } +} + void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) {} void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) {} void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) {} diff --git a/Firmware/communication/interface_can.hpp b/Firmware/communication/interface_can.hpp index 356c6cde..db44d3d0 100644 --- a/Firmware/communication/interface_can.hpp +++ b/Firmware/communication/interface_can.hpp @@ -4,6 +4,7 @@ #include #include #include "fibre/protocol.hpp" +#include "odrive_main.h" #define CAN_CLK_HZ (42000000) #define CAN_CLK_MHZ (42) @@ -44,6 +45,7 @@ class ODriveCAN { volatile bool thread_id_valid_ = false; bool start_can_server(); void can_server_thread(); + void send_heartbeat(Axis* axis); // I/O Functions uint32_t available(); From 8052762684f64d37cbf9c60697c671683329f167 Mon Sep 17 00:00:00 2001 From: Unknown Date: Sat, 6 Oct 2018 12:54:53 -0400 Subject: [PATCH 18/72] Remove nodeID from CAN interface, since it's moving to each axis --- Firmware/communication/interface_can.cpp | 5 ----- Firmware/communication/interface_can.hpp | 5 +---- 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/Firmware/communication/interface_can.cpp b/Firmware/communication/interface_can.cpp index 716821d2..f7b7e078 100644 --- a/Firmware/communication/interface_can.cpp +++ b/Firmware/communication/interface_can.cpp @@ -162,11 +162,6 @@ void ODriveCAN::set_baud_rate(uint32_t baudRate) { } } -void ODriveCAN::set_node_id(uint8_t nodeID) { - // Allow for future nodeID validation by making this a set function - config_.node_id = nodeID; -} - // This function is called by each axis. // It provides an abstraction from the specific CAN protocol in use void ODriveCAN::send_heartbeat(Axis *axis) { diff --git a/Firmware/communication/interface_can.hpp b/Firmware/communication/interface_can.hpp index db44d3d0..1a8d36c0 100644 --- a/Firmware/communication/interface_can.hpp +++ b/Firmware/communication/interface_can.hpp @@ -33,8 +33,7 @@ enum CAN_Protocol_t { class ODriveCAN { public: struct Config_t { - uint8_t node_id = 0; - uint32_t baud = CAN_BAUD_250K; + uint32_t baud = CAN_BAUD_1M; CAN_Protocol_t protocol = CAN_PROTOCOL_SIMPLE; }; @@ -56,10 +55,8 @@ class ODriveCAN { auto make_protocol_definitions() { return make_protocol_member_list( make_protocol_object("config", - make_protocol_ro_property("node_id", &config_.node_id), make_protocol_ro_property("baud_rate", &config_.baud)), make_protocol_property("can_protocol", &config_.protocol), - make_protocol_function("set_node_id", *this, &ODriveCAN::set_node_id, "nodeID"), make_protocol_function("set_baud_rate", *this, &ODriveCAN::set_baud_rate, "baudRate")); } From 165838ccef2ac5ad6846b9e8ac6fabc830bd2b1b Mon Sep 17 00:00:00 2001 From: Unknown Date: Sat, 6 Oct 2018 21:13:36 -0400 Subject: [PATCH 19/72] Change message IDs so they don't collide with test messages --- Firmware/communication/can_simple.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Firmware/communication/can_simple.cpp b/Firmware/communication/can_simple.cpp index 92acf2a8..7808465b 100644 --- a/Firmware/communication/can_simple.cpp +++ b/Firmware/communication/can_simple.cpp @@ -24,16 +24,16 @@ void CANSimple::handle_can_message(CAN_message_t& msg) { } if (axis != nullptr) { switch (msg.id & 0x7F) { - case 0x010: + case 0x020: move_to_pos_callback(axis, msg); break; - case 0x011: + case 0x021: set_pos_setpoint_callback(axis, msg); break; - case 0x012: + case 0x022: set_vel_setpoint_callback(axis, msg); break; - case 0x013: + case 0x023: set_current_setpoint_callback(axis, msg); break; } From a4ebed742cbe695af865160c18cec0fd86150ba9 Mon Sep 17 00:00:00 2001 From: Unknown Date: Sat, 6 Oct 2018 21:14:26 -0400 Subject: [PATCH 20/72] Actually send the heartbeat message... --- Firmware/communication/can_simple.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/Firmware/communication/can_simple.cpp b/Firmware/communication/can_simple.cpp index 7808465b..14ca8af0 100644 --- a/Firmware/communication/can_simple.cpp +++ b/Firmware/communication/can_simple.cpp @@ -116,4 +116,5 @@ void CANSimple::send_heartbeat(Axis* axis){ txmsg.buf[5] = axis->current_state_ >> 8; txmsg.buf[6] = axis->current_state_ >> 16; txmsg.buf[7] = axis->current_state_ >> 24; + odCAN->write(txmsg); } \ No newline at end of file From a59e29b591f04e157f3ffad87f676455ebf38d8a Mon Sep 17 00:00:00 2001 From: Unknown Date: Sat, 6 Oct 2018 21:15:02 -0400 Subject: [PATCH 21/72] Remove unnecessary includes --- Firmware/communication/can_simple.cpp | 1 - Firmware/communication/interface_can.cpp | 2 -- 2 files changed, 3 deletions(-) diff --git a/Firmware/communication/can_simple.cpp b/Firmware/communication/can_simple.cpp index 14ca8af0..38032469 100644 --- a/Firmware/communication/can_simple.cpp +++ b/Firmware/communication/can_simple.cpp @@ -1,6 +1,5 @@ #include "can_simple.hpp" -#include "odrive_main.h" void CANSimple::handle_can_message(CAN_message_t& msg) { // This functional way of handling the messages is neat and is much cleaner from diff --git a/Firmware/communication/interface_can.cpp b/Firmware/communication/interface_can.cpp index f7b7e078..2fd624f1 100644 --- a/Firmware/communication/interface_can.cpp +++ b/Firmware/communication/interface_can.cpp @@ -11,8 +11,6 @@ // Specific CAN Protocols #include "can_simple.hpp" -#include - // Safer context handling via maps instead of arrays // #include // std::unordered_map ctxMap; From 605b7d2fbf32ec166e1221fb4291baf0146a11f4 Mon Sep 17 00:00:00 2001 From: Unknown Date: Sun, 7 Oct 2018 00:05:53 -0400 Subject: [PATCH 22/72] Handle CAN bus initialization failures and baud rate reinitialization --- Firmware/communication/can_simple.cpp | 2 +- Firmware/communication/interface_can.cpp | 92 +++++++++++++----------- Firmware/communication/interface_can.hpp | 1 + 3 files changed, 53 insertions(+), 42 deletions(-) diff --git a/Firmware/communication/can_simple.cpp b/Firmware/communication/can_simple.cpp index 38032469..0a33f704 100644 --- a/Firmware/communication/can_simple.cpp +++ b/Firmware/communication/can_simple.cpp @@ -100,7 +100,7 @@ void CANSimple::set_current_setpoint_callback(Axis* axis, CAN_message_t& msg) { void CANSimple::send_heartbeat(Axis* axis){ CAN_message_t txmsg; txmsg.id = axis->config_.can_node_id << 7; - txmsg.id += 0x1; + txmsg.id += 0x001; // heartbeat ID txmsg.isExt = false; txmsg.len = 8; diff --git a/Firmware/communication/interface_can.cpp b/Firmware/communication/interface_can.cpp index 2fd624f1..ca504fea 100644 --- a/Firmware/communication/interface_can.cpp +++ b/Firmware/communication/interface_can.cpp @@ -24,18 +24,28 @@ ODriveCAN::ODriveCAN(CAN_HandleTypeDef *handle, ODriveCAN::Config_t &config) void ODriveCAN::can_server_thread() { for (;;) { - CAN_message_t rxmsg; + uint32_t status = HAL_CAN_GetError(handle_); + if (status == HAL_CAN_ERROR_NONE) { + CAN_message_t rxmsg; - osSemaphoreWait(sem_can, 10); // Poll every 10ms regardless of sempahore status - while (available()) { - read(rxmsg); - switch (config_.protocol) { - case CAN_PROTOCOL_SIMPLE: - CANSimple::handle_can_message(rxmsg); - break; + osSemaphoreWait(sem_can, 10); // Poll every 10ms regardless of sempahore status + while (available()) { + read(rxmsg); + switch (config_.protocol) { + case CAN_PROTOCOL_SIMPLE: + CANSimple::handle_can_message(rxmsg); + break; + } + } + HAL_CAN_ActivateNotification(handle_, CAN_IT_RX_FIFO0_MSG_PENDING); + } else { + if (status == HAL_CAN_ERROR_TIMEOUT) { + HAL_CAN_ResetError(handle_); + status = HAL_CAN_Start(handle_); + if (status == HAL_OK) + status = HAL_CAN_ActivateNotification(handle_, CAN_IT_RX_FIFO0_MSG_PENDING); } } - HAL_CAN_ActivateNotification(handle_, CAN_IT_RX_FIFO0_MSG_PENDING); } } @@ -48,9 +58,8 @@ bool ODriveCAN::start_can_server() { HAL_StatusTypeDef status; set_baud_rate(config_.baud); + status = HAL_CAN_Init(handle_); - if (status != HAL_OK) - return false; CAN_FilterTypeDef filter; filter.FilterActivation = ENABLE; @@ -64,48 +73,37 @@ bool ODriveCAN::start_can_server() { filter.FilterScale = CAN_FILTERSCALE_32BIT; status = HAL_CAN_ConfigFilter(handle_, &filter); - if (status != HAL_OK) - return false; status = HAL_CAN_Start(handle_); - if (status != HAL_OK) - return false; - - status = HAL_CAN_ActivateNotification(handle_, - // CAN_IT_TX_MAILBOX_EMPTY | - CAN_IT_RX_FIFO0_MSG_PENDING | CAN_IT_RX_FIFO1_MSG_PENDING /* we probably only want this */ - // CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO1_FULL - // CAN_IT_RX_FIFO0_OVERRUN | CAN_IT_RX_FIFO1_OVERRUN | - // CAN_IT_WAKEUP | CAN_IT_SLEEP_ACK | - // CAN_IT_ERROR_WARNING | CAN_IT_ERROR_PASSIVE | - // CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE | - // | CAN_IT_ERROR - ); - if (status != HAL_OK) - return false; + if (status == HAL_OK) + status = HAL_CAN_ActivateNotification(handle_, CAN_IT_RX_FIFO0_MSG_PENDING); osThreadDef(can_server_thread_def, can_server_thread_wrapper, osPriorityNormal, 0, 512); thread_id_ = osThreadCreate(osThread(can_server_thread_def), this); thread_id_valid_ = true; - return true; + return status; } // Send a CAN message on the bus uint32_t ODriveCAN::write(CAN_message_t &txmsg) { - CAN_TxHeaderTypeDef header; - header.StdId = txmsg.id; - header.ExtId = txmsg.id; - header.IDE = txmsg.isExt ? CAN_ID_EXT : CAN_ID_STD; - header.RTR = CAN_RTR_DATA; - header.DLC = txmsg.len; - header.TransmitGlobalTime = FunctionalState::DISABLE; + if (HAL_CAN_GetError(handle_) == HAL_CAN_ERROR_NONE) { + CAN_TxHeaderTypeDef header; + header.StdId = txmsg.id; + header.ExtId = txmsg.id; + header.IDE = txmsg.isExt ? CAN_ID_EXT : CAN_ID_STD; + header.RTR = CAN_RTR_DATA; + header.DLC = txmsg.len; + header.TransmitGlobalTime = FunctionalState::DISABLE; - uint32_t retTxMailbox; - if (HAL_CAN_GetTxMailboxesFreeLevel(handle_) > 0) - HAL_CAN_AddTxMessage(handle_, &header, txmsg.buf, &retTxMailbox); + uint32_t retTxMailbox; + if (HAL_CAN_GetTxMailboxesFreeLevel(handle_) > 0) + HAL_CAN_AddTxMessage(handle_, &header, txmsg.buf, &retTxMailbox); - return retTxMailbox; + return retTxMailbox; + } else { + return -1; + } } uint32_t ODriveCAN::available() { @@ -138,21 +136,25 @@ void ODriveCAN::set_baud_rate(uint32_t baudRate) { case CAN_BAUD_125K: handle_->Init.Prescaler = 16; // 21 TQ's config_.baud = baudRate; + reinit_can(); break; case CAN_BAUD_250K: handle_->Init.Prescaler = 8; // 21 TQ's config_.baud = baudRate; + reinit_can(); break; case CAN_BAUD_500K: handle_->Init.Prescaler = 4; // 21 TQ's config_.baud = baudRate; + reinit_can(); break; case CAN_BAUD_1000K: handle_->Init.Prescaler = 2; // 21 TQ's config_.baud = baudRate; + reinit_can(); break; default: @@ -160,7 +162,15 @@ void ODriveCAN::set_baud_rate(uint32_t baudRate) { } } -// This function is called by each axis. +void ODriveCAN::reinit_can() { + HAL_CAN_Stop(handle_); + HAL_CAN_Init(handle_); + auto status = HAL_CAN_Start(handle_); + if (status == HAL_OK) + status = HAL_CAN_ActivateNotification(handle_, CAN_IT_RX_FIFO0_MSG_PENDING); +} + +// This function is called by each axis. // It provides an abstraction from the specific CAN protocol in use void ODriveCAN::send_heartbeat(Axis *axis) { // Handle heartbeat message diff --git a/Firmware/communication/interface_can.hpp b/Firmware/communication/interface_can.hpp index 1a8d36c0..00ec5bfa 100644 --- a/Firmware/communication/interface_can.hpp +++ b/Firmware/communication/interface_can.hpp @@ -45,6 +45,7 @@ class ODriveCAN { bool start_can_server(); void can_server_thread(); void send_heartbeat(Axis* axis); + void reinit_can(); // I/O Functions uint32_t available(); From 1e47eb90ef9cd7440cda7c8fdef85b5b9c90e76f Mon Sep 17 00:00:00 2001 From: Unknown Date: Sun, 7 Oct 2018 01:29:17 -0400 Subject: [PATCH 23/72] Create initial list of CAN commands --- Firmware/communication/can_simple.hpp | 38 +++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/Firmware/communication/can_simple.hpp b/Firmware/communication/can_simple.hpp index 7d87f2da..21ad509e 100644 --- a/Firmware/communication/can_simple.hpp +++ b/Firmware/communication/can_simple.hpp @@ -5,6 +5,44 @@ class CANSimple { public: + enum { + MSG_NMT_CTRL = 0x000, // CANOpen NMT Message + MSG_SYNC_CTRL = 0x080, // CANOpen SYNC message + MSG_HEARTBEAT_CMD = 0x700, // CANOpen NMT Heartbeat + MSG_EMERGENCY = 0x080, // CANOpen Emergency Message + MSG_GET_MOTOR_ERROR = 0x001, // Errors + MSG_GET_ENCODER_ERROR, + MSG_GET_CONTROLLER_ERROR, + MSG_GET_SENSORLESS_ERROR, + MSG_GET_VBUS_VOLTAGE, // ODrive-level properties + MSG_GET_SERIAL_NUMBER, + MSG_GET_HW_VERSION, + MSG_GET_FW_VERSION, + MSG_REBOOT_ODRIVE, + MSG_SAVE_CONFIG, + MSG_ERASE_CONFIG, + MSG_SET_AXIS_NODE_ID, // Axis properties + MSG_SET_AXIS_REQUESTED_STATE, + MSG_SET_STARTUP_CONFIG, + MSG_SET_MOTOR_PRECALIBRATED, // Motor properties + MSG_GET_MOTOR_CURRENT_LIM, + MSG_SET_MOTOR_CURRENT_LIM, + MSG_SET_MOTOR_POLE_PAIRS, + MSG_GET_ENCODER_CPR, // Encoder Properties + MSG_SET_ENCODER_CPR, + MSG_GET_ENCODER_INDEX_FOUND, + MSG_GET_ENCODER_POS_ESTIMATE, + MSG_GET_ENCODER_VEL_ESTIMATE, + MSG_SET_ENCODER_USE_INDEX, + MSG_SET_ENCODER_PRECALIBRATED, + MSG_MOVE_TO_POS, // Controller properties + MSG_SET_POS_SETPOINT, + MSG_SET_VEL_SETPOINT, + MSG_SET_CUR_SETPOINT, + MSG_SET_VEL_LIMIT, + MSG_START_ANTICOGGING + }; + static void handle_can_message(CAN_message_t& msg); static void send_heartbeat(Axis* axis); From 3197220a1a5e7dfe063d34a5617048f710dc1741 Mon Sep 17 00:00:00 2001 From: Unknown Date: Sun, 7 Oct 2018 01:29:43 -0400 Subject: [PATCH 24/72] More graceful message handling --- Firmware/communication/can_simple.cpp | 27 +++++++++++++++++++-------- Firmware/communication/can_simple.hpp | 4 ++++ 2 files changed, 23 insertions(+), 8 deletions(-) diff --git a/Firmware/communication/can_simple.cpp b/Firmware/communication/can_simple.cpp index 0a33f704..c7b42ca0 100644 --- a/Firmware/communication/can_simple.cpp +++ b/Firmware/communication/can_simple.cpp @@ -1,6 +1,9 @@ #include "can_simple.hpp" +static const uint8_t NUM_NODE_ID_BITS = 6; +static constexpr uint8_t NUM_CMD_ID_BITS = 11 - NUM_NODE_ID_BITS; + void CANSimple::handle_can_message(CAN_message_t& msg) { // This functional way of handling the messages is neat and is much cleaner from // a data security point of view, but it will require some tweaking to fix the syntax. @@ -13,7 +16,7 @@ void CANSimple::handle_can_message(CAN_message_t& msg) { // Frame // nodeID | CMD // 4 bits | 7 bits - auto nodeID = (msg.id >> 7 & 0x15); + auto nodeID = get_node_id(msg.id); Axis* axis = nullptr; for (uint8_t i = 0; i < AXIS_COUNT; i++) { @@ -22,23 +25,31 @@ void CANSimple::handle_can_message(CAN_message_t& msg) { } } if (axis != nullptr) { - switch (msg.id & 0x7F) { - case 0x020: + switch (get_cmd_id(msg.id)) { + case MSG_MOVE_TO_POS: move_to_pos_callback(axis, msg); break; - case 0x021: + case MSG_SET_POS_SETPOINT: set_pos_setpoint_callback(axis, msg); break; - case 0x022: + case MSG_SET_VEL_SETPOINT: set_vel_setpoint_callback(axis, msg); break; - case 0x023: + case MSG_SET_CUR_SETPOINT: set_current_setpoint_callback(axis, msg); break; } } } +uint8_t CANSimple::get_node_id(uint32_t msgID){ + return ((msgID >> NUM_NODE_ID_BITS) & 0x03F); // Upper 6 bits +} + +uint8_t CANSimple::get_cmd_id(uint32_t msgID){ + return (msgID & 0x01F); // Bottom 5 bits +} + void CANSimple::estop_callback(){ for(Axis* axis : axes){ axis->error_ |= Axis::ERROR_ESTOP_REQUESTED; @@ -99,8 +110,8 @@ void CANSimple::set_current_setpoint_callback(Axis* axis, CAN_message_t& msg) { void CANSimple::send_heartbeat(Axis* axis){ CAN_message_t txmsg; - txmsg.id = axis->config_.can_node_id << 7; - txmsg.id += 0x001; // heartbeat ID + txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; + txmsg.id += MSG_HEARTBEAT_CMD; // heartbeat ID txmsg.isExt = false; txmsg.len = 8; diff --git a/Firmware/communication/can_simple.hpp b/Firmware/communication/can_simple.hpp index 21ad509e..a20c1703 100644 --- a/Firmware/communication/can_simple.hpp +++ b/Firmware/communication/can_simple.hpp @@ -55,6 +55,10 @@ class CANSimple { static void set_vel_setpoint_callback(Axis* axis, CAN_message_t& msg); static void set_current_setpoint_callback(Axis* axis, CAN_message_t& msg); + // Utility functions + static uint8_t get_node_id(uint32_t msgID); + static uint8_t get_cmd_id(uint32_t msgID); + // This functional way of handling the messages is neat and is much cleaner from // a data security point of view, but it will require some tweaking // From 887a785e94e54f7c4e61144ea9c46fc67f7aea6e Mon Sep 17 00:00:00 2001 From: Unknown Date: Sun, 7 Oct 2018 01:53:01 -0400 Subject: [PATCH 25/72] Make 250kbps the default CAN baud rate --- Firmware/communication/interface_can.cpp | 3 ++- Firmware/communication/interface_can.hpp | 16 ++++++++-------- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/Firmware/communication/interface_can.cpp b/Firmware/communication/interface_can.cpp index ca504fea..2940cdf1 100644 --- a/Firmware/communication/interface_can.cpp +++ b/Firmware/communication/interface_can.cpp @@ -158,7 +158,8 @@ void ODriveCAN::set_baud_rate(uint32_t baudRate) { break; default: - break; // baudRate is invalid, so do nothing + // baudRate is invalid, so don't accept it. + break; } } diff --git a/Firmware/communication/interface_can.hpp b/Firmware/communication/interface_can.hpp index 00ec5bfa..850c240b 100644 --- a/Firmware/communication/interface_can.hpp +++ b/Firmware/communication/interface_can.hpp @@ -19,11 +19,11 @@ typedef struct { // Anonymous enum for defining the most common CAN baud rates enum { - CAN_BAUD_125K = 125000, - CAN_BAUD_250K = 250000, - CAN_BAUD_500K = 500000, - CAN_BAUD_1000K = 1000000, - CAN_BAUD_1M = 1000000 + CAN_BAUD_125K = 125000, + CAN_BAUD_250K = 250000, + CAN_BAUD_500K = 500000, + CAN_BAUD_1000K = 1000000, + CAN_BAUD_1M = 1000000 }; enum CAN_Protocol_t { @@ -33,7 +33,7 @@ enum CAN_Protocol_t { class ODriveCAN { public: struct Config_t { - uint32_t baud = CAN_BAUD_1M; + uint32_t baud = CAN_BAUD_250K; CAN_Protocol_t protocol = CAN_PROTOCOL_SIMPLE; }; @@ -44,7 +44,7 @@ class ODriveCAN { volatile bool thread_id_valid_ = false; bool start_can_server(); void can_server_thread(); - void send_heartbeat(Axis* axis); + void send_heartbeat(Axis *axis); void reinit_can(); // I/O Functions @@ -57,7 +57,7 @@ class ODriveCAN { return make_protocol_member_list( make_protocol_object("config", make_protocol_ro_property("baud_rate", &config_.baud)), - make_protocol_property("can_protocol", &config_.protocol), + make_protocol_property("can_protocol", &config_.protocol), make_protocol_function("set_baud_rate", *this, &ODriveCAN::set_baud_rate, "baudRate")); } From 8373771457c1393d834ba553a05d0ee252210328 Mon Sep 17 00:00:00 2001 From: Unknown Date: Sun, 7 Oct 2018 01:54:41 -0400 Subject: [PATCH 26/72] Remove nodeID function --- Firmware/communication/interface_can.hpp | 1 - 1 file changed, 1 deletion(-) diff --git a/Firmware/communication/interface_can.hpp b/Firmware/communication/interface_can.hpp index 850c240b..4105592b 100644 --- a/Firmware/communication/interface_can.hpp +++ b/Firmware/communication/interface_can.hpp @@ -65,7 +65,6 @@ class ODriveCAN { CAN_HandleTypeDef *handle_ = nullptr; ODriveCAN::Config_t &config_; - void set_node_id(uint8_t nodeID); void set_baud_rate(uint32_t baudRate); }; From 2f76d3c284742bf3a56cb1bffeb02242eb4d773b Mon Sep 17 00:00:00 2001 From: Unknown Date: Sun, 7 Oct 2018 13:29:18 -0400 Subject: [PATCH 27/72] Implement can_simple --- Firmware/communication/can_simple.cpp | 235 ++++++++++++++++++-------- Firmware/communication/can_simple.hpp | 55 +++--- 2 files changed, 192 insertions(+), 98 deletions(-) diff --git a/Firmware/communication/can_simple.cpp b/Firmware/communication/can_simple.cpp index c7b42ca0..8b2567c7 100644 --- a/Firmware/communication/can_simple.cpp +++ b/Firmware/communication/can_simple.cpp @@ -15,8 +15,10 @@ void CANSimple::handle_can_message(CAN_message_t& msg) { // Frame // nodeID | CMD - // 4 bits | 7 bits - auto nodeID = get_node_id(msg.id); + // 6 bits | 5 bits + uint32_t nodeID = get_node_id(msg.id); + uint32_t cmd = get_cmd_id(msg.id); + Axis* axis = nullptr; for (uint8_t i = 0; i < AXIS_COUNT; i++) { @@ -24,97 +26,177 @@ void CANSimple::handle_can_message(CAN_message_t& msg) { axis = axes[i]; } } - if (axis != nullptr) { - switch (get_cmd_id(msg.id)) { - case MSG_MOVE_TO_POS: - move_to_pos_callback(axis, msg); - break; - case MSG_SET_POS_SETPOINT: - set_pos_setpoint_callback(axis, msg); - break; - case MSG_SET_VEL_SETPOINT: - set_vel_setpoint_callback(axis, msg); - break; - case MSG_SET_CUR_SETPOINT: - set_current_setpoint_callback(axis, msg); - break; - } + switch (cmd) { + case MSG_CO_NMT_CTRL: + nmt_callback(axis, msg); + break; + case MSG_CO_SYNC_CTRL: + sync_callback(axis, msg); + break; + case MSG_CO_HEARTBEAT_CMD: + break; + case MSG_GET_ENCODER_ERROR: + get_encoder_error_callback(axis, msg); + break; + case MSG_GET_SENSORLESS_ERROR: + get_sensorless_error_callback(axis, msg); + break; + case MSG_SET_AXIS_NODE_ID: + set_axis_nodeid_callback(axis, msg); + break; + case MSG_SET_AXIS_REQUESTED_STATE: + set_axis_requested_state_callback(axis, msg); + break; + case MSG_SET_AXIS_STARTUP_CONFIG: + set_axis_startup_config_callback(axis, msg); + break; + case MSG_GET_ENCODER_ESTIMATES: + get_encoder_estimates_callback(axis, msg); + break; + case MSG_MOVE_TO_POS: + move_to_pos_callback(axis, msg); + break; + case MSG_SET_POS_SETPOINT: + set_pos_setpoint_callback(axis, msg); + break; + case MSG_SET_VEL_SETPOINT: + set_vel_setpoint_callback(axis, msg); + break; + case MSG_SET_CUR_SETPOINT: + set_current_setpoint_callback(axis, msg); + break; + case MSG_SET_VEL_LIMIT: + set_vel_limit_callback(axis, msg); + break; + case MSG_START_ANTICOGGING: + start_anticogging_callback(axis, msg); + break; + default: + break; } } -uint8_t CANSimple::get_node_id(uint32_t msgID){ - return ((msgID >> NUM_NODE_ID_BITS) & 0x03F); // Upper 6 bits +void CANSimple::nmt_callback(Axis* axis, CAN_message_t& msg) { + // Not implemented } -uint8_t CANSimple::get_cmd_id(uint32_t msgID){ - return (msgID & 0x01F); // Bottom 5 bits +void CANSimple::sync_callback(Axis* axis, CAN_message_t& msg) { + // Not implemented } -void CANSimple::estop_callback(){ - for(Axis* axis : axes){ - axis->error_ |= Axis::ERROR_ESTOP_REQUESTED; - } +void CANSimple::estop_callback(Axis* axis, CAN_message_t& msg) { + axis->error_ |= Axis::ERROR_ESTOP_REQUESTED; +} + +void CANSimple::get_motor_error_callback(Axis* axis, CAN_message_t& msg) { + CAN_message_t txmsg; + txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; + txmsg.id += MSG_GET_MOTOR_ERROR; // heartbeat ID + txmsg.isExt = false; + txmsg.len = 8; + + txmsg.buf[0] = axis->motor_.error_; + txmsg.buf[1] = axis->motor_.error_ >> 8; + txmsg.buf[2] = axis->motor_.error_ >> 16; + txmsg.buf[3] = axis->motor_.error_ >> 24; + + odCAN->write(txmsg); +} + +void CANSimple::get_encoder_error_callback(Axis* axis, CAN_message_t& msg) { + CAN_message_t txmsg; + txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; + txmsg.id += MSG_GET_ENCODER_ERROR; // heartbeat ID + txmsg.isExt = false; + txmsg.len = 8; + + txmsg.buf[0] = axis->encoder_.error_; + txmsg.buf[1] = axis->encoder_.error_ >> 8; + txmsg.buf[2] = axis->encoder_.error_ >> 16; + txmsg.buf[3] = axis->encoder_.error_ >> 24; + + odCAN->write(txmsg); +} + +void CANSimple::get_sensorless_error_callback(Axis* axis, CAN_message_t& msg) { + CAN_message_t txmsg; + txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; + txmsg.id += MSG_GET_SENSORLESS_ERROR; // heartbeat ID + txmsg.isExt = false; + txmsg.len = 8; + + txmsg.buf[0] = axis->sensorless_estimator_.error_; + txmsg.buf[1] = axis->sensorless_estimator_.error_ >> 8; + txmsg.buf[2] = axis->sensorless_estimator_.error_ >> 16; + txmsg.buf[3] = axis->sensorless_estimator_.error_ >> 24; + + odCAN->write(txmsg); +} + +void CANSimple::set_axis_nodeid_callback(Axis* axis, CAN_message_t& msg) { + axis->config_.can_node_id = msg.buf[0]; +} + +void CANSimple::set_axis_requested_state_callback(Axis* axis, CAN_message_t& msg) { + axis->requested_state_ = static_cast(get_16bit_val(msg, 0)); +} +void CANSimple::set_axis_startup_config_callback(Axis* axis, CAN_message_t& msg) { + // Not Implemented +} + +void CANSimple::get_encoder_estimates_callback(Axis* axis, CAN_message_t& msg) { + CAN_message_t txmsg; + txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; + txmsg.id += MSG_GET_ENCODER_ESTIMATES; // heartbeat ID + txmsg.isExt = false; + txmsg.len = 8; + + uint32_t floatBytes = *(reinterpret_cast(&(axis->encoder_.pos_estimate_))); + txmsg.buf[0] = floatBytes; + txmsg.buf[1] = floatBytes >> 8; + txmsg.buf[2] = floatBytes >> 16; + txmsg.buf[3] = floatBytes >> 24; + + floatBytes = *(reinterpret_cast(&(axis->encoder_.vel_estimate_))); + txmsg.buf[4] = floatBytes; + txmsg.buf[5] = floatBytes >> 8; + txmsg.buf[6] = floatBytes >> 16; + txmsg.buf[7] = floatBytes >> 24; + + odCAN->write(txmsg); } void CANSimple::move_to_pos_callback(Axis* axis, CAN_message_t& msg) { - float pos = msg.buf[0]; - pos += msg.buf[1] << 8; - pos += msg.buf[2] << 16; - pos += msg.buf[3] << 24; - - axis->controller_.move_to_pos(pos); + axis->controller_.move_to_pos(get_32bit_val(msg, 0)); } void CANSimple::set_pos_setpoint_callback(Axis* axis, CAN_message_t& msg) { - float pos = msg.buf[0]; - pos += msg.buf[1] << 8; - pos += msg.buf[2] << 16; - pos += msg.buf[3] << 24; - - float vel = msg.buf[4]; - vel += msg.buf[5] << 8; - vel *= 0.1f; // Factor of 10 - - float current = msg.buf[6]; - current += (msg.buf[7] << 8); - current *= 0.01f; // Factor of 100 - - axis->controller_.set_pos_setpoint(pos, vel, current); + axis->controller_.set_pos_setpoint(get_32bit_val(msg, 0), get_16bit_val(msg, 4) * 0.1f, get_16bit_val(msg, 6) * 0.01f); } void CANSimple::set_vel_setpoint_callback(Axis* axis, CAN_message_t& msg) { - float vel = msg.buf[0]; - vel += msg.buf[1] << 8; - vel += msg.buf[2] << 16; - vel += msg.buf[3] << 24; - vel *= 0.01f; - - float current = msg.buf[4]; - current += msg.buf[5] << 8; - current += msg.buf[6] << 16; - current += msg.buf[7] << 24; - current *= 0.01f; - - axis->controller_.set_vel_setpoint(vel, current); + axis->controller_.set_vel_setpoint(get_32bit_val(msg, 0) * 0.01f, get_32bit_val(msg, 4) * 0.01f); } void CANSimple::set_current_setpoint_callback(Axis* axis, CAN_message_t& msg) { - float current = msg.buf[0]; - current += msg.buf[1] << 8; - current += msg.buf[2] << 16; - current += msg.buf[3] << 24; - current *= 0.01f; - - axis->controller_.set_current_setpoint(current); + axis->controller_.set_current_setpoint(get_32bit_val(msg, 0) * 0.01f); } -void CANSimple::send_heartbeat(Axis* axis){ +void CANSimple::set_vel_limit_callback(Axis* axis, CAN_message_t& msg) { + axis->controller_.config_.vel_limit = get_32bit_val(msg, 0); +} + +void CANSimple::start_anticogging_callback(Axis* axis, CAN_message_t& msg) { + axis->controller_.start_anticogging_calibration(); +} + +void CANSimple::send_heartbeat(Axis* axis) { CAN_message_t txmsg; txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; - txmsg.id += MSG_HEARTBEAT_CMD; // heartbeat ID + txmsg.id += MSG_CO_HEARTBEAT_CMD; // heartbeat ID txmsg.isExt = false; txmsg.len = 8; - + // Axis errors in 1st 32-bit value txmsg.buf[0] = axis->error_; txmsg.buf[1] = axis->error_ >> 8; @@ -127,4 +209,21 @@ void CANSimple::send_heartbeat(Axis* axis){ txmsg.buf[6] = axis->current_state_ >> 16; txmsg.buf[7] = axis->current_state_ >> 24; odCAN->write(txmsg); +} + +uint8_t CANSimple::get_node_id(uint32_t msgID) { + return ((msgID >> NUM_CMD_ID_BITS) & 0x03F); // Upper 6 bits +} + +uint8_t CANSimple::get_cmd_id(uint32_t msgID) { + return (msgID & 0x01F); // Bottom 5 bits +} + +uint16_t CANSimple::get_16bit_val(CAN_message_t& msg, uint8_t start_byte) { + return msg.buf[start_byte] + (msg.buf[start_byte + 1] << 8); +} + +uint32_t CANSimple::get_32bit_val(CAN_message_t& msg, uint8_t start_byte) { + return get_16bit_val(msg, 0) + (get_16bit_val(msg, 2) << 16); + // return msg.buf[start_byte] + (msg.buf[start_byte+1] << 8) + (msg.buf[start_byte+1] << 16) + (msg.buf[start_byte+1] << 24); } \ No newline at end of file diff --git a/Firmware/communication/can_simple.hpp b/Firmware/communication/can_simple.hpp index a20c1703..f1b63998 100644 --- a/Firmware/communication/can_simple.hpp +++ b/Firmware/communication/can_simple.hpp @@ -6,36 +6,18 @@ class CANSimple { public: enum { - MSG_NMT_CTRL = 0x000, // CANOpen NMT Message - MSG_SYNC_CTRL = 0x080, // CANOpen SYNC message - MSG_HEARTBEAT_CMD = 0x700, // CANOpen NMT Heartbeat - MSG_EMERGENCY = 0x080, // CANOpen Emergency Message - MSG_GET_MOTOR_ERROR = 0x001, // Errors + MSG_CO_NMT_CTRL = 0x000, // CANOpen NMT Message REC + MSG_CO_SYNC_CTRL = 0x080, // CANOpen SYNC message REC + MSG_CO_HEARTBEAT_CMD = 0x700, // CANOpen NMT Heartbeat SEND + MSG_CO_EMERGENCY = 0x080, // CANOpen Emergency Message SEND + MSG_GET_MOTOR_ERROR = 0x001, // Errors MSG_GET_ENCODER_ERROR, - MSG_GET_CONTROLLER_ERROR, MSG_GET_SENSORLESS_ERROR, - MSG_GET_VBUS_VOLTAGE, // ODrive-level properties - MSG_GET_SERIAL_NUMBER, - MSG_GET_HW_VERSION, - MSG_GET_FW_VERSION, - MSG_REBOOT_ODRIVE, - MSG_SAVE_CONFIG, - MSG_ERASE_CONFIG, - MSG_SET_AXIS_NODE_ID, // Axis properties + MSG_SET_AXIS_NODE_ID, MSG_SET_AXIS_REQUESTED_STATE, - MSG_SET_STARTUP_CONFIG, - MSG_SET_MOTOR_PRECALIBRATED, // Motor properties - MSG_GET_MOTOR_CURRENT_LIM, - MSG_SET_MOTOR_CURRENT_LIM, - MSG_SET_MOTOR_POLE_PAIRS, - MSG_GET_ENCODER_CPR, // Encoder Properties - MSG_SET_ENCODER_CPR, - MSG_GET_ENCODER_INDEX_FOUND, - MSG_GET_ENCODER_POS_ESTIMATE, - MSG_GET_ENCODER_VEL_ESTIMATE, - MSG_SET_ENCODER_USE_INDEX, - MSG_SET_ENCODER_PRECALIBRATED, - MSG_MOVE_TO_POS, // Controller properties + MSG_SET_AXIS_STARTUP_CONFIG, + MSG_GET_ENCODER_ESTIMATES, + MSG_MOVE_TO_POS, MSG_SET_POS_SETPOINT, MSG_SET_VEL_SETPOINT, MSG_SET_CUR_SETPOINT, @@ -47,18 +29,31 @@ class CANSimple { static void send_heartbeat(Axis* axis); private: - static void estop_callback(); - - // Controller + static void nmt_callback(Axis* axis, CAN_message_t& msg); + static void sync_callback(Axis* axis, CAN_message_t& msg); + static void estop_callback(Axis* axis, CAN_message_t& msg); + static void get_motor_error_callback(Axis* axis, CAN_message_t& msg); + static void get_encoder_error_callback(Axis* axis, CAN_message_t& msg); + static void get_controller_error_callback(Axis* axis, CAN_message_t& msg); + static void get_sensorless_error_callback(Axis* axis, CAN_message_t& msg); + static void set_axis_nodeid_callback(Axis* axis, CAN_message_t& msg); + static void set_axis_requested_state_callback(Axis* axis, CAN_message_t& msg); + static void set_axis_startup_config_callback(Axis* axis, CAN_message_t& msg); + static void get_encoder_estimates_callback(Axis* axis, CAN_message_t& msg); static void move_to_pos_callback(Axis* axis, CAN_message_t& msg); static void set_pos_setpoint_callback(Axis* axis, CAN_message_t& msg); static void set_vel_setpoint_callback(Axis* axis, CAN_message_t& msg); static void set_current_setpoint_callback(Axis* axis, CAN_message_t& msg); + static void set_vel_limit_callback(Axis* axis, CAN_message_t& msg); + static void start_anticogging_callback(Axis* axis, CAN_message_t& msg); // Utility functions static uint8_t get_node_id(uint32_t msgID); static uint8_t get_cmd_id(uint32_t msgID); + static uint16_t get_16bit_val(CAN_message_t& msg, uint8_t start_byte); + static uint32_t get_32bit_val(CAN_message_t& msg, uint8_t start_byte); + // This functional way of handling the messages is neat and is much cleaner from // a data security point of view, but it will require some tweaking // From 867fa5452a70b12d5278225ee6f0f6b3cfe5f7b8 Mon Sep 17 00:00:00 2001 From: Unknown Date: Sun, 7 Oct 2018 17:35:08 -0400 Subject: [PATCH 28/72] Add documentation for the CAN Protocol --- Firmware/communication/can_simple.cpp | 72 ++++++++++++++---- Firmware/communication/can_simple.hpp | 23 ++++-- docs/can-protocol.md | 105 ++++++++++++++++++++++++++ 3 files changed, 178 insertions(+), 22 deletions(-) create mode 100644 docs/can-protocol.md diff --git a/Firmware/communication/can_simple.cpp b/Firmware/communication/can_simple.cpp index 8b2567c7..df19d269 100644 --- a/Firmware/communication/can_simple.cpp +++ b/Firmware/communication/can_simple.cpp @@ -28,13 +28,18 @@ void CANSimple::handle_can_message(CAN_message_t& msg) { } switch (cmd) { case MSG_CO_NMT_CTRL: - nmt_callback(axis, msg); - break; - case MSG_CO_SYNC_CTRL: - sync_callback(axis, msg); break; case MSG_CO_HEARTBEAT_CMD: break; + case MSG_ODRIVE_HEARTBEAT: + // We don't currently do anything to respond to ODrive heartbeat messages + break; + case MSG_ODRIVE_ESTOP: + estop_callback(axis, msg); + break; + case MSG_GET_MOTOR_ERROR: + get_motor_error_callback(axis, msg); + break; case MSG_GET_ENCODER_ERROR: get_encoder_error_callback(axis, msg); break; @@ -53,6 +58,9 @@ void CANSimple::handle_can_message(CAN_message_t& msg) { case MSG_GET_ENCODER_ESTIMATES: get_encoder_estimates_callback(axis, msg); break; + case MSG_GET_ENCODER_COUNT: + get_encoder_count_callback(axis, msg); + break; case MSG_MOVE_TO_POS: move_to_pos_callback(axis, msg); break; @@ -80,10 +88,6 @@ void CANSimple::nmt_callback(Axis* axis, CAN_message_t& msg) { // Not implemented } -void CANSimple::sync_callback(Axis* axis, CAN_message_t& msg) { - // Not implemented -} - void CANSimple::estop_callback(Axis* axis, CAN_message_t& msg) { axis->error_ |= Axis::ERROR_ESTOP_REQUESTED; } @@ -134,7 +138,7 @@ void CANSimple::get_sensorless_error_callback(Axis* axis, CAN_message_t& msg) { } void CANSimple::set_axis_nodeid_callback(Axis* axis, CAN_message_t& msg) { - axis->config_.can_node_id = msg.buf[0]; + axis->config_.can_node_id = msg.buf[0] & 0x3F; // Node ID bitmask } void CANSimple::set_axis_requested_state_callback(Axis* axis, CAN_message_t& msg) { @@ -166,6 +170,26 @@ void CANSimple::get_encoder_estimates_callback(Axis* axis, CAN_message_t& msg) { odCAN->write(txmsg); } +void CANSimple::get_encoder_count_callback(Axis* axis, CAN_message_t& msg){ + CAN_message_t txmsg; + txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; + txmsg.id += MSG_GET_ENCODER_COUNT; + txmsg.isExt = false; + txmsg.len = 8; + + txmsg.buf[0] = axis->encoder_.shadow_count_; + txmsg.buf[1] = axis->encoder_.shadow_count_ >> 8; + txmsg.buf[2] = axis->encoder_.shadow_count_ >> 16; + txmsg.buf[3] = axis->encoder_.shadow_count_ >> 24; + + txmsg.buf[4] = axis->encoder_.count_in_cpr_; + txmsg.buf[5] = axis->encoder_.count_in_cpr_ >> 8; + txmsg.buf[6] = axis->encoder_.count_in_cpr_ >> 16; + txmsg.buf[7] = axis->encoder_.count_in_cpr_ >> 24; + + odCAN->write(txmsg); +} + void CANSimple::move_to_pos_callback(Axis* axis, CAN_message_t& msg) { axis->controller_.move_to_pos(get_32bit_val(msg, 0)); } @@ -183,17 +207,31 @@ void CANSimple::set_current_setpoint_callback(Axis* axis, CAN_message_t& msg) { } void CANSimple::set_vel_limit_callback(Axis* axis, CAN_message_t& msg) { - axis->controller_.config_.vel_limit = get_32bit_val(msg, 0); + axis->controller_.config_.vel_limit = get_float(msg, 0); } void CANSimple::start_anticogging_callback(Axis* axis, CAN_message_t& msg) { axis->controller_.start_anticogging_calibration(); } +void CANSimple::set_traj_vel_limit_callback(Axis* axis, CAN_message_t& msg) { + axis->trap_.config_.vel_limit = get_float(msg, 0); +} + +void CANSimple::set_traj_accel_limits_callback(Axis* axis, CAN_message_t& msg) { + axis->trap_.config_.accel_limit = get_float(msg, 0); + axis->trap_.config_.decel_limit = get_float(msg, 4); +} + +void CANSimple::set_traj_A_per_css_callback(Axis* axis, CAN_message_t& msg) { + axis->trap_.config_.A_per_css = get_float(msg, 0); +} + + void CANSimple::send_heartbeat(Axis* axis) { CAN_message_t txmsg; txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; - txmsg.id += MSG_CO_HEARTBEAT_CMD; // heartbeat ID + txmsg.id += MSG_ODRIVE_HEARTBEAT; // heartbeat ID txmsg.isExt = false; txmsg.len = 8; @@ -219,11 +257,15 @@ uint8_t CANSimple::get_cmd_id(uint32_t msgID) { return (msgID & 0x01F); // Bottom 5 bits } -uint16_t CANSimple::get_16bit_val(CAN_message_t& msg, uint8_t start_byte) { +int16_t CANSimple::get_16bit_val(CAN_message_t& msg, uint8_t start_byte) { return msg.buf[start_byte] + (msg.buf[start_byte + 1] << 8); } -uint32_t CANSimple::get_32bit_val(CAN_message_t& msg, uint8_t start_byte) { - return get_16bit_val(msg, 0) + (get_16bit_val(msg, 2) << 16); - // return msg.buf[start_byte] + (msg.buf[start_byte+1] << 8) + (msg.buf[start_byte+1] << 16) + (msg.buf[start_byte+1] << 24); +int32_t CANSimple::get_32bit_val(CAN_message_t& msg, uint8_t start_byte) { + return get_16bit_val(msg, start_byte) + (get_16bit_val(msg, start_byte + 2) << 16); +} + +float CANSimple::get_float(CAN_message_t& msg, uint8_t start_byte){ + int32_t val = get_32bit_val(msg, start_byte); + return *(reinterpret_cast(val)); // Sexy int32_t -> float cast } \ No newline at end of file diff --git a/Firmware/communication/can_simple.hpp b/Firmware/communication/can_simple.hpp index f1b63998..269fa956 100644 --- a/Firmware/communication/can_simple.hpp +++ b/Firmware/communication/can_simple.hpp @@ -7,22 +7,26 @@ class CANSimple { public: enum { MSG_CO_NMT_CTRL = 0x000, // CANOpen NMT Message REC - MSG_CO_SYNC_CTRL = 0x080, // CANOpen SYNC message REC MSG_CO_HEARTBEAT_CMD = 0x700, // CANOpen NMT Heartbeat SEND - MSG_CO_EMERGENCY = 0x080, // CANOpen Emergency Message SEND - MSG_GET_MOTOR_ERROR = 0x001, // Errors + MSG_ODRIVE_HEARTBEAT = 0x001, + MSG_ODRIVE_ESTOP, + MSG_GET_MOTOR_ERROR, // Errors MSG_GET_ENCODER_ERROR, MSG_GET_SENSORLESS_ERROR, MSG_SET_AXIS_NODE_ID, MSG_SET_AXIS_REQUESTED_STATE, MSG_SET_AXIS_STARTUP_CONFIG, MSG_GET_ENCODER_ESTIMATES, + MSG_GET_ENCODER_COUNT, MSG_MOVE_TO_POS, MSG_SET_POS_SETPOINT, MSG_SET_VEL_SETPOINT, MSG_SET_CUR_SETPOINT, MSG_SET_VEL_LIMIT, - MSG_START_ANTICOGGING + MSG_START_ANTICOGGING, + MSG_SET_TRAJ_VEL_LIMIT, + MSG_SET_TRAJ_ACCEL_LIMITS, + MSG_SET_TRAJ_A_PER_CSS }; static void handle_can_message(CAN_message_t& msg); @@ -30,7 +34,6 @@ class CANSimple { private: static void nmt_callback(Axis* axis, CAN_message_t& msg); - static void sync_callback(Axis* axis, CAN_message_t& msg); static void estop_callback(Axis* axis, CAN_message_t& msg); static void get_motor_error_callback(Axis* axis, CAN_message_t& msg); static void get_encoder_error_callback(Axis* axis, CAN_message_t& msg); @@ -40,19 +43,25 @@ class CANSimple { static void set_axis_requested_state_callback(Axis* axis, CAN_message_t& msg); static void set_axis_startup_config_callback(Axis* axis, CAN_message_t& msg); static void get_encoder_estimates_callback(Axis* axis, CAN_message_t& msg); + static void get_encoder_count_callback(Axis* axis, CAN_message_t& msg); static void move_to_pos_callback(Axis* axis, CAN_message_t& msg); static void set_pos_setpoint_callback(Axis* axis, CAN_message_t& msg); static void set_vel_setpoint_callback(Axis* axis, CAN_message_t& msg); static void set_current_setpoint_callback(Axis* axis, CAN_message_t& msg); static void set_vel_limit_callback(Axis* axis, CAN_message_t& msg); static void start_anticogging_callback(Axis* axis, CAN_message_t& msg); + static void set_traj_vel_limit_callback(Axis* axis, CAN_message_t& msg); + static void set_traj_accel_limits_callback(Axis* axis, CAN_message_t& msg); + static void set_traj_A_per_css_callback(Axis* axis, CAN_message_t& msg); + // Utility functions static uint8_t get_node_id(uint32_t msgID); static uint8_t get_cmd_id(uint32_t msgID); - static uint16_t get_16bit_val(CAN_message_t& msg, uint8_t start_byte); - static uint32_t get_32bit_val(CAN_message_t& msg, uint8_t start_byte); + static int16_t get_16bit_val(CAN_message_t& msg, uint8_t start_byte); + static int32_t get_32bit_val(CAN_message_t& msg, uint8_t start_byte); + static float get_float(CAN_message_t& msg, uint8_t start_byte); // This functional way of handling the messages is neat and is much cleaner from // a data security point of view, but it will require some tweaking diff --git a/docs/can-protocol.md b/docs/can-protocol.md new file mode 100644 index 00000000..212220d4 --- /dev/null +++ b/docs/can-protocol.md @@ -0,0 +1,105 @@ +# CAN Protocol + +## Hardware Setup +ODrive assumes the CAN PHY is a standard differential twisted pair in a linear bus configuration with 120 ohm termination resistance at each end. ODrive uses 3.3v as the high output, but conforms to the CAN PHY requirement of achieving a differential voltage > 1.5V to represent a "0". As such, it is compatible with standard 5V bus architectures. + +ODrive currently supports the following CAN baud rates: +* 125 kbps +* 250 kbps (default) +* 500 kbps +* 1000 kbps + +--- +## Transport Protocol +We've implemented a very basic CAN protocol that we call "CAN Simple" to get users going with ODrive. This protocol is sufficiently abstracted that it is straightforward to add other protocols such as CANOpen, J1939, or Fibre over ISO-TP in the future. Unfortunately, implementing those protocols is a lot of work, and we wanted to give users a way to control ODrive's basic functions via CAN sooner rather than later. + +### CAN Frame +At its most basic, the CAN Simple frame looks like this: + +* Upper 6 bits - Node ID - max 0x3F +* Lower 5 bits - Command ID - max 0x1F + +To understand how the Node ID and Command ID interact, let's look at an example + +`odrv0.axis0.can_node_id = 0x010` - Reserves messages 0x200 through 0x21F +`odrv0.axis1.can_node_id = 0x018` - Reserves messages 0x300 through 0x31F + +It may not be obvious, but this allows for some compatibility with CANOpen. Although the address space 0x200 and 0x300 correspond to receive PDO base addresses, we can guarantee they will not conflict if all CANopen node IDs are >= 32. E.g.: + +CANopen nodeID = 35 = 0x23 +Receive PDO 0x200 + nodeID = 0x223, which does not conflict with the range [0x200 : 0x21F] + +Be careful that you don't assign too many nodeIDs per PDO group. Four CAN Simple nodes (32*4) is all of the available address space of a single PDO. If the bus is strictly ODrive CAN Simple nodes, a simple sequential Node ID assignment will work fine. + +### Messages +CMD ID | Name | Sender | Signals | Start byte +--: | :-- | :-- | :-- | :-- +0x000 | CANOpen NMT Message\*\* | Master | - | - | - +0x700 | CANOpen Heartbeat Message\*\* | Slave | - | - | - +0x001 | ODrive Heartbeat Message | Axis | Axis Error
Axis Current State | 0
4 +0x002 | ODrive Estop Message | Master | - | - | - +0x003 | Get Motor Error\* | Axis | Motor Error | 0 +0x004 | Get Encoder Error\* | Axis | Encoder Error | 0 +0x005 | Get Sensorless Error\* | Axis | Sensorless Error | 0 +0x006 | Set Axis Node ID | Master | Axis CAN Node ID | 0 +0x007 | Set Axis Requested State | Master | Axis Requested State | 0 +0x008 | Set Axis Startup Config | Master | - Not yet implemented - | - +0x009 | Get Encoder Estimates\* | Master | Encoder Pos Estimate
Encoder Vel Estimate | 0
4 +0x010 | Get Encoder Count\* | Master | Encoder Shadow Count
Encoder Count in CPR | 0
4 +0x011 | Move To Pos | Master | Goal Position | 0 +0x012 | Set Pos Setpoint | Master | Pos Setpoint
Vel FF
Current FF | 0
4
6 +0x013 | Set Vel Setpoint | Master | Vel Setpoint
Current FF | 0
4 +0x014 | Set Current Setpoint | Master | Current Setpoint | 0 +0x015 | Set Velocity Limit | Master | Velocity Limit | 0 +0x016 | Start Anticogging | Master | - | - +0x017 | Set Traj Vel Limit | Master | Traj Vel Limit | 0 +0x018 | Set Traj Accel Limits | Master | Traj Accel Limit
Traj Decel Limit | 0
4 +0x019 | Set Traj A per Count / s^2 | Master | Traj A per CSS | 0 + +\* Note: These messages are call & response. The Master node sends a message with no payload, and the axis responds with the same ID and specified payload. +\*\* Note: These CANOpen messages are reserved to avoid bus collisions with CANOpen devices. They are not used by CAN Simple. + +--- +### Signals +Name | Type | Bits | Factor | Offset | Byte Order +:-- | :-- | :--: | --: | :--: | :--: +Axis Error | Unsigned Int | 32 | 1 | 0 | Intel +Axis Current State | Unsigned Int | 32 | 1 | 0 | Intel +Motor Error | Unsigned Int | 32 | 1 | 0 | Intel +Encoder Error | Unsigned Int | 32 | 1 | 0 | Intel +Sensorless Error | Unsigned Int | 32 | 1 | 0 | Intel +Axis CAN Node ID | Unsigned Int | 16 | 1 | 0 | Intel +Axis Requested State | Unsigned Int | 32 | 1 | 0 | Intel +Encoder Pos Estimate | IEEE 754 Float | 32 | 1 | 0 | Intel +Encoder Vel Estimate | IEEE 754 Float | 32 | 1 | 0 | Intel +Encoder Shadow Count | Signed Int | 32 | 1 | 0 | Intel +Encoder Count In CPR | Signed Int | 32 | 1 | 0 | Intel +Goal Position | Signed Int | 32 | 1 | 0 | Intel +Pos Setpoint | Signed Int | 32 | 1 | 0 | Intel +Vel FF | Signed Int | 16 | 0.1 | 0 | Intel +Current FF | Signed Int | 16 | 0.01 | 0 | Intel +Vel Setpoint | Signed Int | 32 | 0.01 | 0 | Intel +Current Setpoint | Signed Int | 32 | 0.01 | 0 | Intel +Velocity Limit | IEEE 754 Float | 32 | 1 | 0 | Intel +Traj Vel Limit | IEEE 754 Float | 32 | 1 | 0 | Intel +Traj Accel Limit | IEEE 754 Float | 32 | 1 | 0 | Intel +Traj Decel Limit | IEEE 754 Float | 32 | 1 | 0 | Intel +Traj A per CSS | IEEE 754 Float | 32 | 1 | 0 | Intel + +--- +## Configuring ODrive for CAN +Configuration of the CAN parameters should be done via USB before putting the device on the bus. + +To set the desired baud rate, use `.can.set_baud_rate()`. The baud rate can be done without rebooting the device. If you'd like to keep the baud rate, simply call `.save_configuration()` before rebooting. + +Each axis looks like a separate node on the bus. Thus, they've inherited a new configuration property: `can_node_id`. This ID can be from 0 to 63 (0x3F) inclusive. + +### Example Configuration + +``` +odrv0.axis0.config.can_node_id = 3 +odrv0.axis1.config.can_node_id = 1 +odrv0.can.set_baud_rate(500000) +odrv0.save_configuration() +odrv0.reboot() +``` From 87f3a1b011d0bf59e66618d51761931ff4f8c72c Mon Sep 17 00:00:00 2001 From: Unknown Date: Sun, 28 Oct 2018 18:45:15 -0400 Subject: [PATCH 29/72] Bump comms thread stack space to 6000 --- Firmware/communication/communication.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Firmware/communication/communication.cpp b/Firmware/communication/communication.cpp index 843f46b3..dfeabfef 100644 --- a/Firmware/communication/communication.cpp +++ b/Firmware/communication/communication.cpp @@ -84,7 +84,7 @@ void init_communication(void) { printf("hi!\r\n"); // Start command handling thread - osThreadDef(task_cmd_parse, communication_task, osPriorityNormal, 0, 5000 /* in 32-bit words */); // TODO: fix stack issues + osThreadDef(task_cmd_parse, communication_task, osPriorityNormal, 0, 6000 /* in 32-bit words */); // TODO: fix stack issues comm_thread = osThreadCreate(osThread(task_cmd_parse), NULL); while (!endpoint_list_valid) From 3a74ea1791848417b573fc7f573814fae3ea69b6 Mon Sep 17 00:00:00 2001 From: Unknown Date: Sun, 18 Nov 2018 01:05:04 -0500 Subject: [PATCH 30/72] Remove undefined behaviour from float->int casts --- Firmware/communication/can_simple.cpp | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/Firmware/communication/can_simple.cpp b/Firmware/communication/can_simple.cpp index df19d269..07a19001 100644 --- a/Firmware/communication/can_simple.cpp +++ b/Firmware/communication/can_simple.cpp @@ -1,6 +1,8 @@ #include "can_simple.hpp" +#include + static const uint8_t NUM_NODE_ID_BITS = 6; static constexpr uint8_t NUM_CMD_ID_BITS = 11 - NUM_NODE_ID_BITS; @@ -155,13 +157,20 @@ void CANSimple::get_encoder_estimates_callback(Axis* axis, CAN_message_t& msg) { txmsg.isExt = false; txmsg.len = 8; - uint32_t floatBytes = *(reinterpret_cast(&(axis->encoder_.pos_estimate_))); + // Undefined behaviour! + // uint32_t floatBytes = *(reinterpret_cast(&(axis->encoder_.pos_estimate_))); + + uint32_t floatBytes; + static_assert(sizeof axis->encoder_.pos_estimate_ == sizeof floatBytes); + std::memcpy(&floatBytes, &axis->encoder_.pos_estimate_, sizeof floatBytes); + txmsg.buf[0] = floatBytes; txmsg.buf[1] = floatBytes >> 8; txmsg.buf[2] = floatBytes >> 16; txmsg.buf[3] = floatBytes >> 24; - floatBytes = *(reinterpret_cast(&(axis->encoder_.vel_estimate_))); + static_assert(sizeof floatBytes == sizeof axis->encoder_.vel_estimate_); + std::memcpy(&floatBytes, &axis->encoder_.vel_estimate_, sizeof floatBytes); txmsg.buf[4] = floatBytes; txmsg.buf[5] = floatBytes >> 8; txmsg.buf[6] = floatBytes >> 16; @@ -267,5 +276,9 @@ int32_t CANSimple::get_32bit_val(CAN_message_t& msg, uint8_t start_byte) { float CANSimple::get_float(CAN_message_t& msg, uint8_t start_byte){ int32_t val = get_32bit_val(msg, start_byte); - return *(reinterpret_cast(val)); // Sexy int32_t -> float cast + float retVal; + + static_assert(sizeof retVal == sizeof val); + std::memcpy(&retVal, &val, sizeof val); // Sexier int32_t -> float cast that isn't UB + return retVal; } \ No newline at end of file From b45e58858d03a42b0637e65da21ba2019251bf44 Mon Sep 17 00:00:00 2001 From: Unknown Date: Wed, 21 Nov 2018 21:44:36 -0500 Subject: [PATCH 31/72] Fix HEX counting mistake -_- --- docs/can-protocol.md | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/docs/can-protocol.md b/docs/can-protocol.md index 212220d4..d3da2473 100644 --- a/docs/can-protocol.md +++ b/docs/can-protocol.md @@ -45,16 +45,16 @@ CMD ID | Name | Sender | Signals | Start byte 0x007 | Set Axis Requested State | Master | Axis Requested State | 0 0x008 | Set Axis Startup Config | Master | - Not yet implemented - | - 0x009 | Get Encoder Estimates\* | Master | Encoder Pos Estimate
Encoder Vel Estimate | 0
4 -0x010 | Get Encoder Count\* | Master | Encoder Shadow Count
Encoder Count in CPR | 0
4 -0x011 | Move To Pos | Master | Goal Position | 0 -0x012 | Set Pos Setpoint | Master | Pos Setpoint
Vel FF
Current FF | 0
4
6 -0x013 | Set Vel Setpoint | Master | Vel Setpoint
Current FF | 0
4 -0x014 | Set Current Setpoint | Master | Current Setpoint | 0 -0x015 | Set Velocity Limit | Master | Velocity Limit | 0 -0x016 | Start Anticogging | Master | - | - -0x017 | Set Traj Vel Limit | Master | Traj Vel Limit | 0 -0x018 | Set Traj Accel Limits | Master | Traj Accel Limit
Traj Decel Limit | 0
4 -0x019 | Set Traj A per Count / s^2 | Master | Traj A per CSS | 0 +0x00A | Get Encoder Count\* | Master | Encoder Shadow Count
Encoder Count in CPR | 0
4 +0x00B | Move To Pos | Master | Goal Position | 0 +0x00C | Set Pos Setpoint | Master | Pos Setpoint
Vel FF
Current FF | 0
4
6 +0x00D | Set Vel Setpoint | Master | Vel Setpoint
Current FF | 0
4 +0x00E | Set Current Setpoint | Master | Current Setpoint | 0 +0x00F | Set Velocity Limit | Master | Velocity Limit | 0 +0x010 | Start Anticogging | Master | - | - +0x011 | Set Traj Vel Limit | Master | Traj Vel Limit | 0 +0x012 | Set Traj Accel Limits | Master | Traj Accel Limit
Traj Decel Limit | 0
4 +0x013 | Set Traj A per Count / s^2 | Master | Traj A per CSS | 0 \* Note: These messages are call & response. The Master node sends a message with no payload, and the axis responds with the same ID and specified payload. \*\* Note: These CANOpen messages are reserved to avoid bus collisions with CANOpen devices. They are not used by CAN Simple. From f2b66ab881d7d2468945f0cb0b81a77801589ac0 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Tue, 29 Jan 2019 19:45:50 +0100 Subject: [PATCH 32/72] Add Get IQ Message --- Firmware/communication/can_simple.cpp | 39 +++++++++++++++++++++++++++ Firmware/communication/can_simple.hpp | 4 ++- docs/can-protocol.md | 3 +++ 3 files changed, 45 insertions(+), 1 deletion(-) diff --git a/Firmware/communication/can_simple.cpp b/Firmware/communication/can_simple.cpp index 07a19001..78021b5b 100644 --- a/Firmware/communication/can_simple.cpp +++ b/Firmware/communication/can_simple.cpp @@ -1,5 +1,6 @@ #include "can_simple.hpp" +#include #include @@ -81,6 +82,18 @@ void CANSimple::handle_can_message(CAN_message_t& msg) { case MSG_START_ANTICOGGING: start_anticogging_callback(axis, msg); break; + case MSG_SET_TRAJ_A_PER_CSS: + set_traj_A_per_css_callback(axis, msg); + break; + case MSG_SET_TRAJ_ACCEL_LIMITS: + set_traj_accel_limits_callback(axis, msg); + break; + case MSG_SET_TRAJ_VEL_LIMIT: + set_traj_vel_limit_callback(axis, msg); + break; + case MSG_GET_IQ: + get_iq_callback(axis, msg); + break; default: break; } @@ -236,6 +249,32 @@ void CANSimple::set_traj_A_per_css_callback(Axis* axis, CAN_message_t& msg) { axis->trap_.config_.A_per_css = get_float(msg, 0); } +void CANSimple::get_iq_callback(Axis* axis, CAN_message_t& msg){ + CAN_message_t txmsg; + txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; + txmsg.id += MSG_GET_IQ; + txmsg.isExt = false; + txmsg.len = 8; + + uint32_t floatBytes; + static_assert(sizeof axis->motor_.current_control_.Iq_setpoint == sizeof floatBytes); + std::memcpy(&floatBytes, &axis->motor_.current_control_.Iq_setpoint, sizeof floatBytes); + + txmsg.buf[0] = floatBytes; + txmsg.buf[1] = floatBytes >> 8; + txmsg.buf[2] = floatBytes >> 16; + txmsg.buf[3] = floatBytes >> 24; + + static_assert(sizeof floatBytes == sizeof axis->motor_.current_control_.Iq_measured); + std::memcpy(&floatBytes, &axis->motor_.current_control_.Iq_measured, sizeof floatBytes); + txmsg.buf[4] = floatBytes; + txmsg.buf[5] = floatBytes >> 8; + txmsg.buf[6] = floatBytes >> 16; + txmsg.buf[7] = floatBytes >> 24; + + odCAN->write(txmsg); +} + void CANSimple::send_heartbeat(Axis* axis) { CAN_message_t txmsg; diff --git a/Firmware/communication/can_simple.hpp b/Firmware/communication/can_simple.hpp index 269fa956..56bb209f 100644 --- a/Firmware/communication/can_simple.hpp +++ b/Firmware/communication/can_simple.hpp @@ -26,7 +26,8 @@ class CANSimple { MSG_START_ANTICOGGING, MSG_SET_TRAJ_VEL_LIMIT, MSG_SET_TRAJ_ACCEL_LIMITS, - MSG_SET_TRAJ_A_PER_CSS + MSG_SET_TRAJ_A_PER_CSS, + MSG_GET_IQ, }; static void handle_can_message(CAN_message_t& msg); @@ -53,6 +54,7 @@ class CANSimple { static void set_traj_vel_limit_callback(Axis* axis, CAN_message_t& msg); static void set_traj_accel_limits_callback(Axis* axis, CAN_message_t& msg); static void set_traj_A_per_css_callback(Axis* axis, CAN_message_t& msg); + static void get_iq_callback(Axis* axis, CAN_message_t& msg); // Utility functions diff --git a/docs/can-protocol.md b/docs/can-protocol.md index d3da2473..17f2975f 100644 --- a/docs/can-protocol.md +++ b/docs/can-protocol.md @@ -55,6 +55,7 @@ CMD ID | Name | Sender | Signals | Start byte 0x011 | Set Traj Vel Limit | Master | Traj Vel Limit | 0 0x012 | Set Traj Accel Limits | Master | Traj Accel Limit
Traj Decel Limit | 0
4 0x013 | Set Traj A per Count / s^2 | Master | Traj A per CSS | 0 +0x014 | Get IQ\* | Axis | Iq Setpoint | Iq Measured \* Note: These messages are call & response. The Master node sends a message with no payload, and the axis responds with the same ID and specified payload. \*\* Note: These CANOpen messages are reserved to avoid bus collisions with CANOpen devices. They are not used by CAN Simple. @@ -85,6 +86,8 @@ Traj Vel Limit | IEEE 754 Float | 32 | 1 | 0 | Intel Traj Accel Limit | IEEE 754 Float | 32 | 1 | 0 | Intel Traj Decel Limit | IEEE 754 Float | 32 | 1 | 0 | Intel Traj A per CSS | IEEE 754 Float | 32 | 1 | 0 | Intel +Iq Setpoint | IEEE 754 Float | 32 | 1 | 0 | Intel +Iq Measured | IEEE 754 Float | 32 | 1 | 0 | Intel --- ## Configuring ODrive for CAN From 3ecbdc64af9001e3ae1ce1965c2c127e9db44d75 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Tue, 29 Jan 2019 19:47:07 +0100 Subject: [PATCH 33/72] Add missing start bytes --- docs/can-protocol.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/can-protocol.md b/docs/can-protocol.md index 17f2975f..56a27055 100644 --- a/docs/can-protocol.md +++ b/docs/can-protocol.md @@ -55,7 +55,7 @@ CMD ID | Name | Sender | Signals | Start byte 0x011 | Set Traj Vel Limit | Master | Traj Vel Limit | 0 0x012 | Set Traj Accel Limits | Master | Traj Accel Limit
Traj Decel Limit | 0
4 0x013 | Set Traj A per Count / s^2 | Master | Traj A per CSS | 0 -0x014 | Get IQ\* | Axis | Iq Setpoint | Iq Measured +0x014 | Get IQ\* | Axis | Iq Setpoint | Iq Measured | 0
4 \* Note: These messages are call & response. The Master node sends a message with no payload, and the axis responds with the same ID and specified payload. \*\* Note: These CANOpen messages are reserved to avoid bus collisions with CANOpen devices. They are not used by CAN Simple. From ec1618f430b3f3880a6b2b36af4c3e1eb809fd45 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Tue, 29 Jan 2019 19:50:46 +0100 Subject: [PATCH 34/72] Fix line break in Iq table --- docs/can-protocol.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/can-protocol.md b/docs/can-protocol.md index 56a27055..5e67f567 100644 --- a/docs/can-protocol.md +++ b/docs/can-protocol.md @@ -55,7 +55,7 @@ CMD ID | Name | Sender | Signals | Start byte 0x011 | Set Traj Vel Limit | Master | Traj Vel Limit | 0 0x012 | Set Traj Accel Limits | Master | Traj Accel Limit
Traj Decel Limit | 0
4 0x013 | Set Traj A per Count / s^2 | Master | Traj A per CSS | 0 -0x014 | Get IQ\* | Axis | Iq Setpoint | Iq Measured | 0
4 +0x014 | Get IQ\* | Axis | Iq Setpoint
Iq Measured | 0
4 \* Note: These messages are call & response. The Master node sends a message with no payload, and the axis responds with the same ID and specified payload. \*\* Note: These CANOpen messages are reserved to avoid bus collisions with CANOpen devices. They are not used by CAN Simple. From bf242f13fe3c895d634f7674d6cfadb75f53fa9e Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Thu, 31 Jan 2019 20:11:57 +0100 Subject: [PATCH 35/72] Add "Get Sensorless Estimates" CAN message --- Firmware/communication/can_simple.cpp | 32 +++++++++++++++++++++++++++ Firmware/communication/can_simple.hpp | 2 ++ docs/can-protocol.md | 3 +++ 3 files changed, 37 insertions(+) diff --git a/Firmware/communication/can_simple.cpp b/Firmware/communication/can_simple.cpp index 78021b5b..bfe35858 100644 --- a/Firmware/communication/can_simple.cpp +++ b/Firmware/communication/can_simple.cpp @@ -94,6 +94,9 @@ void CANSimple::handle_can_message(CAN_message_t& msg) { case MSG_GET_IQ: get_iq_callback(axis, msg); break; + case MSG_GET_SENSORLESS_ESTIMATES: + get_sensorless_estimates_callback(axis, msg); + break; default: break; } @@ -192,6 +195,35 @@ void CANSimple::get_encoder_estimates_callback(Axis* axis, CAN_message_t& msg) { odCAN->write(txmsg); } +void CANSimple::get_sensorless_estimates_callback(Axis* axis, CAN_message_t& msg) { + CAN_message_t txmsg; + txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; + txmsg.id += MSG_GET_SENSORLESS_ESTIMATES; // heartbeat ID + txmsg.isExt = false; + txmsg.len = 8; + + // Undefined behaviour! + // uint32_t floatBytes = *(reinterpret_cast(&(axis->encoder_.pos_estimate_))); + + uint32_t floatBytes; + static_assert(sizeof axis->sensorless_estimator_.pll_pos_ == sizeof floatBytes); + std::memcpy(&floatBytes, &axis->sensorless_estimator_.pll_pos_, sizeof floatBytes); + + txmsg.buf[0] = floatBytes; + txmsg.buf[1] = floatBytes >> 8; + txmsg.buf[2] = floatBytes >> 16; + txmsg.buf[3] = floatBytes >> 24; + + static_assert(sizeof floatBytes == sizeof axis->sensorless_estimator_.vel_estimate_); + std::memcpy(&floatBytes, &axis->sensorless_estimator_.vel_estimate_, sizeof floatBytes); + txmsg.buf[4] = floatBytes; + txmsg.buf[5] = floatBytes >> 8; + txmsg.buf[6] = floatBytes >> 16; + txmsg.buf[7] = floatBytes >> 24; + + odCAN->write(txmsg); +} + void CANSimple::get_encoder_count_callback(Axis* axis, CAN_message_t& msg){ CAN_message_t txmsg; txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; diff --git a/Firmware/communication/can_simple.hpp b/Firmware/communication/can_simple.hpp index 56bb209f..4ed630af 100644 --- a/Firmware/communication/can_simple.hpp +++ b/Firmware/communication/can_simple.hpp @@ -28,6 +28,7 @@ class CANSimple { MSG_SET_TRAJ_ACCEL_LIMITS, MSG_SET_TRAJ_A_PER_CSS, MSG_GET_IQ, + MSG_GET_SENSORLESS_ESTIMATES, }; static void handle_can_message(CAN_message_t& msg); @@ -55,6 +56,7 @@ class CANSimple { static void set_traj_accel_limits_callback(Axis* axis, CAN_message_t& msg); static void set_traj_A_per_css_callback(Axis* axis, CAN_message_t& msg); static void get_iq_callback(Axis* axis, CAN_message_t& msg); + static void get_sensorless_estimates_callback(Axis* axis, CAN_message_t& ms); // Utility functions diff --git a/docs/can-protocol.md b/docs/can-protocol.md index 5e67f567..e704439c 100644 --- a/docs/can-protocol.md +++ b/docs/can-protocol.md @@ -56,6 +56,7 @@ CMD ID | Name | Sender | Signals | Start byte 0x012 | Set Traj Accel Limits | Master | Traj Accel Limit
Traj Decel Limit | 0
4 0x013 | Set Traj A per Count / s^2 | Master | Traj A per CSS | 0 0x014 | Get IQ\* | Axis | Iq Setpoint
Iq Measured | 0
4 +0x015 | Get Sensorless Estimates\* | Master | Sensorless Pos Estimate
Sensorless Vel Estimate | 0
4 \* Note: These messages are call & response. The Master node sends a message with no payload, and the axis responds with the same ID and specified payload. \*\* Note: These CANOpen messages are reserved to avoid bus collisions with CANOpen devices. They are not used by CAN Simple. @@ -88,6 +89,8 @@ Traj Decel Limit | IEEE 754 Float | 32 | 1 | 0 | Intel Traj A per CSS | IEEE 754 Float | 32 | 1 | 0 | Intel Iq Setpoint | IEEE 754 Float | 32 | 1 | 0 | Intel Iq Measured | IEEE 754 Float | 32 | 1 | 0 | Intel +Sensorless Pos Estimate | IEEE 754 Float | 32 | 1 | 0 | Intel +Sensorless Vel Estimate | IEEE 754 Float | 32 | 1 | 0 | Intel --- ## Configuring ODrive for CAN From f9765f4d73060fd167f008305e8eda28e115f2fc Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sat, 2 Mar 2019 00:18:29 +0100 Subject: [PATCH 36/72] Add ODrive Reboot message and Get Vbus Voltage message --- Firmware/communication/can_simple.cpp | 31 +++++++++++++++++++++++++++ Firmware/communication/can_simple.hpp | 5 ++++- docs/can-protocol.md | 4 ++++ 3 files changed, 39 insertions(+), 1 deletion(-) diff --git a/Firmware/communication/can_simple.cpp b/Firmware/communication/can_simple.cpp index bfe35858..607495d4 100644 --- a/Firmware/communication/can_simple.cpp +++ b/Firmware/communication/can_simple.cpp @@ -97,6 +97,12 @@ void CANSimple::handle_can_message(CAN_message_t& msg) { case MSG_GET_SENSORLESS_ESTIMATES: get_sensorless_estimates_callback(axis, msg); break; + case MSG_RESET_ODRIVE: + NVIC_SystemReset(); + break; + case MSG_GET_VBUS_VOLTAGE: + get_vbus_voltage_callback(axis, msg); + break; default: break; } @@ -307,6 +313,31 @@ void CANSimple::get_iq_callback(Axis* axis, CAN_message_t& msg){ odCAN->write(txmsg); } +void CANSimple::get_vbus_voltage_callback(Axis* axis, CAN_message_t& msg) { + CAN_message_t txmsg; + + txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; + txmsg.id += MSG_GET_VBUS_VOLTAGE; + txmsg.isExt = false; + txmsg.len = 8; + + uint32_t floatBytes; + static_assert(sizeof vbus_voltage == sizeof floatBytes); + std::memcpy(&floatBytes, &vbus_voltage, sizeof floatBytes); + + // This also works in principle, but I don't have hardware to verify endianness + // std::memcpy(&txmsg.buf[0], &vbus_voltage, sizeof vbus_voltage); + + txmsg.buf[0] = floatBytes; + txmsg.buf[1] = floatBytes >> 8; + txmsg.buf[2] = floatBytes >> 16; + txmsg.buf[3] = floatBytes >> 24; + + txmsg.buf[4] = 0; + txmsg.buf[5] = 0; + txmsg.buf[6] = 0; + txmsg.buf[7] = 0; +} void CANSimple::send_heartbeat(Axis* axis) { CAN_message_t txmsg; diff --git a/Firmware/communication/can_simple.hpp b/Firmware/communication/can_simple.hpp index 4ed630af..fd078c5a 100644 --- a/Firmware/communication/can_simple.hpp +++ b/Firmware/communication/can_simple.hpp @@ -29,6 +29,8 @@ class CANSimple { MSG_SET_TRAJ_A_PER_CSS, MSG_GET_IQ, MSG_GET_SENSORLESS_ESTIMATES, + MSG_RESET_ODRIVE, + MSG_GET_VBUS_VOLTAGE, }; static void handle_can_message(CAN_message_t& msg); @@ -56,7 +58,8 @@ class CANSimple { static void set_traj_accel_limits_callback(Axis* axis, CAN_message_t& msg); static void set_traj_A_per_css_callback(Axis* axis, CAN_message_t& msg); static void get_iq_callback(Axis* axis, CAN_message_t& msg); - static void get_sensorless_estimates_callback(Axis* axis, CAN_message_t& ms); + static void get_sensorless_estimates_callback(Axis* axis, CAN_message_t& msg); + static void get_vbus_voltage_callback(Axis* axis, CAN_message_t& msg); // Utility functions diff --git a/docs/can-protocol.md b/docs/can-protocol.md index e704439c..c66a5d7b 100644 --- a/docs/can-protocol.md +++ b/docs/can-protocol.md @@ -57,9 +57,12 @@ CMD ID | Name | Sender | Signals | Start byte 0x013 | Set Traj A per Count / s^2 | Master | Traj A per CSS | 0 0x014 | Get IQ\* | Axis | Iq Setpoint
Iq Measured | 0
4 0x015 | Get Sensorless Estimates\* | Master | Sensorless Pos Estimate
Sensorless Vel Estimate | 0
4 +0x016 | Reboot ODrive | Master\*\*\* | | +0x017 | Get Vbus Voltage | Master\*\*\* | Vbus Voltage | 0 \* Note: These messages are call & response. The Master node sends a message with no payload, and the axis responds with the same ID and specified payload. \*\* Note: These CANOpen messages are reserved to avoid bus collisions with CANOpen devices. They are not used by CAN Simple. +\*\*\* Note: These messages can be sent to either address on a given ODrive board. --- ### Signals @@ -91,6 +94,7 @@ Iq Setpoint | IEEE 754 Float | 32 | 1 | 0 | Intel Iq Measured | IEEE 754 Float | 32 | 1 | 0 | Intel Sensorless Pos Estimate | IEEE 754 Float | 32 | 1 | 0 | Intel Sensorless Vel Estimate | IEEE 754 Float | 32 | 1 | 0 | Intel +Vbus Voltage | IEEE 754 Float | 32 | 1 | 0 | Intel --- ## Configuring ODrive for CAN From c38abbcc131749b04bdb551e95c82dd473c44eab Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sat, 2 Mar 2019 00:18:45 +0100 Subject: [PATCH 37/72] Check for valid axis ID before handling message... --- Firmware/communication/can_simple.cpp | 163 +++++++++++++------------- 1 file changed, 84 insertions(+), 79 deletions(-) diff --git a/Firmware/communication/can_simple.cpp b/Firmware/communication/can_simple.cpp index 607495d4..68bc1ae7 100644 --- a/Firmware/communication/can_simple.cpp +++ b/Firmware/communication/can_simple.cpp @@ -24,87 +24,92 @@ void CANSimple::handle_can_message(CAN_message_t& msg) { Axis* axis = nullptr; + bool validAxis = false; for (uint8_t i = 0; i < AXIS_COUNT; i++) { if (axes[i]->config_.can_node_id == nodeID) { axis = axes[i]; + validAxis = true; } } - switch (cmd) { - case MSG_CO_NMT_CTRL: - break; - case MSG_CO_HEARTBEAT_CMD: - break; - case MSG_ODRIVE_HEARTBEAT: - // We don't currently do anything to respond to ODrive heartbeat messages - break; - case MSG_ODRIVE_ESTOP: - estop_callback(axis, msg); - break; - case MSG_GET_MOTOR_ERROR: - get_motor_error_callback(axis, msg); - break; - case MSG_GET_ENCODER_ERROR: - get_encoder_error_callback(axis, msg); - break; - case MSG_GET_SENSORLESS_ERROR: - get_sensorless_error_callback(axis, msg); - break; - case MSG_SET_AXIS_NODE_ID: - set_axis_nodeid_callback(axis, msg); - break; - case MSG_SET_AXIS_REQUESTED_STATE: - set_axis_requested_state_callback(axis, msg); - break; - case MSG_SET_AXIS_STARTUP_CONFIG: - set_axis_startup_config_callback(axis, msg); - break; - case MSG_GET_ENCODER_ESTIMATES: - get_encoder_estimates_callback(axis, msg); - break; - case MSG_GET_ENCODER_COUNT: - get_encoder_count_callback(axis, msg); - break; - case MSG_MOVE_TO_POS: - move_to_pos_callback(axis, msg); - break; - case MSG_SET_POS_SETPOINT: - set_pos_setpoint_callback(axis, msg); - break; - case MSG_SET_VEL_SETPOINT: - set_vel_setpoint_callback(axis, msg); - break; - case MSG_SET_CUR_SETPOINT: - set_current_setpoint_callback(axis, msg); - break; - case MSG_SET_VEL_LIMIT: - set_vel_limit_callback(axis, msg); - break; - case MSG_START_ANTICOGGING: - start_anticogging_callback(axis, msg); - break; - case MSG_SET_TRAJ_A_PER_CSS: - set_traj_A_per_css_callback(axis, msg); - break; - case MSG_SET_TRAJ_ACCEL_LIMITS: - set_traj_accel_limits_callback(axis, msg); - break; - case MSG_SET_TRAJ_VEL_LIMIT: - set_traj_vel_limit_callback(axis, msg); - break; - case MSG_GET_IQ: - get_iq_callback(axis, msg); - break; - case MSG_GET_SENSORLESS_ESTIMATES: - get_sensorless_estimates_callback(axis, msg); - break; + + if (validAxis) { + switch (cmd) { + case MSG_CO_NMT_CTRL: + break; + case MSG_CO_HEARTBEAT_CMD: + break; + case MSG_ODRIVE_HEARTBEAT: + // We don't currently do anything to respond to ODrive heartbeat messages + break; + case MSG_ODRIVE_ESTOP: + estop_callback(axis, msg); + break; + case MSG_GET_MOTOR_ERROR: + get_motor_error_callback(axis, msg); + break; + case MSG_GET_ENCODER_ERROR: + get_encoder_error_callback(axis, msg); + break; + case MSG_GET_SENSORLESS_ERROR: + get_sensorless_error_callback(axis, msg); + break; + case MSG_SET_AXIS_NODE_ID: + set_axis_nodeid_callback(axis, msg); + break; + case MSG_SET_AXIS_REQUESTED_STATE: + set_axis_requested_state_callback(axis, msg); + break; + case MSG_SET_AXIS_STARTUP_CONFIG: + set_axis_startup_config_callback(axis, msg); + break; + case MSG_GET_ENCODER_ESTIMATES: + get_encoder_estimates_callback(axis, msg); + break; + case MSG_GET_ENCODER_COUNT: + get_encoder_count_callback(axis, msg); + break; + case MSG_MOVE_TO_POS: + move_to_pos_callback(axis, msg); + break; + case MSG_SET_POS_SETPOINT: + set_pos_setpoint_callback(axis, msg); + break; + case MSG_SET_VEL_SETPOINT: + set_vel_setpoint_callback(axis, msg); + break; + case MSG_SET_CUR_SETPOINT: + set_current_setpoint_callback(axis, msg); + break; + case MSG_SET_VEL_LIMIT: + set_vel_limit_callback(axis, msg); + break; + case MSG_START_ANTICOGGING: + start_anticogging_callback(axis, msg); + break; + case MSG_SET_TRAJ_A_PER_CSS: + set_traj_A_per_css_callback(axis, msg); + break; + case MSG_SET_TRAJ_ACCEL_LIMITS: + set_traj_accel_limits_callback(axis, msg); + break; + case MSG_SET_TRAJ_VEL_LIMIT: + set_traj_vel_limit_callback(axis, msg); + break; + case MSG_GET_IQ: + get_iq_callback(axis, msg); + break; + case MSG_GET_SENSORLESS_ESTIMATES: + get_sensorless_estimates_callback(axis, msg); + break; case MSG_RESET_ODRIVE: NVIC_SystemReset(); break; case MSG_GET_VBUS_VOLTAGE: get_vbus_voltage_callback(axis, msg); break; - default: - break; + default: + break; + } } } @@ -162,7 +167,7 @@ void CANSimple::get_sensorless_error_callback(Axis* axis, CAN_message_t& msg) { } void CANSimple::set_axis_nodeid_callback(Axis* axis, CAN_message_t& msg) { - axis->config_.can_node_id = msg.buf[0] & 0x3F; // Node ID bitmask + axis->config_.can_node_id = msg.buf[0] & 0x3F; // Node ID bitmask } void CANSimple::set_axis_requested_state_callback(Axis* axis, CAN_message_t& msg) { @@ -185,7 +190,7 @@ void CANSimple::get_encoder_estimates_callback(Axis* axis, CAN_message_t& msg) { uint32_t floatBytes; static_assert(sizeof axis->encoder_.pos_estimate_ == sizeof floatBytes); std::memcpy(&floatBytes, &axis->encoder_.pos_estimate_, sizeof floatBytes); - + txmsg.buf[0] = floatBytes; txmsg.buf[1] = floatBytes >> 8; txmsg.buf[2] = floatBytes >> 16; @@ -214,7 +219,7 @@ void CANSimple::get_sensorless_estimates_callback(Axis* axis, CAN_message_t& msg uint32_t floatBytes; static_assert(sizeof axis->sensorless_estimator_.pll_pos_ == sizeof floatBytes); std::memcpy(&floatBytes, &axis->sensorless_estimator_.pll_pos_, sizeof floatBytes); - + txmsg.buf[0] = floatBytes; txmsg.buf[1] = floatBytes >> 8; txmsg.buf[2] = floatBytes >> 16; @@ -230,7 +235,7 @@ void CANSimple::get_sensorless_estimates_callback(Axis* axis, CAN_message_t& msg odCAN->write(txmsg); } -void CANSimple::get_encoder_count_callback(Axis* axis, CAN_message_t& msg){ +void CANSimple::get_encoder_count_callback(Axis* axis, CAN_message_t& msg) { CAN_message_t txmsg; txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; txmsg.id += MSG_GET_ENCODER_COUNT; @@ -287,7 +292,7 @@ void CANSimple::set_traj_A_per_css_callback(Axis* axis, CAN_message_t& msg) { axis->trap_.config_.A_per_css = get_float(msg, 0); } -void CANSimple::get_iq_callback(Axis* axis, CAN_message_t& msg){ +void CANSimple::get_iq_callback(Axis* axis, CAN_message_t& msg) { CAN_message_t txmsg; txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; txmsg.id += MSG_GET_IQ; @@ -297,7 +302,7 @@ void CANSimple::get_iq_callback(Axis* axis, CAN_message_t& msg){ uint32_t floatBytes; static_assert(sizeof axis->motor_.current_control_.Iq_setpoint == sizeof floatBytes); std::memcpy(&floatBytes, &axis->motor_.current_control_.Iq_setpoint, sizeof floatBytes); - + txmsg.buf[0] = floatBytes; txmsg.buf[1] = floatBytes >> 8; txmsg.buf[2] = floatBytes >> 16; @@ -376,11 +381,11 @@ int32_t CANSimple::get_32bit_val(CAN_message_t& msg, uint8_t start_byte) { return get_16bit_val(msg, start_byte) + (get_16bit_val(msg, start_byte + 2) << 16); } -float CANSimple::get_float(CAN_message_t& msg, uint8_t start_byte){ +float CANSimple::get_float(CAN_message_t& msg, uint8_t start_byte) { int32_t val = get_32bit_val(msg, start_byte); float retVal; - + static_assert(sizeof retVal == sizeof val); - std::memcpy(&retVal, &val, sizeof val); // Sexier int32_t -> float cast that isn't UB + std::memcpy(&retVal, &val, sizeof val); // Sexier int32_t -> float cast that isn't UB return retVal; } \ No newline at end of file From 9355444f077e2d35a614663901ebe5ca2b154b66 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Fri, 8 Mar 2019 19:40:21 +0100 Subject: [PATCH 38/72] Fix get_32bit_val call --- Firmware/communication/can_simple.cpp | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Firmware/communication/can_simple.cpp b/Firmware/communication/can_simple.cpp index 68bc1ae7..f716cc72 100644 --- a/Firmware/communication/can_simple.cpp +++ b/Firmware/communication/can_simple.cpp @@ -374,11 +374,17 @@ uint8_t CANSimple::get_cmd_id(uint32_t msgID) { } int16_t CANSimple::get_16bit_val(CAN_message_t& msg, uint8_t start_byte) { - return msg.buf[start_byte] + (msg.buf[start_byte + 1] << 8); + int16_t retVal = 0; + if(msg.len - start_byte >= sizeof(retVal)) + retVal = std::memcpy(&retVal, &(msg.buf[start_byte]), sizeof(retVal)); + return retVal; } int32_t CANSimple::get_32bit_val(CAN_message_t& msg, uint8_t start_byte) { - return get_16bit_val(msg, start_byte) + (get_16bit_val(msg, start_byte + 2) << 16); + int32_t retVal = 0; + if(msg.len - start_byte >= sizeof(retVal)) + std::memcpy(&retVal, &(msg.buf[start_byte]), sizeof(retVal)); + return retVal; } float CANSimple::get_float(CAN_message_t& msg, uint8_t start_byte) { From e8c83dc72fa8a70734e86a190298d2ea2d097a7a Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Fri, 8 Mar 2019 20:27:59 +0100 Subject: [PATCH 39/72] Fix uninitialized mailbox error --- Firmware/communication/interface_can.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Firmware/communication/interface_can.cpp b/Firmware/communication/interface_can.cpp index 2940cdf1..af1af08a 100644 --- a/Firmware/communication/interface_can.cpp +++ b/Firmware/communication/interface_can.cpp @@ -96,7 +96,7 @@ uint32_t ODriveCAN::write(CAN_message_t &txmsg) { header.DLC = txmsg.len; header.TransmitGlobalTime = FunctionalState::DISABLE; - uint32_t retTxMailbox; + uint32_t retTxMailbox = 0; if (HAL_CAN_GetTxMailboxesFreeLevel(handle_) > 0) HAL_CAN_AddTxMessage(handle_, &header, txmsg.buf, &retTxMailbox); From 1a58918eaaa595fbc2445e301bb8f2eefad30590 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Fri, 8 Mar 2019 21:52:27 +0100 Subject: [PATCH 40/72] Fix compilation error in get_16bit_val --- Firmware/communication/can_simple.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Firmware/communication/can_simple.cpp b/Firmware/communication/can_simple.cpp index f716cc72..093cff0c 100644 --- a/Firmware/communication/can_simple.cpp +++ b/Firmware/communication/can_simple.cpp @@ -375,14 +375,14 @@ uint8_t CANSimple::get_cmd_id(uint32_t msgID) { int16_t CANSimple::get_16bit_val(CAN_message_t& msg, uint8_t start_byte) { int16_t retVal = 0; - if(msg.len - start_byte >= sizeof(retVal)) - retVal = std::memcpy(&retVal, &(msg.buf[start_byte]), sizeof(retVal)); + if(msg.len >= start_byte && size_t(msg.len - start_byte) >= sizeof(retVal)) + std::memcpy(&retVal, &(msg.buf[start_byte]), sizeof(retVal)); return retVal; } int32_t CANSimple::get_32bit_val(CAN_message_t& msg, uint8_t start_byte) { int32_t retVal = 0; - if(msg.len - start_byte >= sizeof(retVal)) + if(msg.len >= start_byte && size_t(msg.len - start_byte) >= sizeof(retVal)) std::memcpy(&retVal, &(msg.buf[start_byte]), sizeof(retVal)); return retVal; } From 1296537582d3daa091ae1f15bfa9e796fc87f837 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Fri, 8 Mar 2019 21:53:02 +0100 Subject: [PATCH 41/72] Assign different can_node_ids to each axis by default --- Firmware/MotorControl/axis.cpp | 4 ++++ Firmware/MotorControl/axis.hpp | 1 + Firmware/MotorControl/main.cpp | 1 + 3 files changed, 6 insertions(+) diff --git a/Firmware/MotorControl/axis.cpp b/Firmware/MotorControl/axis.cpp index d3ecaac3..299fca54 100644 --- a/Firmware/MotorControl/axis.cpp +++ b/Firmware/MotorControl/axis.cpp @@ -81,6 +81,10 @@ void Axis::load_default_step_dir_pin_config( config->dir_gpio_pin = hw_config.dir_gpio_pin; } +void Axis::load_default_can_id(const int& id, Config_t& config){ + config.can_node_id = id; +} + void Axis::decode_step_dir_pins() { step_port_ = get_gpio_port_by_pin(config_.step_gpio_pin); step_pin_ = get_gpio_pin_by_pin(config_.step_gpio_pin); diff --git a/Firmware/MotorControl/axis.hpp b/Firmware/MotorControl/axis.hpp index 63e23c23..d567a26c 100644 --- a/Firmware/MotorControl/axis.hpp +++ b/Firmware/MotorControl/axis.hpp @@ -97,6 +97,7 @@ public: void decode_step_dir_pins(); static void load_default_step_dir_pin_config( const AxisHardwareConfig_t& hw_config, Config_t* config); + static void load_default_can_id(const int& id, Config_t& config); bool check_DRV_fault(); bool check_PSU_brownout(); diff --git a/Firmware/MotorControl/main.cpp b/Firmware/MotorControl/main.cpp index b7a7275c..1dc8c404 100644 --- a/Firmware/MotorControl/main.cpp +++ b/Firmware/MotorControl/main.cpp @@ -74,6 +74,7 @@ void load_configuration(void) { axis_configs[i] = Axis::Config_t(); // Default step/dir pins are different, so we need to explicitly load them Axis::load_default_step_dir_pin_config(hw_configs[i].axis_config, &axis_configs[i]); + Axis::load_default_can_id(i, axis_configs[i]); } } else { user_config_loaded_ = true; From 603e0b1bf2e9952121f127336bc73637fc627b7c Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Thu, 14 Mar 2019 21:28:58 +0100 Subject: [PATCH 42/72] Throw a CAN error if we have duplicate node IDs --- Firmware/communication/can_simple.cpp | 9 ++++++++- Firmware/communication/interface_can.cpp | 3 +++ Firmware/communication/interface_can.hpp | 12 ++++++++++++ 3 files changed, 23 insertions(+), 1 deletion(-) diff --git a/Firmware/communication/can_simple.cpp b/Firmware/communication/can_simple.cpp index 093cff0c..538e8d9e 100644 --- a/Firmware/communication/can_simple.cpp +++ b/Firmware/communication/can_simple.cpp @@ -28,7 +28,14 @@ void CANSimple::handle_can_message(CAN_message_t& msg) { for (uint8_t i = 0; i < AXIS_COUNT; i++) { if (axes[i]->config_.can_node_id == nodeID) { axis = axes[i]; - validAxis = true; + if (!validAxis) { + validAxis = true; + } else { + // Duplicate can IDs, don't assign to any axis + odCAN->set_error(ODriveCAN::ERROR_DUPLICATE_CAN_IDS); + validAxis = false; + break; + } } } diff --git a/Firmware/communication/interface_can.cpp b/Firmware/communication/interface_can.cpp index af1af08a..cc8a3745 100644 --- a/Firmware/communication/interface_can.cpp +++ b/Firmware/communication/interface_can.cpp @@ -171,6 +171,9 @@ void ODriveCAN::reinit_can() { status = HAL_CAN_ActivateNotification(handle_, CAN_IT_RX_FIFO0_MSG_PENDING); } +void ODriveCAN::set_error(Error_t error){ + error_ |= error; +} // This function is called by each axis. // It provides an abstraction from the specific CAN protocol in use void ODriveCAN::send_heartbeat(Axis *axis) { diff --git a/Firmware/communication/interface_can.hpp b/Firmware/communication/interface_can.hpp index 4105592b..2690559b 100644 --- a/Firmware/communication/interface_can.hpp +++ b/Firmware/communication/interface_can.hpp @@ -37,16 +37,25 @@ class ODriveCAN { CAN_Protocol_t protocol = CAN_PROTOCOL_SIMPLE; }; + enum Error_t { + ERROR_NONE = 0x00, + ERROR_DUPLICATE_CAN_IDS = 0x01 + }; + ODriveCAN(CAN_HandleTypeDef *handle, ODriveCAN::Config_t &config); // Thread Relevant Data osThreadId thread_id_; + Error_t error_ = ERROR_NONE; + volatile bool thread_id_valid_ = false; bool start_can_server(); void can_server_thread(); void send_heartbeat(Axis *axis); void reinit_can(); + void set_error(Error_t error); + // I/O Functions uint32_t available(); uint32_t write(CAN_message_t &txmsg); @@ -55,6 +64,7 @@ class ODriveCAN { // Communication Protocol Handling auto make_protocol_definitions() { return make_protocol_member_list( + make_protocol_property("error", &error_), make_protocol_object("config", make_protocol_ro_property("baud_rate", &config_.baud)), make_protocol_property("can_protocol", &config_.protocol), @@ -68,4 +78,6 @@ class ODriveCAN { void set_baud_rate(uint32_t baudRate); }; +DEFINE_ENUM_FLAG_OPERATORS(ODriveCAN::Error_t) + #endif // __INTERFACE_CAN_HPP From dc1f0b71b43b9faafb788f846a424bf754f4d1e4 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Thu, 14 Mar 2019 23:14:57 +0100 Subject: [PATCH 43/72] Add missing include path --- Firmware/.vscode/c_cpp_properties.json | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Firmware/.vscode/c_cpp_properties.json b/Firmware/.vscode/c_cpp_properties.json index 5176fa6c..54854572 100644 --- a/Firmware/.vscode/c_cpp_properties.json +++ b/Firmware/.vscode/c_cpp_properties.json @@ -7,6 +7,7 @@ "${workspaceRoot}/fibre/cpp/include/**", "${workspaceRoot}/MotorControl", "${workspaceRoot}/Drivers/DRV8301", + "${workspaceRoot}/communication", "${workspaceRoot}/Board/v3/Inc", "${workspaceRoot}/Board/v3/Drivers/CMSIS/Include", "${workspaceRoot}/Board/v3/Drivers/CMSIS/Device/ST/STM32F4xx/Include", @@ -39,7 +40,7 @@ ], "limitSymbolsToIncludedHeaders": true }, - "compilerPath": "${ARM_GCC_ROOT}/bin/arm-none-eabi-gcc.exe -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -specs=nosys.specs -specs=nano.specs -u _printf_float -u _scanf_float", + "compilerPath": "\"${ARM_GCC_ROOT}/bin/arm-none-eabi-gcc.exe\" -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -specs=nosys.specs -specs=nano.specs -u _printf_float -u _scanf_float", "cStandard": "c11", "cppStandard": "c++14" }, From 13e8138364b97c1752e0fbc4aa1b8a45277e9839 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Thu, 14 Mar 2019 23:15:25 +0100 Subject: [PATCH 44/72] Formatting --- Firmware/communication/can_simple.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Firmware/communication/can_simple.cpp b/Firmware/communication/can_simple.cpp index 538e8d9e..412a88c6 100644 --- a/Firmware/communication/can_simple.cpp +++ b/Firmware/communication/can_simple.cpp @@ -382,14 +382,14 @@ uint8_t CANSimple::get_cmd_id(uint32_t msgID) { int16_t CANSimple::get_16bit_val(CAN_message_t& msg, uint8_t start_byte) { int16_t retVal = 0; - if(msg.len >= start_byte && size_t(msg.len - start_byte) >= sizeof(retVal)) + if (msg.len >= start_byte && size_t(msg.len - start_byte) >= sizeof(retVal)) std::memcpy(&retVal, &(msg.buf[start_byte]), sizeof(retVal)); return retVal; } int32_t CANSimple::get_32bit_val(CAN_message_t& msg, uint8_t start_byte) { int32_t retVal = 0; - if(msg.len >= start_byte && size_t(msg.len - start_byte) >= sizeof(retVal)) + if (msg.len >= start_byte && size_t(msg.len - start_byte) >= sizeof(retVal)) std::memcpy(&retVal, &(msg.buf[start_byte]), sizeof(retVal)); return retVal; } From 230426f8c8cf177520b2e00e308e0638913a0c6d Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Thu, 14 Mar 2019 23:15:58 +0100 Subject: [PATCH 45/72] Declare single-argument constructors explicit --- Firmware/MotorControl/controller.hpp | 2 +- Firmware/MotorControl/sensorless_estimator.hpp | 2 +- Firmware/MotorControl/trapTraj.hpp | 3 ++- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/Firmware/MotorControl/controller.hpp b/Firmware/MotorControl/controller.hpp index 7ffa25b6..020f34d0 100644 --- a/Firmware/MotorControl/controller.hpp +++ b/Firmware/MotorControl/controller.hpp @@ -34,7 +34,7 @@ public: bool setpoints_in_cpr = false; }; - Controller(Config_t& config); + explicit Controller(Config_t& config); void reset(); void set_error(Error_t error); diff --git a/Firmware/MotorControl/sensorless_estimator.hpp b/Firmware/MotorControl/sensorless_estimator.hpp index 6d15820f..719a3227 100644 --- a/Firmware/MotorControl/sensorless_estimator.hpp +++ b/Firmware/MotorControl/sensorless_estimator.hpp @@ -14,7 +14,7 @@ public: float pm_flux_linkage = 1.58e-3f; // [V / (rad/s)] { 5.51328895422 / ( * ) } }; - SensorlessEstimator(Config_t& config); + explicit SensorlessEstimator(Config_t& config); bool update(); diff --git a/Firmware/MotorControl/trapTraj.hpp b/Firmware/MotorControl/trapTraj.hpp index 42dac0ef..fe5f3fec 100644 --- a/Firmware/MotorControl/trapTraj.hpp +++ b/Firmware/MotorControl/trapTraj.hpp @@ -9,13 +9,14 @@ public: float decel_limit = 5000.0f; // [count/s^2] float A_per_css = 0.0f; // [A/(count/s^2)] }; + struct Step_t { float Y; float Yd; float Ydd; }; - TrapezoidalTrajectory(Config_t& config); + explicit TrapezoidalTrajectory(Config_t& config); bool planTrapezoidal(float Xf, float Xi, float Vi, float Vmax, float Amax, float Dmax); Step_t eval(float t); From 06cc3d8b0e044b6597b443a78f0b36c85c370fdc Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Thu, 14 Mar 2019 23:16:22 +0100 Subject: [PATCH 46/72] Implement CppCheck linting via flylint extension --- ODrive_Workspace.code-workspace | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/ODrive_Workspace.code-workspace b/ODrive_Workspace.code-workspace index d858dcc3..a245793e 100644 --- a/ODrive_Workspace.code-workspace +++ b/ODrive_Workspace.code-workspace @@ -11,6 +11,26 @@ } ], "settings": { + "c-cpp-flylint.cppcheck.includePaths": [ + "${workspaceRoot}", + "${workspaceRoot}/fibre/cpp/include/fibre", + "${workspaceRoot}/MotorControl", + "${workspaceRoot}/Drivers/DRV8301", + "${workspaceRoot}/communication" + ], + "c-cpp-flylint.cppcheck.language": "c++", + "c-cpp-flylint.cppcheck.standard": ["c99","c++14"], + "c-cpp-flylint.cppcheck.defines": [ + "STM32F405xx", + "USE_HAL_DRIVER", + "HW_VERSION_MAJOR=3", + "HW_VERSION_MINOR=5", + "HW_VERSION_VOLTAGE=24", + "USB_PROTOCOL_NATIVE", + "__weak=\"__attribute__((weak))\"", + "__packed=\"__attribute__((__packed__))\"", + "__GNUC__" + ], "files.associations": { "memory": "cpp", "utility": "cpp", From fa22c7a2ba3f8a542b709bedda9193e9eff8d59d Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Fri, 15 Mar 2019 23:01:21 +0100 Subject: [PATCH 47/72] Add configurable can_heartbeat_rate in ms --- Firmware/MotorControl/axis.hpp | 1 + Firmware/communication/interface_can.cpp | 20 +++++++++++--------- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/Firmware/MotorControl/axis.hpp b/Firmware/MotorControl/axis.hpp index d567a26c..4eb605a5 100644 --- a/Firmware/MotorControl/axis.hpp +++ b/Firmware/MotorControl/axis.hpp @@ -66,6 +66,7 @@ public: LockinConfig_t lockin; uint8_t can_node_id = 0; // Both axes will have the same id to start + uint32_t can_heartbeat_rate_ms = 100; }; enum thread_signals { diff --git a/Firmware/communication/interface_can.cpp b/Firmware/communication/interface_can.cpp index cc8a3745..173698c3 100644 --- a/Firmware/communication/interface_can.cpp +++ b/Firmware/communication/interface_can.cpp @@ -159,7 +159,7 @@ void ODriveCAN::set_baud_rate(uint32_t baudRate) { default: // baudRate is invalid, so don't accept it. - break; + break; } } @@ -171,21 +171,23 @@ void ODriveCAN::reinit_can() { status = HAL_CAN_ActivateNotification(handle_, CAN_IT_RX_FIFO0_MSG_PENDING); } -void ODriveCAN::set_error(Error_t error){ +void ODriveCAN::set_error(Error_t error) { error_ |= error; } // This function is called by each axis. // It provides an abstraction from the specific CAN protocol in use void ODriveCAN::send_heartbeat(Axis *axis) { // Handle heartbeat message - uint32_t now = osKernelSysTick(); - if (now - axis->last_heartbeat_ >= 100) { - switch (config_.protocol) { - case CAN_PROTOCOL_SIMPLE: - CANSimple::send_heartbeat(axis); - break; + if (axis->config_.can_heartbeat_rate_ms > 0) { + uint32_t now = osKernelSysTick(); + if ((now - axis->last_heartbeat_) >= axis->config_.can_heartbeat_rate_ms) { + switch (config_.protocol) { + case CAN_PROTOCOL_SIMPLE: + CANSimple::send_heartbeat(axis); + break; + } + axis->last_heartbeat_ = now; } - axis->last_heartbeat_ = now; } } From 632fb4f7d17396dd826482067bda023e07d44fc9 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Fri, 15 Mar 2019 23:02:41 +0100 Subject: [PATCH 48/72] Add heartbeat_rate to config protocol --- Firmware/MotorControl/axis.hpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Firmware/MotorControl/axis.hpp b/Firmware/MotorControl/axis.hpp index 4eb605a5..6aeb00f5 100644 --- a/Firmware/MotorControl/axis.hpp +++ b/Firmware/MotorControl/axis.hpp @@ -236,7 +236,8 @@ public: make_protocol_property("finish_on_distance", &config_.lockin.finish_on_distance), make_protocol_property("finish_on_enc_idx", &config_.lockin.finish_on_enc_idx) ), - make_protocol_property("can_node_id", &config_.can_node_id) + make_protocol_property("can_node_id", &config_.can_node_id), + make_protocol_property("can_heartbeat_rate_ms", &config_.can_heartbeat_rate_ms) ), make_protocol_object("motor", motor_.make_protocol_definitions()), make_protocol_object("controller", controller_.make_protocol_definitions()), From 97eccc8ff59b9d77e3712a41a9af9a641f0bc4b4 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sun, 17 Mar 2019 18:30:58 +0100 Subject: [PATCH 49/72] Add rtr bit to can_Message_t --- Firmware/communication/interface_can.hpp | 1 + 1 file changed, 1 insertion(+) diff --git a/Firmware/communication/interface_can.hpp b/Firmware/communication/interface_can.hpp index 2690559b..68479a61 100644 --- a/Firmware/communication/interface_can.hpp +++ b/Firmware/communication/interface_can.hpp @@ -12,6 +12,7 @@ typedef struct { uint32_t id = 0x000; // 11-bit max is 0x7ff, 29-bit max is 0x1FFFFFFF bool isExt = false; + bool rtr = false; uint8_t len = 8; uint8_t buf[8] = {0, 0, 0, 0, 0, 0, 0, 0}; } CAN_message_t; From 4f333511425a13e747dc64c0d22472e1cca04a82 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sun, 17 Mar 2019 18:31:18 +0100 Subject: [PATCH 50/72] Parse RTR from header when reading a CAN message --- Firmware/communication/interface_can.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/Firmware/communication/interface_can.cpp b/Firmware/communication/interface_can.cpp index 173698c3..1ee2e7cc 100644 --- a/Firmware/communication/interface_can.cpp +++ b/Firmware/communication/interface_can.cpp @@ -124,6 +124,7 @@ bool ODriveCAN::read(CAN_message_t &rxmsg) { rxmsg.isExt = header.IDE; rxmsg.id = rxmsg.isExt ? header.ExtId : header.StdId; // If it's an extended message, pass the extended ID rxmsg.len = header.DLC; + rxmsg.rtr = (header.RTR == CAN_RTR_REMOTE) ? true : false; return validRead; } From 1ff263a2b5804243c50c12348641589fb7c99085 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sun, 17 Mar 2019 18:32:14 +0100 Subject: [PATCH 51/72] Fix missing call to Write in get_vbus_voltage --- Firmware/communication/can_simple.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/Firmware/communication/can_simple.cpp b/Firmware/communication/can_simple.cpp index 412a88c6..05148453 100644 --- a/Firmware/communication/can_simple.cpp +++ b/Firmware/communication/can_simple.cpp @@ -349,6 +349,7 @@ void CANSimple::get_vbus_voltage_callback(Axis* axis, CAN_message_t& msg) { txmsg.buf[5] = 0; txmsg.buf[6] = 0; txmsg.buf[7] = 0; + odCAN->write(txmsg); } void CANSimple::send_heartbeat(Axis* axis) { From 9e5704d7e99512b31a5bd9fc81e55df1f26c7926 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sun, 17 Mar 2019 18:32:45 +0100 Subject: [PATCH 52/72] CAN "get" functions should look for RTR --- Firmware/communication/can_simple.cpp | 263 ++++++++++++++------------ 1 file changed, 140 insertions(+), 123 deletions(-) diff --git a/Firmware/communication/can_simple.cpp b/Firmware/communication/can_simple.cpp index 05148453..74d23c21 100644 --- a/Firmware/communication/can_simple.cpp +++ b/Firmware/communication/can_simple.cpp @@ -129,48 +129,54 @@ void CANSimple::estop_callback(Axis* axis, CAN_message_t& msg) { } void CANSimple::get_motor_error_callback(Axis* axis, CAN_message_t& msg) { - CAN_message_t txmsg; - txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; - txmsg.id += MSG_GET_MOTOR_ERROR; // heartbeat ID - txmsg.isExt = false; - txmsg.len = 8; + if (msg.rtr) { + CAN_message_t txmsg; + txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; + txmsg.id += MSG_GET_MOTOR_ERROR; // heartbeat ID + txmsg.isExt = false; + txmsg.len = 8; - txmsg.buf[0] = axis->motor_.error_; - txmsg.buf[1] = axis->motor_.error_ >> 8; - txmsg.buf[2] = axis->motor_.error_ >> 16; - txmsg.buf[3] = axis->motor_.error_ >> 24; + txmsg.buf[0] = axis->motor_.error_; + txmsg.buf[1] = axis->motor_.error_ >> 8; + txmsg.buf[2] = axis->motor_.error_ >> 16; + txmsg.buf[3] = axis->motor_.error_ >> 24; - odCAN->write(txmsg); + odCAN->write(txmsg); + } } void CANSimple::get_encoder_error_callback(Axis* axis, CAN_message_t& msg) { - CAN_message_t txmsg; - txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; - txmsg.id += MSG_GET_ENCODER_ERROR; // heartbeat ID - txmsg.isExt = false; - txmsg.len = 8; + if (msg.rtr) { + CAN_message_t txmsg; + txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; + txmsg.id += MSG_GET_ENCODER_ERROR; // heartbeat ID + txmsg.isExt = false; + txmsg.len = 8; - txmsg.buf[0] = axis->encoder_.error_; - txmsg.buf[1] = axis->encoder_.error_ >> 8; - txmsg.buf[2] = axis->encoder_.error_ >> 16; - txmsg.buf[3] = axis->encoder_.error_ >> 24; + txmsg.buf[0] = axis->encoder_.error_; + txmsg.buf[1] = axis->encoder_.error_ >> 8; + txmsg.buf[2] = axis->encoder_.error_ >> 16; + txmsg.buf[3] = axis->encoder_.error_ >> 24; - odCAN->write(txmsg); + odCAN->write(txmsg); + } } void CANSimple::get_sensorless_error_callback(Axis* axis, CAN_message_t& msg) { - CAN_message_t txmsg; - txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; - txmsg.id += MSG_GET_SENSORLESS_ERROR; // heartbeat ID - txmsg.isExt = false; - txmsg.len = 8; + if (msg.rtr) { + CAN_message_t txmsg; + txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; + txmsg.id += MSG_GET_SENSORLESS_ERROR; // heartbeat ID + txmsg.isExt = false; + txmsg.len = 8; - txmsg.buf[0] = axis->sensorless_estimator_.error_; - txmsg.buf[1] = axis->sensorless_estimator_.error_ >> 8; - txmsg.buf[2] = axis->sensorless_estimator_.error_ >> 16; - txmsg.buf[3] = axis->sensorless_estimator_.error_ >> 24; + txmsg.buf[0] = axis->sensorless_estimator_.error_; + txmsg.buf[1] = axis->sensorless_estimator_.error_ >> 8; + txmsg.buf[2] = axis->sensorless_estimator_.error_ >> 16; + txmsg.buf[3] = axis->sensorless_estimator_.error_ >> 24; - odCAN->write(txmsg); + odCAN->write(txmsg); + } } void CANSimple::set_axis_nodeid_callback(Axis* axis, CAN_message_t& msg) { @@ -185,81 +191,87 @@ void CANSimple::set_axis_startup_config_callback(Axis* axis, CAN_message_t& msg) } void CANSimple::get_encoder_estimates_callback(Axis* axis, CAN_message_t& msg) { - CAN_message_t txmsg; - txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; - txmsg.id += MSG_GET_ENCODER_ESTIMATES; // heartbeat ID - txmsg.isExt = false; - txmsg.len = 8; + if (msg.rtr) { + CAN_message_t txmsg; + txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; + txmsg.id += MSG_GET_ENCODER_ESTIMATES; // heartbeat ID + txmsg.isExt = false; + txmsg.len = 8; - // Undefined behaviour! - // uint32_t floatBytes = *(reinterpret_cast(&(axis->encoder_.pos_estimate_))); + // Undefined behaviour! + // uint32_t floatBytes = *(reinterpret_cast(&(axis->encoder_.pos_estimate_))); - uint32_t floatBytes; - static_assert(sizeof axis->encoder_.pos_estimate_ == sizeof floatBytes); - std::memcpy(&floatBytes, &axis->encoder_.pos_estimate_, sizeof floatBytes); + uint32_t floatBytes; + static_assert(sizeof axis->encoder_.pos_estimate_ == sizeof floatBytes); + std::memcpy(&floatBytes, &axis->encoder_.pos_estimate_, sizeof floatBytes); - txmsg.buf[0] = floatBytes; - txmsg.buf[1] = floatBytes >> 8; - txmsg.buf[2] = floatBytes >> 16; - txmsg.buf[3] = floatBytes >> 24; + txmsg.buf[0] = floatBytes; + txmsg.buf[1] = floatBytes >> 8; + txmsg.buf[2] = floatBytes >> 16; + txmsg.buf[3] = floatBytes >> 24; - static_assert(sizeof floatBytes == sizeof axis->encoder_.vel_estimate_); - std::memcpy(&floatBytes, &axis->encoder_.vel_estimate_, sizeof floatBytes); - txmsg.buf[4] = floatBytes; - txmsg.buf[5] = floatBytes >> 8; - txmsg.buf[6] = floatBytes >> 16; - txmsg.buf[7] = floatBytes >> 24; + static_assert(sizeof floatBytes == sizeof axis->encoder_.vel_estimate_); + std::memcpy(&floatBytes, &axis->encoder_.vel_estimate_, sizeof floatBytes); + txmsg.buf[4] = floatBytes; + txmsg.buf[5] = floatBytes >> 8; + txmsg.buf[6] = floatBytes >> 16; + txmsg.buf[7] = floatBytes >> 24; - odCAN->write(txmsg); + odCAN->write(txmsg); + } } void CANSimple::get_sensorless_estimates_callback(Axis* axis, CAN_message_t& msg) { - CAN_message_t txmsg; - txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; - txmsg.id += MSG_GET_SENSORLESS_ESTIMATES; // heartbeat ID - txmsg.isExt = false; - txmsg.len = 8; + if (msg.rtr) { + CAN_message_t txmsg; + txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; + txmsg.id += MSG_GET_SENSORLESS_ESTIMATES; // heartbeat ID + txmsg.isExt = false; + txmsg.len = 8; - // Undefined behaviour! - // uint32_t floatBytes = *(reinterpret_cast(&(axis->encoder_.pos_estimate_))); + // Undefined behaviour! + // uint32_t floatBytes = *(reinterpret_cast(&(axis->encoder_.pos_estimate_))); - uint32_t floatBytes; - static_assert(sizeof axis->sensorless_estimator_.pll_pos_ == sizeof floatBytes); - std::memcpy(&floatBytes, &axis->sensorless_estimator_.pll_pos_, sizeof floatBytes); + uint32_t floatBytes; + static_assert(sizeof axis->sensorless_estimator_.pll_pos_ == sizeof floatBytes); + std::memcpy(&floatBytes, &axis->sensorless_estimator_.pll_pos_, sizeof floatBytes); - txmsg.buf[0] = floatBytes; - txmsg.buf[1] = floatBytes >> 8; - txmsg.buf[2] = floatBytes >> 16; - txmsg.buf[3] = floatBytes >> 24; + txmsg.buf[0] = floatBytes; + txmsg.buf[1] = floatBytes >> 8; + txmsg.buf[2] = floatBytes >> 16; + txmsg.buf[3] = floatBytes >> 24; - static_assert(sizeof floatBytes == sizeof axis->sensorless_estimator_.vel_estimate_); - std::memcpy(&floatBytes, &axis->sensorless_estimator_.vel_estimate_, sizeof floatBytes); - txmsg.buf[4] = floatBytes; - txmsg.buf[5] = floatBytes >> 8; - txmsg.buf[6] = floatBytes >> 16; - txmsg.buf[7] = floatBytes >> 24; + static_assert(sizeof floatBytes == sizeof axis->sensorless_estimator_.vel_estimate_); + std::memcpy(&floatBytes, &axis->sensorless_estimator_.vel_estimate_, sizeof floatBytes); + txmsg.buf[4] = floatBytes; + txmsg.buf[5] = floatBytes >> 8; + txmsg.buf[6] = floatBytes >> 16; + txmsg.buf[7] = floatBytes >> 24; - odCAN->write(txmsg); + odCAN->write(txmsg); + } } void CANSimple::get_encoder_count_callback(Axis* axis, CAN_message_t& msg) { - CAN_message_t txmsg; - txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; - txmsg.id += MSG_GET_ENCODER_COUNT; - txmsg.isExt = false; - txmsg.len = 8; + if (msg.rtr) { + CAN_message_t txmsg; + txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; + txmsg.id += MSG_GET_ENCODER_COUNT; + txmsg.isExt = false; + txmsg.len = 8; - txmsg.buf[0] = axis->encoder_.shadow_count_; - txmsg.buf[1] = axis->encoder_.shadow_count_ >> 8; - txmsg.buf[2] = axis->encoder_.shadow_count_ >> 16; - txmsg.buf[3] = axis->encoder_.shadow_count_ >> 24; + txmsg.buf[0] = axis->encoder_.shadow_count_; + txmsg.buf[1] = axis->encoder_.shadow_count_ >> 8; + txmsg.buf[2] = axis->encoder_.shadow_count_ >> 16; + txmsg.buf[3] = axis->encoder_.shadow_count_ >> 24; - txmsg.buf[4] = axis->encoder_.count_in_cpr_; - txmsg.buf[5] = axis->encoder_.count_in_cpr_ >> 8; - txmsg.buf[6] = axis->encoder_.count_in_cpr_ >> 16; - txmsg.buf[7] = axis->encoder_.count_in_cpr_ >> 24; + txmsg.buf[4] = axis->encoder_.count_in_cpr_; + txmsg.buf[5] = axis->encoder_.count_in_cpr_ >> 8; + txmsg.buf[6] = axis->encoder_.count_in_cpr_ >> 16; + txmsg.buf[7] = axis->encoder_.count_in_cpr_ >> 24; - odCAN->write(txmsg); + odCAN->write(txmsg); + } } void CANSimple::move_to_pos_callback(Axis* axis, CAN_message_t& msg) { @@ -300,56 +312,61 @@ void CANSimple::set_traj_A_per_css_callback(Axis* axis, CAN_message_t& msg) { } void CANSimple::get_iq_callback(Axis* axis, CAN_message_t& msg) { - CAN_message_t txmsg; - txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; - txmsg.id += MSG_GET_IQ; - txmsg.isExt = false; - txmsg.len = 8; + if (msg.rtr) { + CAN_message_t txmsg; + txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; + txmsg.id += MSG_GET_IQ; + txmsg.isExt = false; + txmsg.len = 8; - uint32_t floatBytes; - static_assert(sizeof axis->motor_.current_control_.Iq_setpoint == sizeof floatBytes); - std::memcpy(&floatBytes, &axis->motor_.current_control_.Iq_setpoint, sizeof floatBytes); + uint32_t floatBytes; + static_assert(sizeof axis->motor_.current_control_.Iq_setpoint == sizeof floatBytes); + std::memcpy(&floatBytes, &axis->motor_.current_control_.Iq_setpoint, sizeof floatBytes); - txmsg.buf[0] = floatBytes; - txmsg.buf[1] = floatBytes >> 8; - txmsg.buf[2] = floatBytes >> 16; - txmsg.buf[3] = floatBytes >> 24; + txmsg.buf[0] = floatBytes; + txmsg.buf[1] = floatBytes >> 8; + txmsg.buf[2] = floatBytes >> 16; + txmsg.buf[3] = floatBytes >> 24; - static_assert(sizeof floatBytes == sizeof axis->motor_.current_control_.Iq_measured); - std::memcpy(&floatBytes, &axis->motor_.current_control_.Iq_measured, sizeof floatBytes); - txmsg.buf[4] = floatBytes; - txmsg.buf[5] = floatBytes >> 8; - txmsg.buf[6] = floatBytes >> 16; - txmsg.buf[7] = floatBytes >> 24; + static_assert(sizeof floatBytes == sizeof axis->motor_.current_control_.Iq_measured); + std::memcpy(&floatBytes, &axis->motor_.current_control_.Iq_measured, sizeof floatBytes); + txmsg.buf[4] = floatBytes; + txmsg.buf[5] = floatBytes >> 8; + txmsg.buf[6] = floatBytes >> 16; + txmsg.buf[7] = floatBytes >> 24; - odCAN->write(txmsg); + odCAN->write(txmsg); + } } void CANSimple::get_vbus_voltage_callback(Axis* axis, CAN_message_t& msg) { - CAN_message_t txmsg; + if (msg.rtr) { + CAN_message_t txmsg; - txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; - txmsg.id += MSG_GET_VBUS_VOLTAGE; - txmsg.isExt = false; - txmsg.len = 8; + txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; + txmsg.id += MSG_GET_VBUS_VOLTAGE; + txmsg.isExt = false; + txmsg.len = 8; - uint32_t floatBytes; - static_assert(sizeof vbus_voltage == sizeof floatBytes); - std::memcpy(&floatBytes, &vbus_voltage, sizeof floatBytes); + uint32_t floatBytes; + static_assert(sizeof vbus_voltage == sizeof floatBytes); + std::memcpy(&floatBytes, &vbus_voltage, sizeof floatBytes); - // This also works in principle, but I don't have hardware to verify endianness - // std::memcpy(&txmsg.buf[0], &vbus_voltage, sizeof vbus_voltage); + // This also works in principle, but I don't have hardware to verify endianness + // std::memcpy(&txmsg.buf[0], &vbus_voltage, sizeof vbus_voltage); - txmsg.buf[0] = floatBytes; - txmsg.buf[1] = floatBytes >> 8; - txmsg.buf[2] = floatBytes >> 16; - txmsg.buf[3] = floatBytes >> 24; + txmsg.buf[0] = floatBytes; + txmsg.buf[1] = floatBytes >> 8; + txmsg.buf[2] = floatBytes >> 16; + txmsg.buf[3] = floatBytes >> 24; + + txmsg.buf[4] = 0; + txmsg.buf[5] = 0; + txmsg.buf[6] = 0; + txmsg.buf[7] = 0; - txmsg.buf[4] = 0; - txmsg.buf[5] = 0; - txmsg.buf[6] = 0; - txmsg.buf[7] = 0; odCAN->write(txmsg); + } } void CANSimple::send_heartbeat(Axis* axis) { From 0a24ce3bf91dbe4672a400c0c263728ed88c3a04 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sun, 17 Mar 2019 18:35:13 +0100 Subject: [PATCH 53/72] Fix minor CppCheck warning --- Firmware/MotorControl/axis.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Firmware/MotorControl/axis.cpp b/Firmware/MotorControl/axis.cpp index 299fca54..bd4b65cc 100644 --- a/Firmware/MotorControl/axis.cpp +++ b/Firmware/MotorControl/axis.cpp @@ -13,8 +13,8 @@ Axis::Axis(const AxisHardwareConfig_t& hw_config, SensorlessEstimator& sensorless_estimator, Controller& controller, Motor& motor, - TrapezoidalTrajectory& trap) - : hw_config_(hw_config), + TrapezoidalTrajectory& trap) : + hw_config_(hw_config), config_(config), encoder_(encoder), sensorless_estimator_(sensorless_estimator), From 4a4c4c836d08f493482991444b5b12fcfe325cfa Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sat, 23 Mar 2019 09:32:18 +0100 Subject: [PATCH 54/72] Fix RTR != header.RTR issue --- Firmware/communication/interface_can.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Firmware/communication/interface_can.cpp b/Firmware/communication/interface_can.cpp index 1ee2e7cc..44cd7e2d 100644 --- a/Firmware/communication/interface_can.cpp +++ b/Firmware/communication/interface_can.cpp @@ -124,7 +124,7 @@ bool ODriveCAN::read(CAN_message_t &rxmsg) { rxmsg.isExt = header.IDE; rxmsg.id = rxmsg.isExt ? header.ExtId : header.StdId; // If it's an extended message, pass the extended ID rxmsg.len = header.DLC; - rxmsg.rtr = (header.RTR == CAN_RTR_REMOTE) ? true : false; + rxmsg.rtr = header.RTR; return validRead; } From 0c68cd929875f4223a16975a231aee933372462b Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sat, 23 Mar 2019 09:35:05 +0100 Subject: [PATCH 55/72] Fix error code for Estop --- Firmware/MotorControl/axis.hpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Firmware/MotorControl/axis.hpp b/Firmware/MotorControl/axis.hpp index b37628cc..7971f475 100644 --- a/Firmware/MotorControl/axis.hpp +++ b/Firmware/MotorControl/axis.hpp @@ -21,7 +21,7 @@ public: ERROR_CONTROLLER_FAILED = 0x200, ERROR_POS_CTRL_DURING_SENSORLESS = 0x400, ERROR_WATCHDOG_TIMER_EXPIRED = 0x800, - ERROR_ESTOP_REQUESTED = 0x800 + ERROR_ESTOP_REQUESTED = 0x1000 }; enum State_t { From 850325558fe743c1320cf82914685f38830d3979 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sat, 23 Mar 2019 09:36:09 +0100 Subject: [PATCH 56/72] Feed Axis Watchdog when receiving a valid message --- Firmware/communication/can_simple.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/Firmware/communication/can_simple.cpp b/Firmware/communication/can_simple.cpp index 74d23c21..d6327449 100644 --- a/Firmware/communication/can_simple.cpp +++ b/Firmware/communication/can_simple.cpp @@ -40,6 +40,7 @@ void CANSimple::handle_can_message(CAN_message_t& msg) { } if (validAxis) { + axis->watchdog_feed(); switch (cmd) { case MSG_CO_NMT_CTRL: break; From 703d686ca4dc0f168bbd59930ab1244f2b56e564 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sun, 24 Mar 2019 18:42:29 +0100 Subject: [PATCH 57/72] Update documentation --- docs/can-protocol.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/can-protocol.md b/docs/can-protocol.md index c66a5d7b..fd1c49d1 100644 --- a/docs/can-protocol.md +++ b/docs/can-protocol.md @@ -60,7 +60,7 @@ CMD ID | Name | Sender | Signals | Start byte 0x016 | Reboot ODrive | Master\*\*\* | | 0x017 | Get Vbus Voltage | Master\*\*\* | Vbus Voltage | 0 -\* Note: These messages are call & response. The Master node sends a message with no payload, and the axis responds with the same ID and specified payload. +\* Note: These messages are call & response. The Master node sends a message with the RTR bit set, and the axis responds with the same ID and specified payload. \*\* Note: These CANOpen messages are reserved to avoid bus collisions with CANOpen devices. They are not used by CAN Simple. \*\*\* Note: These messages can be sent to either address on a given ODrive board. From 0598c2c995110283da036b6b886212756082f6a1 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Thu, 16 May 2019 00:03:37 +0200 Subject: [PATCH 58/72] Setup doctest --- Firmware/.vscode/c_cpp_properties.json | 3 ++- Firmware/MotorControl/main.cpp | 9 +++++++++ Firmware/Tests/test_runner.cpp | 18 ++++++++++++++++++ Firmware/Tupfile.lua | 8 +++++--- 4 files changed, 34 insertions(+), 4 deletions(-) create mode 100644 Firmware/Tests/test_runner.cpp diff --git a/Firmware/.vscode/c_cpp_properties.json b/Firmware/.vscode/c_cpp_properties.json index c4a2f37c..7f0685e5 100644 --- a/Firmware/.vscode/c_cpp_properties.json +++ b/Firmware/.vscode/c_cpp_properties.json @@ -17,7 +17,8 @@ "${workspaceRoot}/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc", "${workspaceRoot}/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS", "${workspaceRoot}/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/include", - "${workspaceRoot}/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F" + "${workspaceRoot}/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F", + "C:/Tools/doctest/doctest" ], "defines": [ "STM32F405xx", diff --git a/Firmware/MotorControl/main.cpp b/Firmware/MotorControl/main.cpp index 427792b3..5a90ce17 100644 --- a/Firmware/MotorControl/main.cpp +++ b/Firmware/MotorControl/main.cpp @@ -98,6 +98,7 @@ void enter_dfu_mode() { extern "C" { int odrive_main(void); + void vApplicationStackOverflowHook(xTaskHandle *pxTask, signed portCHAR *pcTaskName) { for (;;); // TODO: safe action } @@ -116,8 +117,16 @@ void vApplicationIdleHook(void) { } } +#include int odrive_main(void) { +doctest::Context context; + +auto vals = context.run(); +while(vals){ + +} + #if HW_VERSION_MAJOR == 3 && HW_VERSION_MINOR >= 3 if (board_config.enable_i2c_instead_of_can) { // Set up the direction GPIO as input diff --git a/Firmware/Tests/test_runner.cpp b/Firmware/Tests/test_runner.cpp new file mode 100644 index 00000000..26238a00 --- /dev/null +++ b/Firmware/Tests/test_runner.cpp @@ -0,0 +1,18 @@ + + +#define DOCTEST_CONFIG_IMPLEMENT +#define DOCTEST_CONFIG_TREAT_CHAR_STAR_AS_STRING +#define DOCTEST_CONFIG_USE_STD_HEADERS +#define DOCTEST_CONFIG_NO_TRY_CATCH_IN_ASSERTS +#define DOCTEST_CONFIG_NO_EXCEPTIONS +#define DOCTEST_CONFIG_NO_WINDOWS_SEH +#define DOCTEST_CONFIG_NO_POSIX_SIGNALS +// #define DOCTEST_CONFIG_VOID_CAST_EXPRESSIONS + +#include + +#include "odrive_main.h" + +TEST_CASE("[something]"){ + CHECK(mod(3, 10) == 3); +} \ No newline at end of file diff --git a/Firmware/Tupfile.lua b/Firmware/Tupfile.lua index 994fd746..5cb2addc 100644 --- a/Firmware/Tupfile.lua +++ b/Firmware/Tupfile.lua @@ -176,12 +176,14 @@ build{ 'communication/interface_can.cpp', 'communication/interface_i2c.cpp', 'fibre/cpp/protocol.cpp', - 'FreeRTOS-openocd.c' + 'FreeRTOS-openocd.c', + 'Tests/test_runner.cpp' }, includes={ 'Drivers/DRV8301', 'MotorControl', 'fibre/cpp/include', - '.' + '.', + "C:/Tools/doctest/doctest" } -} +} \ No newline at end of file From 9315c4e1c724292e9c9dcb72f7b2a2c0c094e059 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sun, 19 May 2019 21:18:18 +0200 Subject: [PATCH 59/72] Write and test CAN getSignal function --- Firmware/Tests/test_runner.cpp | 80 ++++++++++++++++++++++++++++++++-- Firmware/Tupfile.lua | 3 +- 2 files changed, 77 insertions(+), 6 deletions(-) diff --git a/Firmware/Tests/test_runner.cpp b/Firmware/Tests/test_runner.cpp index 26238a00..dfaaf981 100644 --- a/Firmware/Tests/test_runner.cpp +++ b/Firmware/Tests/test_runner.cpp @@ -1,6 +1,6 @@ -#define DOCTEST_CONFIG_IMPLEMENT +#define DOCTEST_CONFIG_IMPLEMENT_WITH_MAIN #define DOCTEST_CONFIG_TREAT_CHAR_STAR_AS_STRING #define DOCTEST_CONFIG_USE_STD_HEADERS #define DOCTEST_CONFIG_NO_TRY_CATCH_IN_ASSERTS @@ -11,8 +11,80 @@ #include -#include "odrive_main.h" +using std::cout; +using std::endl; +struct can_Message_t { + uint32_t id = 0x000; // 11-bit max is 0x7ff, 29-bit max is 0x1FFFFFFF + bool isExt = false; + bool rtr = false; + uint8_t len = 8; + uint8_t buf[8] = {0, 0, 0, 0, 0, 0, 0, 0}; +}; -TEST_CASE("[something]"){ - CHECK(mod(3, 10) == 3); +struct can_Signal_t { + uint8_t startBit = 0; + uint8_t length = 16; + bool isIntel = true; + float factor = 1.0f; + float offset = 0.0f; +}; + +// Fetch a specific signal from the message +template +T getSignal(can_Message_t msg, uint8_t startBit, uint8_t length, bool isIntel, float factor, float offset) { + uint64_t tempVal = 0; + uint64_t mask = (1ULL << length) - 1; + + if (isIntel) { + std::memcpy(&tempVal, msg.buf, sizeof(tempVal)); + tempVal = (tempVal >> startBit) & mask; + } else { + std::reverse(std::begin(msg.buf), std::end(msg.buf)); + std::memcpy(&tempVal, msg.buf, sizeof(tempVal)); + tempVal = (tempVal >> (64 - startBit - length)) & mask; + } + + T retVal; + std::memcpy(&retVal, &tempVal, sizeof(T)); + return static_cast((retVal * factor) + offset); +} + +// template +// T can_getSignal(can_Message_t msg, can_Signal_t signal){ +// return can_getSignal(msg, signal.startBit, signal.length, signal.isIntel, signal.factor, signal.offset); +// } + +TEST_SUITE("getSignal") { + TEST_CASE("reverse") { + can_Message_t rxmsg; + rxmsg.id = 0x000; + rxmsg.isExt = false; + rxmsg.len = 8; + + rxmsg.buf[0] = 0x12; + rxmsg.buf[1] = 0x34; + + std::reverse(std::begin(rxmsg.buf), std::end(rxmsg.buf)); + CHECK(rxmsg.buf[0] == 0x00); + CHECK(rxmsg.buf[6] == 0x34); + CHECK(rxmsg.buf[7] == 0x12); + } + + TEST_CASE("getSignal") { + can_Message_t rxmsg; + + auto val = 0x1234; + std::memcpy(rxmsg.buf, &val, sizeof(val)); + + val = getSignal(rxmsg, 0, 16, true, 1, 0); + CHECK(val == 0x1234); + + val = getSignal(rxmsg, 0, 16, false, 1, 0); + CHECK(val == 0x3412); + + float myFloat = 1234.6789f; + std::memcpy(rxmsg.buf, &myFloat, sizeof(myFloat)); + auto floatVal = getSignal(rxmsg, 0, 32, true, 1, 0); + CHECK(floatVal == 1234.6789f); + } } \ No newline at end of file diff --git a/Firmware/Tupfile.lua b/Firmware/Tupfile.lua index e667d708..027db034 100644 --- a/Firmware/Tupfile.lua +++ b/Firmware/Tupfile.lua @@ -177,8 +177,7 @@ build{ 'communication/interface_can.cpp', 'communication/interface_i2c.cpp', 'fibre/cpp/protocol.cpp', - 'FreeRTOS-openocd.c', - 'Tests/test_runner.cpp' + 'FreeRTOS-openocd.c' }, includes={ 'Drivers/DRV8301', From b09e835647030c354beb729a85c2fb413a7fc4ad Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sun, 19 May 2019 21:18:46 +0200 Subject: [PATCH 60/72] Remove doctest from STM builds --- Firmware/MotorControl/main.cpp | 8 -------- 1 file changed, 8 deletions(-) diff --git a/Firmware/MotorControl/main.cpp b/Firmware/MotorControl/main.cpp index ed34ba20..88e3262b 100644 --- a/Firmware/MotorControl/main.cpp +++ b/Firmware/MotorControl/main.cpp @@ -126,16 +126,8 @@ void vApplicationIdleHook(void) { } } -#include int odrive_main(void) { -doctest::Context context; - -auto vals = context.run(); -while(vals){ - -} - #if HW_VERSION_MAJOR == 3 && HW_VERSION_MINOR >= 3 if (board_config.enable_i2c_instead_of_can) { // Set up the direction GPIO as input From 9503a9ce2981b21a9fdfa6151dbd1d8447f02dd6 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sun, 19 May 2019 21:19:30 +0200 Subject: [PATCH 61/72] Formatting pass on CAN files --- Firmware/communication/can_simple.cpp | 107 +++++++++-------------- Firmware/communication/can_simple.hpp | 80 ++++++++++------- Firmware/communication/interface_can.cpp | 6 +- Firmware/communication/interface_can.hpp | 6 +- ODrive_Workspace.code-workspace | 13 ++- 5 files changed, 109 insertions(+), 103 deletions(-) diff --git a/Firmware/communication/can_simple.cpp b/Firmware/communication/can_simple.cpp index d6327449..81502c8e 100644 --- a/Firmware/communication/can_simple.cpp +++ b/Firmware/communication/can_simple.cpp @@ -7,7 +7,7 @@ static const uint8_t NUM_NODE_ID_BITS = 6; static constexpr uint8_t NUM_CMD_ID_BITS = 11 - NUM_NODE_ID_BITS; -void CANSimple::handle_can_message(CAN_message_t& msg) { +void CANSimple::handle_can_message(can_Message_t& msg) { // This functional way of handling the messages is neat and is much cleaner from // a data security point of view, but it will require some tweaking to fix the syntax. // @@ -121,17 +121,17 @@ void CANSimple::handle_can_message(CAN_message_t& msg) { } } -void CANSimple::nmt_callback(Axis* axis, CAN_message_t& msg) { +void CANSimple::nmt_callback(Axis* axis, can_Message_t& msg) { // Not implemented } -void CANSimple::estop_callback(Axis* axis, CAN_message_t& msg) { +void CANSimple::estop_callback(Axis* axis, can_Message_t& msg) { axis->error_ |= Axis::ERROR_ESTOP_REQUESTED; } -void CANSimple::get_motor_error_callback(Axis* axis, CAN_message_t& msg) { +void CANSimple::get_motor_error_callback(Axis* axis, can_Message_t& msg) { if (msg.rtr) { - CAN_message_t txmsg; + can_Message_t txmsg; txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; txmsg.id += MSG_GET_MOTOR_ERROR; // heartbeat ID txmsg.isExt = false; @@ -146,9 +146,9 @@ void CANSimple::get_motor_error_callback(Axis* axis, CAN_message_t& msg) { } } -void CANSimple::get_encoder_error_callback(Axis* axis, CAN_message_t& msg) { +void CANSimple::get_encoder_error_callback(Axis* axis, can_Message_t& msg) { if (msg.rtr) { - CAN_message_t txmsg; + can_Message_t txmsg; txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; txmsg.id += MSG_GET_ENCODER_ERROR; // heartbeat ID txmsg.isExt = false; @@ -163,9 +163,9 @@ void CANSimple::get_encoder_error_callback(Axis* axis, CAN_message_t& msg) { } } -void CANSimple::get_sensorless_error_callback(Axis* axis, CAN_message_t& msg) { +void CANSimple::get_sensorless_error_callback(Axis* axis, can_Message_t& msg) { if (msg.rtr) { - CAN_message_t txmsg; + can_Message_t txmsg; txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; txmsg.id += MSG_GET_SENSORLESS_ERROR; // heartbeat ID txmsg.isExt = false; @@ -180,20 +180,20 @@ void CANSimple::get_sensorless_error_callback(Axis* axis, CAN_message_t& msg) { } } -void CANSimple::set_axis_nodeid_callback(Axis* axis, CAN_message_t& msg) { +void CANSimple::set_axis_nodeid_callback(Axis* axis, can_Message_t& msg) { axis->config_.can_node_id = msg.buf[0] & 0x3F; // Node ID bitmask } -void CANSimple::set_axis_requested_state_callback(Axis* axis, CAN_message_t& msg) { - axis->requested_state_ = static_cast(get_16bit_val(msg, 0)); +void CANSimple::set_axis_requested_state_callback(Axis* axis, can_Message_t& msg) { + axis->requested_state_ = static_cast(can_getSignal(msg, 0, 16, true, 1, 0)); } -void CANSimple::set_axis_startup_config_callback(Axis* axis, CAN_message_t& msg) { +void CANSimple::set_axis_startup_config_callback(Axis* axis, can_Message_t& msg) { // Not Implemented } -void CANSimple::get_encoder_estimates_callback(Axis* axis, CAN_message_t& msg) { +void CANSimple::get_encoder_estimates_callback(Axis* axis, can_Message_t& msg) { if (msg.rtr) { - CAN_message_t txmsg; + can_Message_t txmsg; txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; txmsg.id += MSG_GET_ENCODER_ESTIMATES; // heartbeat ID txmsg.isExt = false; @@ -222,9 +222,9 @@ void CANSimple::get_encoder_estimates_callback(Axis* axis, CAN_message_t& msg) { } } -void CANSimple::get_sensorless_estimates_callback(Axis* axis, CAN_message_t& msg) { +void CANSimple::get_sensorless_estimates_callback(Axis* axis, can_Message_t& msg) { if (msg.rtr) { - CAN_message_t txmsg; + can_Message_t txmsg; txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; txmsg.id += MSG_GET_SENSORLESS_ESTIMATES; // heartbeat ID txmsg.isExt = false; @@ -253,9 +253,9 @@ void CANSimple::get_sensorless_estimates_callback(Axis* axis, CAN_message_t& msg } } -void CANSimple::get_encoder_count_callback(Axis* axis, CAN_message_t& msg) { +void CANSimple::get_encoder_count_callback(Axis* axis, can_Message_t& msg) { if (msg.rtr) { - CAN_message_t txmsg; + can_Message_t txmsg; txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; txmsg.id += MSG_GET_ENCODER_COUNT; txmsg.isExt = false; @@ -275,46 +275,46 @@ void CANSimple::get_encoder_count_callback(Axis* axis, CAN_message_t& msg) { } } -void CANSimple::move_to_pos_callback(Axis* axis, CAN_message_t& msg) { - axis->controller_.move_to_pos(get_32bit_val(msg, 0)); +void CANSimple::move_to_pos_callback(Axis* axis, can_Message_t& msg) { + axis->controller_.move_to_pos(can_getSignal(msg, 0, 32, true, 1, 0)); } -void CANSimple::set_pos_setpoint_callback(Axis* axis, CAN_message_t& msg) { - axis->controller_.set_pos_setpoint(get_32bit_val(msg, 0), get_16bit_val(msg, 4) * 0.1f, get_16bit_val(msg, 6) * 0.01f); +void CANSimple::set_pos_setpoint_callback(Axis* axis, can_Message_t& msg) { + axis->controller_.set_pos_setpoint(can_getSignal(msg, 0, 32, true, 1, 0), can_getSignal(msg, 32, 16, true, 0.1f, 0), can_getSignal(msg, 48, 16, true, 0.01f, 0)); } -void CANSimple::set_vel_setpoint_callback(Axis* axis, CAN_message_t& msg) { - axis->controller_.set_vel_setpoint(get_32bit_val(msg, 0) * 0.01f, get_32bit_val(msg, 4) * 0.01f); +void CANSimple::set_vel_setpoint_callback(Axis* axis, can_Message_t& msg) { + axis->controller_.set_vel_setpoint(can_getSignal(msg, 0, 32, true, 0.01f, 0.0f), can_getSignal(msg, 4, 32, true, 0.01f, 0.0f)); } -void CANSimple::set_current_setpoint_callback(Axis* axis, CAN_message_t& msg) { - axis->controller_.set_current_setpoint(get_32bit_val(msg, 0) * 0.01f); +void CANSimple::set_current_setpoint_callback(Axis* axis, can_Message_t& msg) { + axis->controller_.set_current_setpoint(can_getSignal(msg, 0, 32, true, 0.01f, 0)); } -void CANSimple::set_vel_limit_callback(Axis* axis, CAN_message_t& msg) { - axis->controller_.config_.vel_limit = get_float(msg, 0); +void CANSimple::set_vel_limit_callback(Axis* axis, can_Message_t& msg) { + axis->controller_.config_.vel_limit = can_getSignal(msg, 0, 32, true, 1, 0); } -void CANSimple::start_anticogging_callback(Axis* axis, CAN_message_t& msg) { +void CANSimple::start_anticogging_callback(Axis* axis, can_Message_t& msg) { axis->controller_.start_anticogging_calibration(); } -void CANSimple::set_traj_vel_limit_callback(Axis* axis, CAN_message_t& msg) { - axis->trap_.config_.vel_limit = get_float(msg, 0); +void CANSimple::set_traj_vel_limit_callback(Axis* axis, can_Message_t& msg) { + axis->trap_.config_.vel_limit = can_getSignal(msg, 0, 32, true, 1, 0); } -void CANSimple::set_traj_accel_limits_callback(Axis* axis, CAN_message_t& msg) { - axis->trap_.config_.accel_limit = get_float(msg, 0); - axis->trap_.config_.decel_limit = get_float(msg, 4); +void CANSimple::set_traj_accel_limits_callback(Axis* axis, can_Message_t& msg) { + axis->trap_.config_.accel_limit = can_getSignal(msg, 0, 32, true, 1, 0); + axis->trap_.config_.decel_limit = can_getSignal(msg, 32, 32, true, 1, 0); } -void CANSimple::set_traj_A_per_css_callback(Axis* axis, CAN_message_t& msg) { - axis->trap_.config_.A_per_css = get_float(msg, 0); +void CANSimple::set_traj_A_per_css_callback(Axis* axis, can_Message_t& msg) { + axis->trap_.config_.A_per_css = can_getSignal(msg, 0, 32, true, 1, 0); } -void CANSimple::get_iq_callback(Axis* axis, CAN_message_t& msg) { +void CANSimple::get_iq_callback(Axis* axis, can_Message_t& msg) { if (msg.rtr) { - CAN_message_t txmsg; + can_Message_t txmsg; txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; txmsg.id += MSG_GET_IQ; txmsg.isExt = false; @@ -340,9 +340,9 @@ void CANSimple::get_iq_callback(Axis* axis, CAN_message_t& msg) { } } -void CANSimple::get_vbus_voltage_callback(Axis* axis, CAN_message_t& msg) { +void CANSimple::get_vbus_voltage_callback(Axis* axis, can_Message_t& msg) { if (msg.rtr) { - CAN_message_t txmsg; + can_Message_t txmsg; txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; txmsg.id += MSG_GET_VBUS_VOLTAGE; @@ -371,7 +371,7 @@ void CANSimple::get_vbus_voltage_callback(Axis* axis, CAN_message_t& msg) { } void CANSimple::send_heartbeat(Axis* axis) { - CAN_message_t txmsg; + can_Message_t txmsg; txmsg.id = axis->config_.can_node_id << NUM_CMD_ID_BITS; txmsg.id += MSG_ODRIVE_HEARTBEAT; // heartbeat ID txmsg.isExt = false; @@ -397,27 +397,4 @@ uint8_t CANSimple::get_node_id(uint32_t msgID) { uint8_t CANSimple::get_cmd_id(uint32_t msgID) { return (msgID & 0x01F); // Bottom 5 bits -} - -int16_t CANSimple::get_16bit_val(CAN_message_t& msg, uint8_t start_byte) { - int16_t retVal = 0; - if (msg.len >= start_byte && size_t(msg.len - start_byte) >= sizeof(retVal)) - std::memcpy(&retVal, &(msg.buf[start_byte]), sizeof(retVal)); - return retVal; -} - -int32_t CANSimple::get_32bit_val(CAN_message_t& msg, uint8_t start_byte) { - int32_t retVal = 0; - if (msg.len >= start_byte && size_t(msg.len - start_byte) >= sizeof(retVal)) - std::memcpy(&retVal, &(msg.buf[start_byte]), sizeof(retVal)); - return retVal; -} - -float CANSimple::get_float(CAN_message_t& msg, uint8_t start_byte) { - int32_t val = get_32bit_val(msg, start_byte); - float retVal; - - static_assert(sizeof retVal == sizeof val); - std::memcpy(&retVal, &val, sizeof val); // Sexier int32_t -> float cast that isn't UB - return retVal; } \ No newline at end of file diff --git a/Firmware/communication/can_simple.hpp b/Firmware/communication/can_simple.hpp index fd078c5a..9138e109 100644 --- a/Firmware/communication/can_simple.hpp +++ b/Firmware/communication/can_simple.hpp @@ -6,8 +6,8 @@ class CANSimple { public: enum { - MSG_CO_NMT_CTRL = 0x000, // CANOpen NMT Message REC - MSG_CO_HEARTBEAT_CMD = 0x700, // CANOpen NMT Heartbeat SEND + MSG_CO_NMT_CTRL = 0x000, // CANOpen NMT Message REC + MSG_CO_HEARTBEAT_CMD = 0x700, // CANOpen NMT Heartbeat SEND MSG_ODRIVE_HEARTBEAT = 0x001, MSG_ODRIVE_ESTOP, MSG_GET_MOTOR_ERROR, // Errors @@ -33,49 +33,67 @@ class CANSimple { MSG_GET_VBUS_VOLTAGE, }; - static void handle_can_message(CAN_message_t& msg); + static void handle_can_message(can_Message_t& msg); static void send_heartbeat(Axis* axis); private: - static void nmt_callback(Axis* axis, CAN_message_t& msg); - static void estop_callback(Axis* axis, CAN_message_t& msg); - static void get_motor_error_callback(Axis* axis, CAN_message_t& msg); - static void get_encoder_error_callback(Axis* axis, CAN_message_t& msg); - static void get_controller_error_callback(Axis* axis, CAN_message_t& msg); - static void get_sensorless_error_callback(Axis* axis, CAN_message_t& msg); - static void set_axis_nodeid_callback(Axis* axis, CAN_message_t& msg); - static void set_axis_requested_state_callback(Axis* axis, CAN_message_t& msg); - static void set_axis_startup_config_callback(Axis* axis, CAN_message_t& msg); - static void get_encoder_estimates_callback(Axis* axis, CAN_message_t& msg); - static void get_encoder_count_callback(Axis* axis, CAN_message_t& msg); - static void move_to_pos_callback(Axis* axis, CAN_message_t& msg); - static void set_pos_setpoint_callback(Axis* axis, CAN_message_t& msg); - static void set_vel_setpoint_callback(Axis* axis, CAN_message_t& msg); - static void set_current_setpoint_callback(Axis* axis, CAN_message_t& msg); - static void set_vel_limit_callback(Axis* axis, CAN_message_t& msg); - static void start_anticogging_callback(Axis* axis, CAN_message_t& msg); - static void set_traj_vel_limit_callback(Axis* axis, CAN_message_t& msg); - static void set_traj_accel_limits_callback(Axis* axis, CAN_message_t& msg); - static void set_traj_A_per_css_callback(Axis* axis, CAN_message_t& msg); - static void get_iq_callback(Axis* axis, CAN_message_t& msg); - static void get_sensorless_estimates_callback(Axis* axis, CAN_message_t& msg); - static void get_vbus_voltage_callback(Axis* axis, CAN_message_t& msg); - + static void nmt_callback(Axis* axis, can_Message_t& msg); + static void estop_callback(Axis* axis, can_Message_t& msg); + static void get_motor_error_callback(Axis* axis, can_Message_t& msg); + static void get_encoder_error_callback(Axis* axis, can_Message_t& msg); + static void get_controller_error_callback(Axis* axis, can_Message_t& msg); + static void get_sensorless_error_callback(Axis* axis, can_Message_t& msg); + static void set_axis_nodeid_callback(Axis* axis, can_Message_t& msg); + static void set_axis_requested_state_callback(Axis* axis, can_Message_t& msg); + static void set_axis_startup_config_callback(Axis* axis, can_Message_t& msg); + static void get_encoder_estimates_callback(Axis* axis, can_Message_t& msg); + static void get_encoder_count_callback(Axis* axis, can_Message_t& msg); + static void move_to_pos_callback(Axis* axis, can_Message_t& msg); + static void set_pos_setpoint_callback(Axis* axis, can_Message_t& msg); + static void set_vel_setpoint_callback(Axis* axis, can_Message_t& msg); + static void set_current_setpoint_callback(Axis* axis, can_Message_t& msg); + static void set_vel_limit_callback(Axis* axis, can_Message_t& msg); + static void start_anticogging_callback(Axis* axis, can_Message_t& msg); + static void set_traj_vel_limit_callback(Axis* axis, can_Message_t& msg); + static void set_traj_accel_limits_callback(Axis* axis, can_Message_t& msg); + static void set_traj_A_per_css_callback(Axis* axis, can_Message_t& msg); + static void get_iq_callback(Axis* axis, can_Message_t& msg); + static void get_sensorless_estimates_callback(Axis* axis, can_Message_t& msg); + static void get_vbus_voltage_callback(Axis* axis, can_Message_t& msg); // Utility functions static uint8_t get_node_id(uint32_t msgID); static uint8_t get_cmd_id(uint32_t msgID); - static int16_t get_16bit_val(CAN_message_t& msg, uint8_t start_byte); - static int32_t get_32bit_val(CAN_message_t& msg, uint8_t start_byte); - static float get_float(CAN_message_t& msg, uint8_t start_byte); + // Fetch a specific signal from the message // This functional way of handling the messages is neat and is much cleaner from // a data security point of view, but it will require some tweaking // - // const std::map> callback_map = { + // const std::map> callback_map = { // {0x000, std::bind(&CANSimple::heartbeat_callback, this, _1)} // }; }; + +#include +template +T can_getSignal(can_Message_t msg, uint8_t startBit, uint8_t length, bool isIntel, float factor, float offset) { + uint64_t tempVal = 0; + uint64_t mask = (1ULL << length) - 1; + + if (isIntel) { + std::memcpy(&tempVal, msg.buf, sizeof(tempVal)); + tempVal = (tempVal >> startBit) & mask; + } else { + std::reverse(std::begin(msg.buf), std::end(msg.buf)); + std::memcpy(&tempVal, msg.buf, sizeof(tempVal)); + tempVal = (tempVal >> (64 - startBit - length)) & mask; + } + + T retVal; + std::memcpy(&retVal, &tempVal, sizeof(T)); + return static_cast((retVal * factor) + offset); +} + #endif \ No newline at end of file diff --git a/Firmware/communication/interface_can.cpp b/Firmware/communication/interface_can.cpp index 44cd7e2d..251dec43 100644 --- a/Firmware/communication/interface_can.cpp +++ b/Firmware/communication/interface_can.cpp @@ -26,7 +26,7 @@ void ODriveCAN::can_server_thread() { for (;;) { uint32_t status = HAL_CAN_GetError(handle_); if (status == HAL_CAN_ERROR_NONE) { - CAN_message_t rxmsg; + can_Message_t rxmsg; osSemaphoreWait(sem_can, 10); // Poll every 10ms regardless of sempahore status while (available()) { @@ -86,7 +86,7 @@ bool ODriveCAN::start_can_server() { } // Send a CAN message on the bus -uint32_t ODriveCAN::write(CAN_message_t &txmsg) { +uint32_t ODriveCAN::write(can_Message_t &txmsg) { if (HAL_CAN_GetError(handle_) == HAL_CAN_ERROR_NONE) { CAN_TxHeaderTypeDef header; header.StdId = txmsg.id; @@ -110,7 +110,7 @@ uint32_t ODriveCAN::available() { return (HAL_CAN_GetRxFifoFillLevel(handle_, CAN_RX_FIFO0) + HAL_CAN_GetRxFifoFillLevel(handle_, CAN_RX_FIFO1)); } -bool ODriveCAN::read(CAN_message_t &rxmsg) { +bool ODriveCAN::read(can_Message_t &rxmsg) { CAN_RxHeaderTypeDef header; bool validRead = false; if (HAL_CAN_GetRxFifoFillLevel(handle_, CAN_RX_FIFO0) > 0) { diff --git a/Firmware/communication/interface_can.hpp b/Firmware/communication/interface_can.hpp index 68479a61..a19c953a 100644 --- a/Firmware/communication/interface_can.hpp +++ b/Firmware/communication/interface_can.hpp @@ -15,7 +15,7 @@ typedef struct { bool rtr = false; uint8_t len = 8; uint8_t buf[8] = {0, 0, 0, 0, 0, 0, 0, 0}; -} CAN_message_t; +} can_Message_t; // Anonymous enum for defining the most common CAN baud rates @@ -59,8 +59,8 @@ class ODriveCAN { // I/O Functions uint32_t available(); - uint32_t write(CAN_message_t &txmsg); - bool read(CAN_message_t &rxmsg); + uint32_t write(can_Message_t &txmsg); + bool read(can_Message_t &rxmsg); // Communication Protocol Handling auto make_protocol_definitions() { diff --git a/ODrive_Workspace.code-workspace b/ODrive_Workspace.code-workspace index d9644123..9c333d91 100644 --- a/ODrive_Workspace.code-workspace +++ b/ODrive_Workspace.code-workspace @@ -53,7 +53,18 @@ "chrono": "cpp", "condition_variable": "cpp", "future": "cpp", - "arm_math.h": "c" + "arm_math.h": "c", + "iostream": "cpp", + "cmath": "cpp", + "csignal": "cpp", + "cstdarg": "cpp", + "cstddef": "cpp", + "ctime": "cpp", + "unordered_map": "cpp", + "fstream": "cpp", + "iomanip": "cpp", + "optional": "cpp", + "sstream": "cpp" } } } From 93458d127f4e819ffc49aaec85f74872b46395d0 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sun, 19 May 2019 21:19:40 +0200 Subject: [PATCH 62/72] std::reverse requires C++17 --- Firmware/build.lua | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Firmware/build.lua b/Firmware/build.lua index d4c7aad4..016f6d8e 100644 --- a/Firmware/build.lua +++ b/Firmware/build.lua @@ -85,7 +85,7 @@ function GCCToolchain(prefix, builddir, compiler_flags, linker_flags) end return { compile_c = function(src, flags, includes, outputs) gcc_generic_compiler(prefix..'gcc -std=c99', compiler_flags, calculate_stack_usage, src, flags, includes, outputs) end, - compile_cpp = function(src, flags, includes, outputs) gcc_generic_compiler(prefix..'g++ -std=c++14', compiler_flags, calculate_stack_usage, src, flags, includes, outputs) end, + compile_cpp = function(src, flags, includes, outputs) gcc_generic_compiler(prefix..'g++ -std=c++17 -Wno-register', compiler_flags, calculate_stack_usage, src, flags, includes, outputs) end, compile_asm = function(src, flags, includes, outputs) gcc_generic_compiler(prefix..'gcc -x assembler-with-cpp', compiler_flags, false, src, flags, includes, outputs) end, link = function(objects, output_name) output_name = builddir..'/'..output_name From ca460aaa21f4246697e7f2d0609ba6a561b47a68 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sun, 19 May 2019 21:19:52 +0200 Subject: [PATCH 63/72] Add Tests folder to VSCode intellisense --- .gitignore | 2 ++ Firmware/.vscode/c_cpp_properties.json | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index ae3506ce..ac7997d4 100644 --- a/.gitignore +++ b/.gitignore @@ -41,3 +41,5 @@ tup.config /_site /.bundle + +*.exe diff --git a/Firmware/.vscode/c_cpp_properties.json b/Firmware/.vscode/c_cpp_properties.json index 2c96b614..12d9684c 100644 --- a/Firmware/.vscode/c_cpp_properties.json +++ b/Firmware/.vscode/c_cpp_properties.json @@ -19,6 +19,7 @@ "${workspaceRoot}/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS", "${workspaceRoot}/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/include", "${workspaceRoot}/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F", + "${workspaceFolder}/Tests", "C:/Tools/doctest/doctest" ], "defines": [ @@ -32,7 +33,7 @@ "__packed=\"__attribute__((__packed__))\"", "__GNUC__" ], - "intelliSenseMode": "clang-x64", + "intelliSenseMode": "gcc-x64", "compilerPath": "\"${ARM_GCC_ROOT}/bin/arm-none-eabi-gcc.exe\" -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -specs=nosys.specs -specs=nano.specs -u _printf_float -u _scanf_float", "cStandard": "c11", "cppStandard": "c++14" From 772c991274734fc2aba578e1621c75072e577027 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sun, 19 May 2019 21:24:09 +0200 Subject: [PATCH 64/72] can_Message_t is a struct, no need to typedef it --- Firmware/communication/interface_can.hpp | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/Firmware/communication/interface_can.hpp b/Firmware/communication/interface_can.hpp index a19c953a..c8506a8e 100644 --- a/Firmware/communication/interface_can.hpp +++ b/Firmware/communication/interface_can.hpp @@ -9,16 +9,23 @@ #define CAN_CLK_HZ (42000000) #define CAN_CLK_MHZ (42) -typedef struct { +struct can_Message_t { uint32_t id = 0x000; // 11-bit max is 0x7ff, 29-bit max is 0x1FFFFFFF bool isExt = false; bool rtr = false; uint8_t len = 8; uint8_t buf[8] = {0, 0, 0, 0, 0, 0, 0, 0}; -} can_Message_t; +} ; + +struct can_Signal_t { + uint8_t startBit = 0; + uint8_t length = 16; + bool isIntel = true; + float factor = 1.0f; + float offset = 0.0f; +}; // Anonymous enum for defining the most common CAN baud rates - enum { CAN_BAUD_125K = 125000, CAN_BAUD_250K = 250000, From c21fe04287387389617a887e9ab2e97c8e717f1b Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sun, 19 May 2019 21:24:41 +0200 Subject: [PATCH 65/72] Use recursive includepath --- Firmware/.vscode/c_cpp_properties.json | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/Firmware/.vscode/c_cpp_properties.json b/Firmware/.vscode/c_cpp_properties.json index 12d9684c..1886c707 100644 --- a/Firmware/.vscode/c_cpp_properties.json +++ b/Firmware/.vscode/c_cpp_properties.json @@ -3,23 +3,7 @@ { "name": "Win32", "includePath": [ - "${workspaceRoot}", - "${workspaceRoot}/fibre/cpp/include/**", - "${workspaceRoot}/MotorControl", - "${workspaceRoot}/communication", - "${workspaceRoot}/Drivers/DRV8301", - "${workspaceRoot}/communication", - "${workspaceRoot}/Board/v3/Inc", - "${workspaceRoot}/Board/v3/Drivers/CMSIS/Include", - "${workspaceRoot}/Board/v3/Drivers/CMSIS/Device/ST/STM32F4xx/Include", - "${workspaceRoot}/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc", - "${workspaceRoot}/Board/v3/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy", - "${workspaceRoot}/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Core/Inc", - "${workspaceRoot}/Board/v3/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc", - "${workspaceRoot}/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS", - "${workspaceRoot}/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/include", - "${workspaceRoot}/Board/v3/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F", - "${workspaceFolder}/Tests", + "${workspaceRoot}/**", "C:/Tools/doctest/doctest" ], "defines": [ From 6f2802746be36c17c9b50722fb145ab7afaea59b Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sun, 19 May 2019 22:23:27 +0200 Subject: [PATCH 66/72] Move can_getSignal to interface_can, and add can_setSignal --- Firmware/communication/can_simple.hpp | 17 -------- Firmware/communication/interface_can.hpp | 49 ++++++++++++++++++++++++ 2 files changed, 49 insertions(+), 17 deletions(-) diff --git a/Firmware/communication/can_simple.hpp b/Firmware/communication/can_simple.hpp index 9138e109..75553b87 100644 --- a/Firmware/communication/can_simple.hpp +++ b/Firmware/communication/can_simple.hpp @@ -76,24 +76,7 @@ class CANSimple { }; -#include -template -T can_getSignal(can_Message_t msg, uint8_t startBit, uint8_t length, bool isIntel, float factor, float offset) { - uint64_t tempVal = 0; - uint64_t mask = (1ULL << length) - 1; - if (isIntel) { - std::memcpy(&tempVal, msg.buf, sizeof(tempVal)); - tempVal = (tempVal >> startBit) & mask; - } else { - std::reverse(std::begin(msg.buf), std::end(msg.buf)); - std::memcpy(&tempVal, msg.buf, sizeof(tempVal)); - tempVal = (tempVal >> (64 - startBit - length)) & mask; - } - T retVal; - std::memcpy(&retVal, &tempVal, sizeof(T)); - return static_cast((retVal * factor) + offset); -} #endif \ No newline at end of file diff --git a/Firmware/communication/interface_can.hpp b/Firmware/communication/interface_can.hpp index c8506a8e..4b61cf38 100644 --- a/Firmware/communication/interface_can.hpp +++ b/Firmware/communication/interface_can.hpp @@ -86,6 +86,55 @@ class ODriveCAN { void set_baud_rate(uint32_t baudRate); }; +#include +template +T can_getSignal(can_Message_t msg, const uint8_t startBit, const uint8_t length, const bool isIntel, const float factor, const float offset) { + uint64_t tempVal = 0; + uint64_t mask = (1ULL << length) - 1; + + if (isIntel) { + std::memcpy(&tempVal, msg.buf, sizeof(tempVal)); + tempVal = (tempVal >> startBit) & mask; + } else { + std::reverse(std::begin(msg.buf), std::end(msg.buf)); + std::memcpy(&tempVal, msg.buf, sizeof(tempVal)); + tempVal = (tempVal >> (64 - startBit - length)) & mask; + } + + T retVal; + std::memcpy(&retVal, &tempVal, sizeof(T)); + return static_cast((retVal * factor) + offset); +} + +template +void can_setSignal(can_Message_t& msg, const T& val, const uint8_t startBit, const uint8_t length, const bool isIntel, const float factor, const float offset) { + T scaledVal = (val - offset) / factor; + uint64_t valAsBits = 0; + std::memcpy(&valAsBits, &scaledVal, sizeof(scaledVal)); + + uint64_t mask = (1ULL << length) - 1; + + if (isIntel) { + uint64_t data = 0; + std::memcpy(&data, msg.buf, sizeof(data)); + + data &= ~(mask << startBit); + data |= valAsBits << startBit; + + std::memcpy(msg.buf, &data, sizeof(data)); + } else { + uint64_t data = 0; + std::reverse(std::begin(msg.buf), std::end(msg.buf)); + std::memcpy(&data, msg.buf, sizeof(data)); + + data &= ~(mask << (64 - startBit - length)); + data |= valAsBits << (64 - startBit - length); + + std::memcpy(msg.buf, &data, sizeof(data)); + std::reverse(std::begin(msg.buf), std::end(msg.buf)); + } +} + DEFINE_ENUM_FLAG_OPERATORS(ODriveCAN::Error_t) #endif // __INTERFACE_CAN_HPP From 8d0f97125728a4a4afc749fec4e6881ea64c0f87 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sun, 19 May 2019 22:23:35 +0200 Subject: [PATCH 67/72] Add tests for can_setSignal --- Firmware/Tests/test_runner.cpp | 80 +++++++++++++++++++++++++++++----- 1 file changed, 70 insertions(+), 10 deletions(-) diff --git a/Firmware/Tests/test_runner.cpp b/Firmware/Tests/test_runner.cpp index dfaaf981..cd00e93f 100644 --- a/Firmware/Tests/test_runner.cpp +++ b/Firmware/Tests/test_runner.cpp @@ -13,6 +13,7 @@ using std::cout; using std::endl; + struct can_Message_t { uint32_t id = 0x000; // 11-bit max is 0x7ff, 29-bit max is 0x1FFFFFFF bool isExt = false; @@ -22,16 +23,18 @@ struct can_Message_t { }; struct can_Signal_t { - uint8_t startBit = 0; - uint8_t length = 16; - bool isIntel = true; - float factor = 1.0f; - float offset = 0.0f; + const uint8_t startBit; + const uint8_t length; + const bool isIntel; + const float factor; + const float offset; }; + + // Fetch a specific signal from the message template -T getSignal(can_Message_t msg, uint8_t startBit, uint8_t length, bool isIntel, float factor, float offset) { +T can_getSignal(can_Message_t msg, const uint8_t startBit, const uint8_t length, const bool isIntel, const float factor, const float offset) { uint64_t tempVal = 0; uint64_t mask = (1ULL << length) - 1; @@ -49,12 +52,45 @@ T getSignal(can_Message_t msg, uint8_t startBit, uint8_t length, bool isIntel, f return static_cast((retVal * factor) + offset); } +template +void can_setSignal(can_Message_t& msg, const T& val, const uint8_t startBit, const uint8_t length, const bool isIntel, const float factor, const float offset) { + T scaledVal = (val - offset) / factor; + uint64_t valAsBits = 0; + std::memcpy(&valAsBits, &scaledVal, sizeof(scaledVal)); + + uint64_t mask = (1ULL << length) - 1; + + if (isIntel) { + uint64_t data = 0; + std::memcpy(&data, msg.buf, sizeof(data)); + + data &= ~(mask << startBit); + data |= valAsBits << startBit; + + std::memcpy(msg.buf, &data, sizeof(data)); + } else { + uint64_t data = 0; + std::reverse(std::begin(msg.buf), std::end(msg.buf)); + std::memcpy(&data, msg.buf, sizeof(data)); + + data &= ~(mask << (64 - startBit - length)); + data |= valAsBits << (64 - startBit - length); + + std::memcpy(msg.buf, &data, sizeof(data)); + std::reverse(std::begin(msg.buf), std::end(msg.buf)); + } +} + // template // T can_getSignal(can_Message_t msg, can_Signal_t signal){ // return can_getSignal(msg, signal.startBit, signal.length, signal.isIntel, signal.factor, signal.offset); // } -TEST_SUITE("getSignal") { +TEST_CASE("fake"){ + cout << endl; +} + +TEST_SUITE("CAN Functions") { TEST_CASE("reverse") { can_Message_t rxmsg; rxmsg.id = 0x000; @@ -76,15 +112,39 @@ TEST_SUITE("getSignal") { auto val = 0x1234; std::memcpy(rxmsg.buf, &val, sizeof(val)); - val = getSignal(rxmsg, 0, 16, true, 1, 0); + val = can_getSignal(rxmsg, 0, 16, true, 1, 0); CHECK(val == 0x1234); - val = getSignal(rxmsg, 0, 16, false, 1, 0); + val = can_getSignal(rxmsg, 0, 16, false, 1, 0); CHECK(val == 0x3412); float myFloat = 1234.6789f; std::memcpy(rxmsg.buf, &myFloat, sizeof(myFloat)); - auto floatVal = getSignal(rxmsg, 0, 32, true, 1, 0); + auto floatVal = can_getSignal(rxmsg, 0, 32, true, 1, 0); CHECK(floatVal == 1234.6789f); } + + TEST_CASE("setSignal") { + can_Message_t txmsg; + + can_setSignal(txmsg, 0x1234, 0, 16, true, 1.0f, 0.0f); + CHECK(can_getSignal(txmsg, 0, 16, true, 1.0f, 0.0f) == 0x1234); + + can_setSignal(txmsg, 0xABCD, 16, 16, true, 1.0f, 0.0f); + CHECK(can_getSignal(txmsg, 0, 16, true, 1.0f, 0.0f) == 0x1234); + CHECK(can_getSignal(txmsg, 16, 16, true, 1.0f, 0.0f) == 0xABCD); + + can_setSignal(txmsg, 1234.5678f, 32, 32, true, 1.0f, 0.0f); + CHECK(can_getSignal(txmsg, 0, 16, true, 1.0f, 0.0f) == 0x1234); + CHECK(can_getSignal(txmsg, 16, 16, true, 1.0f, 0.0f) == 0xABCD); + CHECK(can_getSignal(txmsg, 32, 32, true, 1.0f, 0.0f)); + + can_setSignal(txmsg, 0x1234, 0, 16, false, 1.0f, 0.0f); + CHECK(can_getSignal(txmsg, 0, 16, false, 1.0f, 0.0f) == 0x1234); + CHECK(can_getSignal(txmsg, 16, 16, true, 1.0f, 0.0f) == 0xABCD); + CHECK(can_getSignal(txmsg, 32, 32, true, 1.0f, 0.0f)); + + can_setSignal(txmsg, 234981.0f, 12, 32, false, 2.0f, 1.1f); + CHECK(can_getSignal(txmsg, 12, 32, false, 2.0f, 1.1f) == 234981.0f); + } } \ No newline at end of file From ae0a2a1923b4c464bba8f0b90c35bcb9eb0bf6f9 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sun, 19 May 2019 22:24:13 +0200 Subject: [PATCH 68/72] can_Signal_t should use const, force initialization. --- Firmware/communication/interface_can.hpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Firmware/communication/interface_can.hpp b/Firmware/communication/interface_can.hpp index 4b61cf38..58c32d76 100644 --- a/Firmware/communication/interface_can.hpp +++ b/Firmware/communication/interface_can.hpp @@ -18,11 +18,11 @@ struct can_Message_t { } ; struct can_Signal_t { - uint8_t startBit = 0; - uint8_t length = 16; - bool isIntel = true; - float factor = 1.0f; - float offset = 0.0f; + const uint8_t startBit; + const uint8_t length; + const bool isIntel; + const float factor; + const float offset; }; // Anonymous enum for defining the most common CAN baud rates From 4f7f35e753d3e72890f704f6f35aedac7cfbbeac Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sun, 19 May 2019 22:24:24 +0200 Subject: [PATCH 69/72] Remove explicit includes from flylint --- ODrive_Workspace.code-workspace | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/ODrive_Workspace.code-workspace b/ODrive_Workspace.code-workspace index 9c333d91..a131f5cb 100644 --- a/ODrive_Workspace.code-workspace +++ b/ODrive_Workspace.code-workspace @@ -11,14 +11,7 @@ } ], "settings": { - "c-cpp-flylint.cppcheck.includePaths": [ - "${workspaceRoot}", - "${workspaceRoot}/fibre/cpp/include/fibre", - "${workspaceRoot}/MotorControl", - "${workspaceRoot}/Drivers/DRV8301", - "${workspaceRoot}/communication" - ], - "c-cpp-flylint.cppcheck.standard": ["c99","c++14"], + "c-cpp-flylint.cppcheck.standard": ["c99","c++17"], "files.associations": { "memory": "cpp", "utility": "cpp", From 21b9758198158f3351f89b05082cf06eb124856e Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sun, 19 May 2019 22:24:40 +0200 Subject: [PATCH 70/72] Add AlignConsecutiveAssignments to formatting rules --- Firmware/.vscode/settings.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Firmware/.vscode/settings.json b/Firmware/.vscode/settings.json index 63c1463b..ffb1469b 100644 --- a/Firmware/.vscode/settings.json +++ b/Firmware/.vscode/settings.json @@ -1,5 +1,5 @@ { - "C_Cpp.clang_format_style": "{ BasedOnStyle: Google, IndentWidth: 4, ColumnLimit: 0 }", + "C_Cpp.clang_format_style": "{ BasedOnStyle: Google, IndentWidth: 4, ColumnLimit: 0, AlignConsecutiveAssignments: true }", "C_Cpp.intelliSenseEngine": "Default", "C_Cpp.intelliSenseEngineFallback": "Disabled", "files.exclude": { From ea7bd1ebc31b1e8e7a05b03ebd55d6082a8dc36f Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sun, 19 May 2019 22:38:28 +0200 Subject: [PATCH 71/72] Add can_get/set function that take signal objects --- Firmware/Tests/test_runner.cpp | 19 ++++++++++++------- Firmware/communication/interface_can.hpp | 10 ++++++++++ 2 files changed, 22 insertions(+), 7 deletions(-) diff --git a/Firmware/Tests/test_runner.cpp b/Firmware/Tests/test_runner.cpp index cd00e93f..560cb5c7 100644 --- a/Firmware/Tests/test_runner.cpp +++ b/Firmware/Tests/test_runner.cpp @@ -81,21 +81,26 @@ void can_setSignal(can_Message_t& msg, const T& val, const uint8_t startBit, con } } -// template -// T can_getSignal(can_Message_t msg, can_Signal_t signal){ -// return can_getSignal(msg, signal.startBit, signal.length, signal.isIntel, signal.factor, signal.offset); -// } +template +T can_getSignal(can_Message_t msg, const can_Signal_t& signal) { + return can_getSignal(msg, signal.startBit, signal.length, signal.isIntel, signal.factor, signal.offset); +} -TEST_CASE("fake"){ +template +void can_setSignal(can_Message_t& msg, const T& val, const can_Signal_t& signal) { + can_setSignal(msg, val, signal.startBit, signal.length, signal.isIntel, signal.factor, signal.offset); +} + +TEST_CASE("fake") { cout << endl; } TEST_SUITE("CAN Functions") { TEST_CASE("reverse") { can_Message_t rxmsg; - rxmsg.id = 0x000; + rxmsg.id = 0x000; rxmsg.isExt = false; - rxmsg.len = 8; + rxmsg.len = 8; rxmsg.buf[0] = 0x12; rxmsg.buf[1] = 0x34; diff --git a/Firmware/communication/interface_can.hpp b/Firmware/communication/interface_can.hpp index 58c32d76..28e3987b 100644 --- a/Firmware/communication/interface_can.hpp +++ b/Firmware/communication/interface_can.hpp @@ -135,6 +135,16 @@ void can_setSignal(can_Message_t& msg, const T& val, const uint8_t startBit, con } } +template +T can_getSignal(can_Message_t msg, const can_Signal_t& signal) { + return can_getSignal(msg, signal.startBit, signal.length, signal.isIntel, signal.factor, signal.offset); +} + +template +void can_setSignal(can_Message_t& msg, const T& val, const can_Signal_t& signal) { + can_setSignal(msg, val, signal.startBit, signal.length, signal.isIntel, signal.factor, signal.offset); +} + DEFINE_ENUM_FLAG_OPERATORS(ODriveCAN::Error_t) #endif // __INTERFACE_CAN_HPP From 9b86d0a63856e7b41bd621e7a32a81a92ee19bb5 Mon Sep 17 00:00:00 2001 From: Paul Guenette Date: Sun, 19 May 2019 22:39:04 +0200 Subject: [PATCH 72/72] Formatting in test_runner.cpp --- Firmware/Tests/test_runner.cpp | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/Firmware/Tests/test_runner.cpp b/Firmware/Tests/test_runner.cpp index 560cb5c7..3214f278 100644 --- a/Firmware/Tests/test_runner.cpp +++ b/Firmware/Tests/test_runner.cpp @@ -15,10 +15,10 @@ using std::cout; using std::endl; struct can_Message_t { - uint32_t id = 0x000; // 11-bit max is 0x7ff, 29-bit max is 0x1FFFFFFF - bool isExt = false; - bool rtr = false; - uint8_t len = 8; + uint32_t id = 0x000; // 11-bit max is 0x7ff, 29-bit max is 0x1FFFFFFF + bool isExt = false; + bool rtr = false; + uint8_t len = 8; uint8_t buf[8] = {0, 0, 0, 0, 0, 0, 0, 0}; }; @@ -30,13 +30,11 @@ struct can_Signal_t { const float offset; }; - - // Fetch a specific signal from the message template T can_getSignal(can_Message_t msg, const uint8_t startBit, const uint8_t length, const bool isIntel, const float factor, const float offset) { uint64_t tempVal = 0; - uint64_t mask = (1ULL << length) - 1; + uint64_t mask = (1ULL << length) - 1; if (isIntel) { std::memcpy(&tempVal, msg.buf, sizeof(tempVal)); @@ -54,7 +52,7 @@ T can_getSignal(can_Message_t msg, const uint8_t startBit, const uint8_t length, template void can_setSignal(can_Message_t& msg, const T& val, const uint8_t startBit, const uint8_t length, const bool isIntel, const float factor, const float offset) { - T scaledVal = (val - offset) / factor; + T scaledVal = (val - offset) / factor; uint64_t valAsBits = 0; std::memcpy(&valAsBits, &scaledVal, sizeof(scaledVal));