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https://github.com/gatieme/LDD-LinuxDeviceDrivers.git
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进程调度之优先级详解...
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gatieme
@@ -502,5 +502,13 @@ finish_task_switch完成一些清理工作, 使得能够正确的释放锁, 但
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-------
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switch_mm()进行用户空间的切换, 更确切地说, 是切换地址转换表(pgd)， 由于pgd包括内核虚拟地址空间和用户虚拟地址空间地址映射, linux内核把进程的整个虚拟地址空间分成两个部分, 一部分是内核虚拟地址空间, 另外一部分是内核虚拟地址空间, 各个进程的虚拟地址空间各不相同, 但是却共用了同样的内核地址空间, 这样在进程切换的时候, 就只需要切换虚拟地址空间的用户空间部分.
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每个进程都有其自身的页目录表pgd
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进程本身尚未切换, 而存储管理机制的页目录指针cr3却已经切换了，这样不会造成问题吗?不会的，因为这个时候CPU在系统空间运行，而所有进程的页目录表中与系统空间对应的目录项都指向相同的页表，所以，不管切换到哪一个进程的页目录表都一样，受影响的只是用户空间，系统空间的映射则永远不变
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##5 switch_to切换寄存器状态和内核栈详细分析
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-------
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@@ -0,0 +1,164 @@
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// http://lxr.free-electrons.com/source/arch/x86/include/asm/mmu_context.h?v=4.6#L118
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static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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unsigned cpu = smp_processor_id();
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if (likely(prev != next))
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{
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#ifdef CONFIG_SMP
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this_cpu_write(cpu_tlbstate.state, TLBSTATE_OK);
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this_cpu_write(cpu_tlbstate.active_mm, next);
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#endif
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//
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cpumask_set_cpu(cpu, mm_cpumask(next));
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/*
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* Re-load page tables.
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*
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* This logic has an ordering constraint:
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*
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* CPU 0: Write to a PTE for 'next'
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* CPU 0: load bit 1 in mm_cpumask. if nonzero, send IPI.
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* CPU 1: set bit 1 in next's mm_cpumask
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* CPU 1: load from the PTE that CPU 0 writes (implicit)
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*
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* We need to prevent an outcome in which CPU 1 observes
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* the new PTE value and CPU 0 observes bit 1 clear in
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* mm_cpumask. (If that occurs, then the IPI will never
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* be sent, and CPU 0's TLB will contain a stale entry.)
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*
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* The bad outcome can occur if either CPU's load is
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* reordered before that CPU's store, so both CPUs must
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* execute full barriers to prevent this from happening.
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*
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* Thus, switch_mm needs a full barrier between the
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* store to mm_cpumask and any operation that could load
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* from next->pgd. TLB fills are special and can happen
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* due to instruction fetches or for no reason at all,
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* and neither LOCK nor MFENCE orders them.
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* Fortunately, load_cr3() is serializing and gives the
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* ordering guarantee we need.
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*
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*/
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load_cr3(next->pgd);
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trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
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/* Stop flush ipis for the previous mm */
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cpumask_clear_cpu(cpu, mm_cpumask(prev));
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/* Load per-mm CR4 state */
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load_mm_cr4(next);
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#ifdef CONFIG_MODIFY_LDT_SYSCALL
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/*
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* Load the LDT, if the LDT is different.
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*
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* It's possible that prev->context.ldt doesn't match
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* the LDT register. This can happen if leave_mm(prev)
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* was called and then modify_ldt changed
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* prev->context.ldt but suppressed an IPI to this CPU.
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* In this case, prev->context.ldt != NULL, because we
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* never set context.ldt to NULL while the mm still
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* exists. That means that next->context.ldt !=
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* prev->context.ldt, because mms never share an LDT.
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*/
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if (unlikely(prev->context.ldt != next->context.ldt))
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load_mm_ldt(next);
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#endif
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}
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#ifdef CONFIG_SMP
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else {
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this_cpu_write(cpu_tlbstate.state, TLBSTATE_OK);
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BUG_ON(this_cpu_read(cpu_tlbstate.active_mm) != next);
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if (!cpumask_test_cpu(cpu, mm_cpumask(next))) {
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/*
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* On established mms, the mm_cpumask is only changed
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* from irq context, from ptep_clear_flush() while in
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* lazy tlb mode, and here. Irqs are blocked during
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* schedule, protecting us from simultaneous changes.
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*/
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cpumask_set_cpu(cpu, mm_cpumask(next));
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/*
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* We were in lazy tlb mode and leave_mm disabled
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* tlb flush IPI delivery. We must reload CR3
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* to make sure to use no freed page tables.
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*
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* As above, load_cr3() is serializing and orders TLB
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* fills with respect to the mm_cpumask write.
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*/
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load_cr3(next->pgd);
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trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
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load_mm_cr4(next);
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load_mm_ldt(next);
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}
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}
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#endif
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}
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// http://lxr.free-electrons.com/source/arch/arm/include/asm/mmu_context.h?v=4.6#L126
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/*
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* This is the actual mm switch as far as the scheduler
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* is concerned. No registers are touched. We avoid
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* calling the CPU specific function when the mm hasn't
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* actually changed.
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*/
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static inline void
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switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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#ifdef CONFIG_MMU
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unsigned int cpu = smp_processor_id();
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/*
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* __sync_icache_dcache doesn't broadcast the I-cache invalidation,
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* so check for possible thread migration and invalidate the I-cache
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* if we're new to this CPU.
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*/
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if (cache_ops_need_broadcast() &&
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!cpumask_empty(mm_cpumask(next)) &&
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!cpumask_test_cpu(cpu, mm_cpumask(next)))
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__flush_icache_all();
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if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {
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check_and_switch_context(next, tsk);
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if (cache_is_vivt())
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cpumask_clear_cpu(cpu, mm_cpumask(prev));
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}
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#endif
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}
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// http://lxr.free-electrons.com/source/arch/arm64/include/asm/mmu_context.h?v=4.6#L183
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/*
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* This is the actual mm switch as far as the scheduler
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* is concerned. No registers are touched. We avoid
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* calling the CPU specific function when the mm hasn't
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* actually changed.
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*/
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static inline void
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switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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unsigned int cpu = smp_processor_id();
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if (prev == next)
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return;
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/*
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* init_mm.pgd does not contain any user mappings and it is always
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* active for kernel addresses in TTBR1. Just set the reserved TTBR0.
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*/
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if (next == &init_mm) {
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cpu_set_reserved_ttbr0();
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return;
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}
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check_and_switch_context(next, cpu);
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}
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@@ -0,0 +1,153 @@
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// http://lxr.free-electrons.com/source/arch/x86/include/asm/switch_to.h?v=4.6#L27
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// http://lxr.free-electrons.com/source/arch/x86/include/asm/switch_to.h?v=4.6#L102
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#ifdef CONFIG_X86_32
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#ifdef CONFIG_CC_STACKPROTECTOR
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#define __switch_canary \
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"movl %P[task_canary](%[next]), %%ebx\n\t" \
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"movl %%ebx, "__percpu_arg([stack_canary])"\n\t"
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#define __switch_canary_oparam \
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, [stack_canary] "=m" (stack_canary.canary)
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#define __switch_canary_iparam \
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, [task_canary] "i" (offsetof(struct task_struct, stack_canary))
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#else /* CC_STACKPROTECTOR */
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#define __switch_canary
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#define __switch_canary_oparam
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#define __switch_canary_iparam
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#endif /* CC_STACKPROTECTOR */
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/*
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* Saving eflags is important. It switches not only IOPL between tasks,
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* it also protects other tasks from NT leaking through sysenter etc.
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*/
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#define switch_to(prev, next, last) \
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do { \
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/* \
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* Context-switching clobbers all registers, so we clobber \
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* them explicitly, via unused output variables. \
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* (EAX and EBP is not listed because EBP is saved/restored \
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* explicitly for wchan access and EAX is the return value of \
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* __switch_to()) \
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*/ \
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unsigned long ebx, ecx, edx, esi, edi; \
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\
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asm volatile("pushfl\n\t" /* save flags */ \
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"pushl %%ebp\n\t" /* save EBP */ \
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"movl %%esp,%[prev_sp]\n\t" /* save ESP */ \
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"movl %[next_sp],%%esp\n\t" /* restore ESP */ \
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"movl $1f,%[prev_ip]\n\t" /* save EIP */ \
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"pushl %[next_ip]\n\t" /* restore EIP */ \
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__switch_canary \
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"jmp __switch_to\n" /* regparm call */ \
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"1:\t" \
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"popl %%ebp\n\t" /* restore EBP */ \
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"popfl\n" /* restore flags */ \
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\
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/* output parameters */ \
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: [prev_sp] "=m" (prev->thread.sp), \
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[prev_ip] "=m" (prev->thread.ip), \
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"=a" (last), \
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\
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/* clobbered output registers: */ \
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"=b" (ebx), "=c" (ecx), "=d" (edx), \
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"=S" (esi), "=D" (edi) \
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\
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__switch_canary_oparam \
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\
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/* input parameters: */ \
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: [next_sp] "m" (next->thread.sp), \
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[next_ip] "m" (next->thread.ip), \
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\
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/* regparm parameters for __switch_to(): */ \
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[prev] "a" (prev), \
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[next] "d" (next) \
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\
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__switch_canary_iparam \
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\
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: /* reloaded segment registers */ \
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"memory"); \
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} while (0)
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#else /* CONFIG_X86_32 */
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/* frame pointer must be last for get_wchan */
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#define SAVE_CONTEXT "pushq %%rbp ; movq %%rsi,%%rbp\n\t"
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#define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp\t"
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#define __EXTRA_CLOBBER \
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, "rcx", "rbx", "rdx", "r8", "r9", "r10", "r11", \
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"r12", "r13", "r14", "r15", "flags"
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#ifdef CONFIG_CC_STACKPROTECTOR
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#define __switch_canary \
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"movq %P[task_canary](%%rsi),%%r8\n\t" \
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"movq %%r8,"__percpu_arg([gs_canary])"\n\t"
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#define __switch_canary_oparam \
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, [gs_canary] "=m" (irq_stack_union.stack_canary)
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#define __switch_canary_iparam \
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, [task_canary] "i" (offsetof(struct task_struct, stack_canary))
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#else /* CC_STACKPROTECTOR */
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#define __switch_canary
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#define __switch_canary_oparam
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#define __switch_canary_iparam
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#endif /* CC_STACKPROTECTOR */
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/*
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* There is no need to save or restore flags, because flags are always
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* clean in kernel mode, with the possible exception of IOPL. Kernel IOPL
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* has no effect.
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*/
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#define switch_to(prev, next, last) \
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asm volatile(SAVE_CONTEXT \
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"movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */ \
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"movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */ \
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"call __switch_to\n\t" \
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"movq "__percpu_arg([current_task])",%%rsi\n\t" \
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__switch_canary \
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"movq %P[thread_info](%%rsi),%%r8\n\t" \
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"movq %%rax,%%rdi\n\t" \
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"testl %[_tif_fork],%P[ti_flags](%%r8)\n\t" \
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"jnz ret_from_fork\n\t" \
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RESTORE_CONTEXT \
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: "=a" (last) \
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__switch_canary_oparam \
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: [next] "S" (next), [prev] "D" (prev), \
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[threadrsp] "i" (offsetof(struct task_struct, thread.sp)), \
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[ti_flags] "i" (offsetof(struct thread_info, flags)), \
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[_tif_fork] "i" (_TIF_FORK), \
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[thread_info] "i" (offsetof(struct task_struct, stack)), \
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[current_task] "m" (current_task) \
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__switch_canary_iparam \
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: "memory", "cc" __EXTRA_CLOBBER)
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#endif /* CONFIG_X86_32 */
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// http://lxr.free-electrons.com/source/arch/arm/include/asm/switch_to.h?v=4.6#L25
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/*
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* For v7 SMP cores running a preemptible kernel we may be pre-empted
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* during a TLB maintenance operation, so execute an inner-shareable dsb
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* to ensure that the maintenance completes in case we migrate to another
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* CPU.
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*/
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#if defined(CONFIG_PREEMPT) && defined(CONFIG_SMP) && defined(CONFIG_CPU_V7)
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#define __complete_pending_tlbi() dsb(ish)
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#else
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#define __complete_pending_tlbi()
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#endif
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/*
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* switch_to(prev, next) should switch from task `prev' to `next'
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* `prev' will never be the same as `next'. schedule() itself
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* contains the memory barrier to tell GCC not to cache `current'.
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*/
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extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
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#define switch_to(prev,next,last) \
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do { \
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__complete_pending_tlbi(); \
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last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \
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} while (0)
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